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spi: imx: fix ecspi mode setup

PATCH New Andrew Y. Kuksov 2 participants 5 messages Jul 14, 2015 – Oct 22, 2015

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#0 lore raw

PATCH 1/1 spi: imx: fix ecspi mode setup

Fixed problem with setting spi mode 0 or 1 after setting mode 2 or 3

---
 drivers/spi/spi-imx.c | 7 +++++++
 1 file changed, 7 insertions(+)
drivers/spi/spi-imx.c +7 -0
index eb7d3a6..36b6ece 100644
@@ -335,13 +335,20 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
 
 	if (config->mode & SPI_CPHA)
 		cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
+	else
+		cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
 
 	if (config->mode & SPI_CPOL) {
 		cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
 		cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
+	} else {
+		cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
+		cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
 	}
 	if (config->mode & SPI_CS_HIGH)
 		cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
+	else
+		cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(config->cs);
 
 	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 	writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
Signature · 1 line
2.1.0
maintainer
#1 lore raw

PATCH 1/1 spi: imx: fix ecspi mode setup

Quoted 1 line · Andrew Y. Kuksov

Fixed problem with setting spi mode 0 or 1 after setting mode 2 or 3

What is the problem and how does this change fix it (this information
should be in the changelog)?
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#2 lore raw

PATCH 1/1 spi: imx: fix ecspi mode setup

Quoted 3 lines
Quoted 1 line

Fixed problem with setting spi mode 0 or 1 after setting mode 2 or 3

What is the problem and how does this change fix it (this information should be in the changelog)?

SPI_MODE_0 and SPI_MODE_1 requires clock low when inactive. SPI_MODE_2 and SPI_MODE_3 requires clk high when inactive.
Currently driver can just set bits in fields SCLK_PHA (SPI Clock/Data Phase Control), SCLK_POL (SPI Clock Polarity Control), SCLK_CTL (controls the inactive state of SCLK) ans SS_POL (SPI SS Polarity Select) of ECSPIx_CONFIGREG register.
This patch allows driver to clear corresponding bits in these fields.

maintainer
#3 lore raw

PATCH 1/1 spi: imx: fix ecspi mode setup

Quoted 5 lines · Andrew Kuksov
Quoted 4 lines
Quoted 1 line

Fixed problem with setting spi mode 0 or 1 after setting mode 2 or 3

What is the problem and how does this change fix it (this information should be in the changelog)?

Quoted 7 lines

SPI_MODE_0 and SPI_MODE_1 requires clock low when inactive. SPI_MODE_2 and SPI_MODE_3 requires clk high when inactive.
Currently driver can just set bits in fields SCLK_PHA (SPI Clock/Data Phase Control), SCLK_POL (SPI Clock Polarity Control), SCLK_CTL (controls the inactive state of SCLK) ans SS_POL (SPI SS Polarity Select) of ECSPIx_CONFIGREG register.
This patch allows driver to clear corresponding bits in these fields.

Please provide a patch with a changelog more like this...
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maintainer
#4 lore raw

PATCH 1/1 spi: imx: fix ecspi mode setup

In reply to Andrew Kuksov
Quoted 5 lines · Andrew Kuksov
Quoted 4 lines
Quoted 1 line

Fixed problem with setting spi mode 0 or 1 after setting mode 2 or 3

What is the problem and how does this change fix it (this information should be in the changelog)?

Quoted 7 lines

SPI_MODE_0 and SPI_MODE_1 requires clock low when inactive. SPI_MODE_2 and SPI_MODE_3 requires clk high when inactive.
Currently driver can just set bits in fields SCLK_PHA (SPI Clock/Data Phase Control), SCLK_POL (SPI Clock Polarity Control), SCLK_CTL (controls the inactive state of SCLK) ans SS_POL (SPI SS Polarity Select) of ECSPIx_CONFIGREG register.
This patch allows driver to clear corresponding bits in these fields.

OK... when I was asking for this to be in the changelog what I meant
was that you should send a new patch with a changelog including the
relevant description. I've done that by hand now.
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