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Disas QOMification, round 2

PATCH Applied Peter Crosthwaite 9 participants 25 messages Jul 12, 2015 – Aug 28, 2015

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Peter Crosthwaite

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#0 lore raw

cover Disas QOMification, round 2

Continue QOMifying target-specific disassembly. Convert all arches except for X86 and PPC. They will be round 3 and are non-trivial.

This brings us close to no arch-specific code in disas.c allow conversion to common-obj and preparing these arches for inclusion in multi-arch.

Tested to various degrees depending on image availability. Arches with bios's are the easiest, others have sample test images available. Some that accept binary blobs as code I half-tested with random data as code. Moxie has no testing. Status:

s390: Tested with bios
moxie: No testing (requires an elf)
m68k: Tested with random code
sparc,sparc64: Tested with bios
lm32: Tested with random code
sh4: Tested with sample image
mips: Tested with sample image
alpha: Tested with bios

Peter Crosthwaite (8):
disas: s390x: QOMify target specific disas setup
disas: moxie: QOMify target specific disas setup
disas: m68k: QOMify target specific disas setup
disas: sparc: QOMify target specific disas setup
disas: lm32: QOMify target specific disas setup
disas: sh4: QOMify target specific disas setup
disas: mips: QOMify target specific disas setup
disas: alpha: QOMify target specific disas setup

 disas.c            | 55 ------------------------------------------------------
 target-alpha/cpu.c |  8 ++++++++
 target-lm32/cpu.c  |  8 ++++++++
 target-m68k/cpu.c  |  7 +++++++
 target-mips/cpu.c  | 10 ++++++++++
 target-moxie/cpu.c |  7 +++++++
 target-s390x/cpu.c |  8 ++++++++
 target-sh4/cpu.c   |  8 ++++++++
 target-sparc/cpu.c |  9 +++++++++
 9 files changed, 65 insertions(+), 55 deletions(-)
Signature · 1 line
1.9.1
author
#1 lore raw

PATCH 1/8 disas: s390x: QOMify target specific disas setup

From: Peter Crosthwaite <[email protected]>

Move the target_disas() s390 specifics to the QOM disas_set_info hook and delete the #ifdef specific code in disas.c.

Cc Richard Henderson <[email protected]>
Cc Alexander Graf <[email protected]>
Signed-off-by Peter Crosthwaite <[email protected]>

---
Testing:

$ ./s390x-softmmu/qemu-system-s390x -nographic -d in_asm -S 2> err
QEMU 2.3.90 monitor - type 'help' for more information
(qemu) info register
unknown command: 'register'
(qemu) info registers
PSW=mask 0000000180000000 addr 0000000007e00468 cc 00
...
(qemu) x/i 0x7e00468
0x0000000007e00468:  larl   %r15,0x7e0d000
(qemu) x/i 0x7e0046e
0x0000000007e0046e:  larl   %r6,0x7e15000
(qemu) c
(qemu) No virtio-blk device found!
$ more err
IN:
0x0000000007e00468:  larl   %r15,0x7e0d000
0x0000000007e0046e:  larl   %r6,0x7e15000
0x0000000007e00474:  stg    %r7,0(%r6)
0x0000000007e0047a:  j  0x7e0052c
...
---
 disas.c            | 6 ------
 target-s390x/cpu.c | 8 ++++++++
 2 files changed, 8 insertions(+), 6 deletions(-)
disas.c +0 -6
index 69a6066..e62c934 100644
@@ -257,9 +257,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
 #elif defined(TARGET_ALPHA)
     s.info.mach = bfd_mach_alpha_ev6;
     s.info.print_insn = print_insn_alpha;
-#elif defined(TARGET_S390X)
-    s.info.mach = bfd_mach_s390_64;
-    s.info.print_insn = print_insn_s390;
 #elif defined(TARGET_MOXIE)
     s.info.mach = bfd_arch_moxie;
     s.info.print_insn = print_insn_moxie;

@@ -480,9 +477,6 @@ void monitor_disas(Monitor *mon, CPUState *cpu,
 #elif defined(TARGET_SH4)
     s.info.mach = bfd_mach_sh4;
     s.info.print_insn = print_insn_sh;
-#elif defined(TARGET_S390X)
-    s.info.mach = bfd_mach_s390_64;
-    s.info.print_insn = print_insn_s390;
 #elif defined(TARGET_MOXIE)
     s.info.mach = bfd_arch_moxie;
     s.info.print_insn = print_insn_moxie;
target-s390x/cpu.c +8 -0
index c3e21b4..471c6a7 100644
@@ -184,6 +184,12 @@ static void s390_cpu_machine_reset_cb(void *opaque)
 }
 #endif
 
+static void s390_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+    info->mach = bfd_mach_s390_64;
+    info->print_insn = print_insn_s390;
+}
+
 static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
 {
     CPUState *cs = CPU(dev);

@@ -353,6 +359,8 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
 #endif
     cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
     cc->gdb_core_xml_file = "s390x-core64.xml";
+
+    cc->disas_set_info = s390_cpu_disas_set_info;
 }
 
 static const TypeInfo s390_cpu_type_info = {
Signature · 1 line
1.9.1
author
#2 lore raw

Re: [Qemu-devel] [PATCH 1/8] disas: s390x: QOMify target specific disas setup

Ping!

Quoted 89 lines · Peter Crosthwaite

From: Peter Crosthwaite <[email protected]>

Move the target_disas() s390 specifics to the QOM disas_set_info hook and delete the #ifdef specific code in disas.c.

Cc Richard Henderson <[email protected]>
Cc Alexander Graf <[email protected]>
Signed-off-by Peter Crosthwaite <[email protected]>

---
Testing:

$ ./s390x-softmmu/qemu-system-s390x -nographic -d in_asm -S 2> err
QEMU 2.3.90 monitor - type 'help' for more information
(qemu) info register
unknown command: 'register'
(qemu) info registers
PSW=mask 0000000180000000 addr 0000000007e00468 cc 00
...
(qemu) x/i 0x7e00468
0x0000000007e00468:  larl   %r15,0x7e0d000
(qemu) x/i 0x7e0046e
0x0000000007e0046e:  larl   %r6,0x7e15000
(qemu) c
(qemu) No virtio-blk device found!
$ more err
IN:
0x0000000007e00468:  larl   %r15,0x7e0d000
0x0000000007e0046e:  larl   %r6,0x7e15000
0x0000000007e00474:  stg    %r7,0(%r6)
0x0000000007e0047a:  j  0x7e0052c
...
---
 disas.c            | 6 ------
 target-s390x/cpu.c | 8 ++++++++
 2 files changed, 8 insertions(+), 6 deletions(-)
disas.c +0 -6
index 69a6066..e62c934 100644
@@ -257,9 +257,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
 #elif defined(TARGET_ALPHA)
     s.info.mach = bfd_mach_alpha_ev6;
     s.info.print_insn = print_insn_alpha;
-#elif defined(TARGET_S390X)
-    s.info.mach = bfd_mach_s390_64;
-    s.info.print_insn = print_insn_s390;
 #elif defined(TARGET_MOXIE)
     s.info.mach = bfd_arch_moxie;
     s.info.print_insn = print_insn_moxie;

@@ -480,9 +477,6 @@ void monitor_disas(Monitor *mon, CPUState *cpu,
 #elif defined(TARGET_SH4)
     s.info.mach = bfd_mach_sh4;
     s.info.print_insn = print_insn_sh;
-#elif defined(TARGET_S390X)
-    s.info.mach = bfd_mach_s390_64;
-    s.info.print_insn = print_insn_s390;
 #elif defined(TARGET_MOXIE)
     s.info.mach = bfd_arch_moxie;
     s.info.print_insn = print_insn_moxie;
target-s390x/cpu.c +8 -1
index c3e21b4..471c6a7 100644
@@ -184,6 +184,12 @@ static void s390_cpu_machine_reset_cb(void *opaque)
 }
 #endif
 
+static void s390_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+    info->mach = bfd_mach_s390_64;
+    info->print_insn = print_insn_s390;
+}
+
 static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
 {
     CPUState *cs = CPU(dev);

@@ -353,6 +359,8 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
 #endif
     cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
     cc->gdb_core_xml_file = "s390x-core64.xml";
+
+    cc->disas_set_info = s390_cpu_disas_set_info;
 }
 
 static const TypeInfo s390_cpu_type_info = {
--

1.9.1

author
#3 lore raw

PATCH 2/8 disas: moxie: QOMify target specific disas setup

In reply to Peter Crosthwaite

From: Peter Crosthwaite <[email protected]>

Move the target_disas() moxie specifics to the QOM disas_set_info hook and delete the #ifdef specific code in disas.c.

Cc Anthony Green <[email protected]>
Signed-off-by Peter Crosthwaite <[email protected]>

---
I don't have any easy way to test this. Is there a simple binary image somewhere I can pass in to see disas of handful of instructions?

---
 disas.c            | 6 ------
 target-moxie/cpu.c | 7 +++++++
 2 files changed, 7 insertions(+), 6 deletions(-)
disas.c +0 -6
index e62c934..6c86129 100644
@@ -257,9 +257,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
 #elif defined(TARGET_ALPHA)
     s.info.mach = bfd_mach_alpha_ev6;
     s.info.print_insn = print_insn_alpha;
-#elif defined(TARGET_MOXIE)
-    s.info.mach = bfd_arch_moxie;
-    s.info.print_insn = print_insn_moxie;
 #elif defined(TARGET_LM32)
     s.info.mach = bfd_mach_lm32;
     s.info.print_insn = print_insn_lm32;

@@ -477,9 +474,6 @@ void monitor_disas(Monitor *mon, CPUState *cpu,
 #elif defined(TARGET_SH4)
     s.info.mach = bfd_mach_sh4;
     s.info.print_insn = print_insn_sh;
-#elif defined(TARGET_MOXIE)
-    s.info.mach = bfd_arch_moxie;
-    s.info.print_insn = print_insn_moxie;
 #elif defined(TARGET_LM32)
     s.info.mach = bfd_mach_lm32;
     s.info.print_insn = print_insn_lm32;
target-moxie/cpu.c +7 -0
index 6b035aa..4044cca 100644
@@ -48,6 +48,12 @@ static void moxie_cpu_reset(CPUState *s)
     tlb_flush(s, 1);
 }
 
+static void moxie_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+    info->mach = bfd_arch_moxie;
+    info->print_insn = print_insn_moxie;
+}
+
 static void moxie_cpu_realizefn(DeviceState *dev, Error **errp)
 {
     CPUState *cs = CPU(dev);

@@ -114,6 +120,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
     cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
     cc->vmsd = &vmstate_moxie_cpu;
 #endif
+    cc->disas_set_info = moxie_cpu_disas_set_info;
 }
 
 static void moxielite_initfn(Object *obj)
Signature · 1 line
1.9.1
author
#4 lore raw

PATCH 3/8 disas: m68k: QOMify target specific disas setup

In reply to Peter Crosthwaite

From: Peter Crosthwaite <[email protected]>

Move the target_disas() m68k specifics to the QOM disas_set_info hook and delete the #ifdef specific code in disas.c.

Cc Greg Ungerer <[email protected]>
Cc Laurent Vivier <[email protected]>
Signed-off-by Peter Crosthwaite <[email protected]>

---
Testing:
I cant find binaries for this arch easily, but I got this from executing random code:

$ ./m68k-softmmu/qemu-system-m68k -kernel ./random_code -S -nographic -d in_asm 2> err
QEMU 2.3.90 monitor - type 'help' for more information
(qemu) xp 0x40000000
0000000040000000: 0x7d413a22
(qemu) xp/i 0x40000000
0x40000000:  mvsw %d1,%d6
(qemu) xp/i 0x40000004
0x40000004:  addqb #2,%a0@(27614)
(qemu) c
(qemu) Aborted (core dumped)
$ more err
qemu: fatal: Illegal instruction: 7d41 @ 40000000
---
 disas.c           | 4 ----
 target-m68k/cpu.c | 7 +++++++
 2 files changed, 7 insertions(+), 4 deletions(-)
disas.c +0 -4
index 6c86129..91cbb1a 100644
@@ -243,8 +243,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
     }
     s.info.disassembler_options = (char *)"any";
     s.info.print_insn = print_insn_ppc;
-#elif defined(TARGET_M68K)
-    s.info.print_insn = print_insn_m68k;
 #elif defined(TARGET_MIPS)
 #ifdef TARGET_WORDS_BIGENDIAN
     s.info.print_insn = print_insn_big_mips;

@@ -463,8 +461,6 @@ void monitor_disas(Monitor *mon, CPUState *cpu,
         s.info.endian = BFD_ENDIAN_LITTLE;
     }
     s.info.print_insn = print_insn_ppc;
-#elif defined(TARGET_M68K)
-    s.info.print_insn = print_insn_m68k;
 #elif defined(TARGET_MIPS)
 #ifdef TARGET_WORDS_BIGENDIAN
     s.info.print_insn = print_insn_big_mips;
target-m68k/cpu.c +7 -0
index 4f246da..2555755 100644
@@ -61,6 +61,11 @@ static void m68k_cpu_reset(CPUState *s)
     tlb_flush(s, 1);
 }
 
+static void m68k_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+    info->print_insn = print_insn_m68k;
+}
+
 /* CPU models */
 
 static ObjectClass *m68k_cpu_class_by_name(const char *cpu_model)

@@ -212,6 +217,8 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
     dc->vmsd = &vmstate_m68k_cpu;
     cc->gdb_num_core_regs = 18;
     cc->gdb_core_xml_file = "cf-core.xml";
+
+    cc->disas_set_info = m68k_cpu_disas_set_info;
 }
 
 static void register_cpu_type(const M68kCPUInfo *info)
Signature · 1 line
1.9.1
Reviewed-by on v1 3/8
#5 lore raw

Re: [Qemu-devel] [PATCH 3/8] disas: m68k: QOMify target specific disas setup

Quoted 24 lines · Peter Crosthwaite

From: Peter Crosthwaite <[email protected]>

Move the target_disas() m68k specifics to the QOM disas_set_info hook and delete the #ifdef specific code in disas.c.

Cc Greg Ungerer <[email protected]>
Cc Laurent Vivier <[email protected]>
Signed-off-by Peter Crosthwaite <[email protected]>

---
Testing:
I cant find binaries for this arch easily, but I got this from executing random code:

$ ./m68k-softmmu/qemu-system-m68k -kernel ./random_code -S -nographic -d in_asm 2> err
QEMU 2.3.90 monitor - type 'help' for more information
(qemu) xp 0x40000000
0000000040000000: 0x7d413a22
(qemu) xp/i 0x40000000
0x40000000:  mvsw %d1,%d6
(qemu) xp/i 0x40000004
0x40000004:  addqb #2,%a0@(27614)
(qemu) c
(qemu) Aborted (core dumped)
Quoted 6 lines
$ more err
qemu: fatal: Illegal instruction: 7d41 @ 40000000
---
 disas.c           | 4 ----
 target-m68k/cpu.c | 7 +++++++
 2 files changed, 7 insertions(+), 4 deletions(-)
Reviewed-by Laurent Vivier <[email protected]>
Reviewed-by on v1 3/8
#6 lore raw

Re: [Qemu-devel] [PATCH 3/8] disas: m68k: QOMify target specific disas setup

In reply to Peter Crosthwaite
Quoted 6 lines · Peter Crosthwaite

From: Peter Crosthwaite <[email protected]>

Move the target_disas() m68k specifics to the QOM disas_set_info hook and delete the #ifdef specific code in disas.c.

Cc Greg Ungerer <[email protected]>

I see no problems.

Reviewed-by Greg Ungerer <[email protected]>
Quoted 73 lines
Cc Laurent Vivier <[email protected]>
Signed-off-by Peter Crosthwaite <[email protected]>

---
Testing:
I cant find binaries for this arch easily, but I got this from executing random code:

$ ./m68k-softmmu/qemu-system-m68k -kernel ./random_code -S -nographic -d in_asm 2> err
QEMU 2.3.90 monitor - type 'help' for more information
(qemu) xp 0x40000000
0000000040000000: 0x7d413a22
(qemu) xp/i 0x40000000
0x40000000:  mvsw %d1,%d6
(qemu) xp/i 0x40000004
0x40000004:  addqb #2,%a0@(27614)
(qemu) c
(qemu) Aborted (core dumped)
$ more err
qemu: fatal: Illegal instruction: 7d41 @ 40000000
---
 disas.c           | 4 ----
 target-m68k/cpu.c | 7 +++++++
 2 files changed, 7 insertions(+), 4 deletions(-)
disas.c +0 -4
index 6c86129..91cbb1a 100644
@@ -243,8 +243,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
     }
     s.info.disassembler_options = (char *)"any";
     s.info.print_insn = print_insn_ppc;
-#elif defined(TARGET_M68K)
-    s.info.print_insn = print_insn_m68k;
 #elif defined(TARGET_MIPS)
 #ifdef TARGET_WORDS_BIGENDIAN
     s.info.print_insn = print_insn_big_mips;

@@ -463,8 +461,6 @@ void monitor_disas(Monitor *mon, CPUState *cpu,
         s.info.endian = BFD_ENDIAN_LITTLE;
     }
     s.info.print_insn = print_insn_ppc;
-#elif defined(TARGET_M68K)
-    s.info.print_insn = print_insn_m68k;
 #elif defined(TARGET_MIPS)
 #ifdef TARGET_WORDS_BIGENDIAN
     s.info.print_insn = print_insn_big_mips;
target-m68k/cpu.c +7 -0
index 4f246da..2555755 100644
@@ -61,6 +61,11 @@ static void m68k_cpu_reset(CPUState *s)
     tlb_flush(s, 1);
 }
 
+static void m68k_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+    info->print_insn = print_insn_m68k;
+}
+
 /* CPU models */
 
 static ObjectClass *m68k_cpu_class_by_name(const char *cpu_model)

@@ -212,6 +217,8 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
     dc->vmsd = &vmstate_m68k_cpu;
     cc->gdb_num_core_regs = 18;
     cc->gdb_core_xml_file = "cf-core.xml";
+
+    cc->disas_set_info = m68k_cpu_disas_set_info;
 }
 
 static void register_cpu_type(const M68kCPUInfo *info)
author
#7 lore raw

PATCH 4/8 disas: sparc: QOMify target specific disas setup

In reply to Peter Crosthwaite

From: Peter Crosthwaite <[email protected]>

Move the target_disas() sparc specifics to the QOM disas_set_info hook and delete the #ifdef specific code in disas.c.

Cc Mark Cave-Ayland <[email protected]>
Signed-off-by Peter Crosthwaite <[email protected]>

---
Testing:

$ ./sparc64-softmmu/qemu-system-sparc64 -nographic 2> er -d in_asm -S
QEMU 2.3.90 monitor - type 'help' for more information
(qemu) info registers
pc: 000001fff0000020  npc: 000001fff0000024
...
(qemu) x/i 0x1fff0000020
0x000001fff0000020:  b  0x1fff000c020
(qemu) x/i 0x1fff0000024
0x000001fff0000024:  nop
(qemu) c
(qemu) OpenBIOS for Sparc64
QEMU: Terminated
$ more err
--------------
IN:
0x000001fff0000020:  b  0x1fff000c020
0x000001fff0000024:  nop
$ ./sparc-softmmu/qemu-system-sparc -nographic 2> err -d in_asm -S
QEMU 2.3.90 monitor - type 'help' for more information
(qemu) info registers
pc: 00000000  npc: 00000004
...
(qemu) x/i 0
0x00000000:  b  0x5d48
(qemu) x/i 4
0x00000004:  nop
(qemu) c
(qemu) q
$ more err
--------------
IN:
0x00000000:  b  0x5d48
0x00000004:  nop
---
 disas.c            | 10 ----------
 target-sparc/cpu.c |  9 +++++++++
 2 files changed, 9 insertions(+), 10 deletions(-)
disas.c +0 -10
index 91cbb1a..9459505 100644
@@ -222,11 +222,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
         s.info.mach = bfd_mach_i386_i386;
     }
     s.info.print_insn = print_insn_i386;
-#elif defined(TARGET_SPARC)
-    s.info.print_insn = print_insn_sparc;
-#ifdef TARGET_SPARC64
-    s.info.mach = bfd_mach_sparc_v9b;
-#endif
 #elif defined(TARGET_PPC)
     if ((flags >> 16) & 1) {
         s.info.endian = BFD_ENDIAN_LITTLE;

@@ -441,11 +436,6 @@ void monitor_disas(Monitor *mon, CPUState *cpu,
     s.info.print_insn = print_insn_i386;
 #elif defined(TARGET_ALPHA)
     s.info.print_insn = print_insn_alpha;
-#elif defined(TARGET_SPARC)
-    s.info.print_insn = print_insn_sparc;
-#ifdef TARGET_SPARC64
-    s.info.mach = bfd_mach_sparc_v9b;
-#endif
 #elif defined(TARGET_PPC)
     if (flags & 0xFFFF) {
         /* If we have a precise definition of the instruction set, use it. */
target-sparc/cpu.c +9 -0
index 9528e3a..06c59a4 100644
@@ -90,6 +90,14 @@ static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
     return false;
 }
 
+static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+    info->print_insn = print_insn_sparc;
+#ifdef TARGET_SPARC64
+    info->mach = bfd_mach_sparc_v9b;
+#endif
+}
+
 static int cpu_sparc_register(SPARCCPU *cpu, const char *cpu_model)
 {
     CPUClass *cc = CPU_GET_CLASS(cpu);

@@ -854,6 +862,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
 #else
     cc->gdb_num_core_regs = 72;
 #endif
+    cc->disas_set_info = cpu_sparc_disas_set_info;
 }
 
 static const TypeInfo sparc_cpu_type_info = {
Signature · 1 line
1.9.1
author
#8 lore raw

PATCH 5/8 disas: lm32: QOMify target specific disas setup

In reply to Peter Crosthwaite

From: Peter Crosthwaite <[email protected]>

Move the target_disas() lm32 specifics to the QOM disas_set_info hook and delete the #ifdef specific code in disas.c.

Cc Michael Walle <[email protected]>
Signed-off-by Peter Crosthwaite <[email protected]>

---
Testing:

$ ./lm32-softmmu/qemu-system-lm32 -kernel ./random_code -S -d in_asm -nographic
QEMU 2.3.90 monitor - type 'help' for more information
(qemu) info cpus
* CPU #0: thread_id=1113
(qemu) info registers
IN: PC=8000000
...
(qemu) x/i 0x8000000
0x08000000:  7d 41 3a 22    cmpnei   r1, r10, 14882
(qemu) x/i 0x8000004
0x08000004:  54 28 6b de    bgu      r8, r1, 801af7c
(qemu) c
$ more err
08000000:   7d413a22    cmpnei r10, r1, 14882
08000004:   54286bde    bgu r1, r8, 110456
0x08000000:  7d 41 3a 22    cmpnei   r1, r10, 14882
0x08000004:  54 28 6b de    bgu      r8, r1, 801af7c
---
 disas.c           | 6 ------
 target-lm32/cpu.c | 8 ++++++++
 2 files changed, 8 insertions(+), 6 deletions(-)
disas.c +0 -6
index 9459505..f269cc9 100644
@@ -250,9 +250,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
 #elif defined(TARGET_ALPHA)
     s.info.mach = bfd_mach_alpha_ev6;
     s.info.print_insn = print_insn_alpha;
-#elif defined(TARGET_LM32)
-    s.info.mach = bfd_mach_lm32;
-    s.info.print_insn = print_insn_lm32;
 #endif
     if (s.info.print_insn == NULL) {
         s.info.print_insn = print_insn_od_target;

@@ -460,9 +457,6 @@ void monitor_disas(Monitor *mon, CPUState *cpu,
 #elif defined(TARGET_SH4)
     s.info.mach = bfd_mach_sh4;
     s.info.print_insn = print_insn_sh;
-#elif defined(TARGET_LM32)
-    s.info.mach = bfd_mach_lm32;
-    s.info.print_insn = print_insn_lm32;
 #endif
     if (!s.info.print_insn) {
         monitor_printf(mon, "0x" TARGET_FMT_lx
target-lm32/cpu.c +8 -0
index c2b77c6..f9080ef 100644
@@ -131,6 +131,12 @@ static void lm32_cpu_reset(CPUState *s)
     tlb_flush(s, 1);
 }
 
+static void lm32_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+    info->mach = bfd_mach_lm32;
+    info->print_insn = print_insn_lm32;
+}
+
 static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
 {
     CPUState *cs = CPU(dev);

@@ -275,6 +281,8 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
     cc->gdb_num_core_regs = 32 + 7;
     cc->gdb_stop_before_watchpoint = true;
     cc->debug_excp_handler = lm32_debug_excp_handler;
+
+    cc->disas_set_info = lm32_cpu_disas_set_info;
 }
 
 static void lm32_register_cpu_type(const LM32CPUInfo *info)
Signature · 1 line
1.9.1
Acked-by on v1 5/8
#9 lore raw

Re: [Qemu-devel] [PATCH 5/8] disas: lm32: QOMify target specific disas setup

Am 12. Juli 2015 04:00:02 MESZ, schrieb Peter Crosthwaite <[email protected]>:

Quoted 7 lines

From: Peter Crosthwaite <[email protected]>

Move the target_disas() lm32 specifics to the QOM disas_set_info hook and delete the #ifdef specific code in disas.c.

Cc Michael Walle <[email protected]>
Signed-off-by Peter Crosthwaite <[email protected]>
Acked-by Michael Walle <[email protected]>
author
#10 lore raw

PATCH 6/8 disas: sh4: QOMify target specific disas setup

In reply to Peter Crosthwaite

From: Peter Crosthwaite <[email protected]>

Move the target_disas() sh4 specifics to the QOM disas_set_info hook and delete the #ifdef specific code in disas.c.

Cc Aurelien Jarno <[email protected]>
Signed-off-by Peter Crosthwaite <[email protected]>

---
Testing:

$ ../../qemu/sh4-softmmu/qemu-system-sh4 -M r2d -kernel zImage \
    -hda sh-linux-mini.img -nographic -d in_asm -S 2> err
QEMU 2.3.90 monitor - type 'help' for more information
(qemu) info registers
pc=0xac800000 sr=0x700000f0 pr=0x00000000 fpscr=0x00040001
...
(qemu) x/i 0xac800000
0xac800000:  mov.l  0xac80007c,r1   ! 0x400000f0
(qemu) x/i 0xac800004
0xac800004:  mova   0xac80004c,r0
(qemu) c
(qemu) q
$ more err
IN:
0xac800000:  mov.l  0xac80007c,r1   ! 0x400000f0
0xac800002:  ldc    r1,sr

IN:
0xac800004: mova 0xac80004c,r0

---
 disas.c          | 6 ------
 target-sh4/cpu.c | 8 ++++++++
 2 files changed, 8 insertions(+), 6 deletions(-)
disas.c +0 -6
index f269cc9..eee369e 100644
@@ -244,9 +244,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
 #else
     s.info.print_insn = print_insn_little_mips;
 #endif
-#elif defined(TARGET_SH4)
-    s.info.mach = bfd_mach_sh4;
-    s.info.print_insn = print_insn_sh;
 #elif defined(TARGET_ALPHA)
     s.info.mach = bfd_mach_alpha_ev6;
     s.info.print_insn = print_insn_alpha;

@@ -454,9 +451,6 @@ void monitor_disas(Monitor *mon, CPUState *cpu,
 #else
     s.info.print_insn = print_insn_little_mips;
 #endif
-#elif defined(TARGET_SH4)
-    s.info.mach = bfd_mach_sh4;
-    s.info.print_insn = print_insn_sh;
 #endif
     if (!s.info.print_insn) {
         monitor_printf(mon, "0x" TARGET_FMT_lx
target-sh4/cpu.c +8 -0
index 5c65ab4..1b4289d 100644
@@ -70,6 +70,12 @@ static void superh_cpu_reset(CPUState *s)
     set_default_nan_mode(1, &env->fp_status);
 }
 
+static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+    info->mach = bfd_mach_sh4;
+    info->print_insn = print_insn_sh;
+}
+
 typedef struct SuperHCPUListState {
     fprintf_function cpu_fprintf;
     FILE *file;

@@ -290,6 +296,8 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
 #endif
     dc->vmsd = &vmstate_sh_cpu;
     cc->gdb_num_core_regs = 59;
+
+    cc->disas_set_info = superh_cpu_disas_set_info;
 }
 
 static const TypeInfo superh_cpu_type_info = {
Signature · 1 line
1.9.1
Acked-by on v1 6/8
#11 lore raw

Re: [Qemu-devel] [PATCH 6/8] disas: sh4: QOMify target specific disas setup

Quoted 76 lines · Peter Crosthwaite

From: Peter Crosthwaite <[email protected]>

Move the target_disas() sh4 specifics to the QOM disas_set_info hook and delete the #ifdef specific code in disas.c.

Cc Aurelien Jarno <[email protected]>
Signed-off-by Peter Crosthwaite <[email protected]>

---
Testing:

$ ../../qemu/sh4-softmmu/qemu-system-sh4 -M r2d -kernel zImage \
    -hda sh-linux-mini.img -nographic -d in_asm -S 2> err
QEMU 2.3.90 monitor - type 'help' for more information
(qemu) info registers
pc=0xac800000 sr=0x700000f0 pr=0x00000000 fpscr=0x00040001
...
(qemu) x/i 0xac800000
0xac800000:  mov.l  0xac80007c,r1   ! 0x400000f0
(qemu) x/i 0xac800004
0xac800004:  mova   0xac80004c,r0
(qemu) c
(qemu) q
$ more err
IN:
0xac800000:  mov.l  0xac80007c,r1   ! 0x400000f0
0xac800002:  ldc    r1,sr

IN:
0xac800004: mova 0xac80004c,r0

---
 disas.c          | 6 ------
 target-sh4/cpu.c | 8 ++++++++
 2 files changed, 8 insertions(+), 6 deletions(-)
disas.c +0 -6
index f269cc9..eee369e 100644
@@ -244,9 +244,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
 #else
     s.info.print_insn = print_insn_little_mips;
 #endif
-#elif defined(TARGET_SH4)
-    s.info.mach = bfd_mach_sh4;
-    s.info.print_insn = print_insn_sh;
 #elif defined(TARGET_ALPHA)
     s.info.mach = bfd_mach_alpha_ev6;
     s.info.print_insn = print_insn_alpha;

@@ -454,9 +451,6 @@ void monitor_disas(Monitor *mon, CPUState *cpu,
 #else
     s.info.print_insn = print_insn_little_mips;
 #endif
-#elif defined(TARGET_SH4)
-    s.info.mach = bfd_mach_sh4;
-    s.info.print_insn = print_insn_sh;
 #endif
     if (!s.info.print_insn) {
         monitor_printf(mon, "0x" TARGET_FMT_lx
target-sh4/cpu.c +6 -0
index 5c65ab4..1b4289d 100644
@@ -70,6 +70,12 @@ static void superh_cpu_reset(CPUState *s)
     set_default_nan_mode(1, &env->fp_status);
 }
 
+static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+    info->mach = bfd_mach_sh4;
+    info->print_insn = print_insn_sh;
+}
+
 typedef struct SuperHCPUListState {
     fprintf_function cpu_fprintf;
     FILE *file;

target-sh4/cpu.c static void superh_cpu_class_init(ObjectClass *oc, void *data) · line 303

Quoted 8 lines
target-sh4/cpu.c +2 -0
@@ -290,6 +296,8 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
 #endif
     dc->vmsd = &vmstate_sh_cpu;
     cc->gdb_num_core_regs = 59;
+
+    cc->disas_set_info = superh_cpu_disas_set_info;
 }
 
 static const TypeInfo superh_cpu_type_info = {
Acked-by Aurelien Jarno <[email protected]>
Signature · 2 lines
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
[email protected]                 http://www.aurel32.net
author
#12 lore raw

PATCH 7/8 disas: mips: QOMify target specific disas setup

In reply to Peter Crosthwaite

From: Peter Crosthwaite <[email protected]>

Move the target_disas() mips specifics to the QOM disas_set_info hook and delete the #ifdef specific code in disas.c.

Cc Aurelien Jarno <[email protected]>
Cc Leon Alrae <[email protected]>
Signed-off-by Peter Crosthwaite <[email protected]>

---
Testing:
mips-test$ ./run-qemu -d in_asm -S 2> err QEMU 2.3.90 monitor - type 'help' for more information (qemu) x/i 0xbfc00000
0xbfc00000: j 0xbfc00580
(qemu) c
(qemu) q

mips-test$ more err
IN:
0xbfc00000: j 0xbfc00580
0xbfc00004: nop

IN:
0xbfc00580: li a0,2
0xbfc00584: lui sp,0x8000
...

---
 disas.c           | 12 ------------
 target-mips/cpu.c | 10 ++++++++++
 2 files changed, 10 insertions(+), 12 deletions(-)
disas.c +0 -12
index eee369e..28decc9 100644
@@ -238,12 +238,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
     }
     s.info.disassembler_options = (char *)"any";
     s.info.print_insn = print_insn_ppc;
-#elif defined(TARGET_MIPS)
-#ifdef TARGET_WORDS_BIGENDIAN
-    s.info.print_insn = print_insn_big_mips;
-#else
-    s.info.print_insn = print_insn_little_mips;
-#endif
 #elif defined(TARGET_ALPHA)
     s.info.mach = bfd_mach_alpha_ev6;
     s.info.print_insn = print_insn_alpha;

@@ -445,12 +439,6 @@ void monitor_disas(Monitor *mon, CPUState *cpu,
         s.info.endian = BFD_ENDIAN_LITTLE;
     }
     s.info.print_insn = print_insn_ppc;
-#elif defined(TARGET_MIPS)
-#ifdef TARGET_WORDS_BIGENDIAN
-    s.info.print_insn = print_insn_big_mips;
-#else
-    s.info.print_insn = print_insn_little_mips;
-#endif
 #endif
     if (!s.info.print_insn) {
         monitor_printf(mon, "0x" TARGET_FMT_lx
target-mips/cpu.c +10 -0
index 4027d0f..83ab2b0 100644
@@ -97,6 +97,14 @@ static void mips_cpu_reset(CPUState *s)
 #endif
 }
 
+static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) {
+#ifdef TARGET_WORDS_BIGENDIAN
+    info->print_insn = print_insn_big_mips;
+#else
+    info->print_insn = print_insn_little_mips;
+#endif
+}
+
 static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
 {
     CPUState *cs = CPU(dev);

@@ -153,6 +161,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
 
     cc->gdb_num_core_regs = 73;
     cc->gdb_stop_before_watchpoint = true;
+
+    cc->disas_set_info = mips_cpu_disas_set_info;
 }
 
 static const TypeInfo mips_cpu_type_info = {
Signature · 1 line
1.9.1
Acked-by on v1 7/8
#13 lore raw

Re: [Qemu-devel] [PATCH 7/8] disas: mips: QOMify target specific disas setup

Quoted 22 lines · Peter Crosthwaite

From: Peter Crosthwaite <[email protected]>

Move the target_disas() mips specifics to the QOM disas_set_info hook and delete the #ifdef specific code in disas.c.

Cc Aurelien Jarno <[email protected]>
Cc Leon Alrae <[email protected]>
Signed-off-by Peter Crosthwaite <[email protected]>

---
Testing:
mips-test$ ./run-qemu -d in_asm -S 2> err QEMU 2.3.90 monitor - type 'help' for more information (qemu) x/i 0xbfc00000
0xbfc00000: j 0xbfc00580
(qemu) c
(qemu) q

mips-test$ more err
IN:
0xbfc00000: j 0xbfc00580
0xbfc00004: nop

Quoted 8 lines

IN:
0xbfc00580: li a0,2
0xbfc00584: lui sp,0x8000
...

---
 disas.c           | 12 ------------
 target-mips/cpu.c | 10 ++++++++++
 2 files changed, 10 insertions(+), 12 deletions(-)
Acked-by Leon Alrae <[email protected]>
author
#14 lore raw

PATCH 8/8 disas: alpha: QOMify target specific disas setup

In reply to Peter Crosthwaite

From: Peter Crosthwaite <[email protected]>

Move the target_disas() alpha specifics to the QOM disas_set_info hook and delete the #ifdef specific code in disas.c.

This also makes monitor_disas() consistent with target_disas(), as monitor_disas() was missing a set of the BFD (This was an omission from commit b9bec751c8c8b08d8055da32306eb105db03031b).

Cc Richard Henderson <[email protected]>
Signed-off-by Peter Crosthwaite <[email protected]>

---
Testing:

$ ./alpha-softmmu/qemu-system-alpha -nographic -d in_asm -S 2> err
QEMU 2.3.90 monitor - type 'help' for more information
(qemu) info registers
     PC  fffffc0000000000
...
(qemu) x/i 0xfffffc0000000000
0xfffffc0000000000:  br gp,0xfffffc0000000004
(qemu) x/i 0xfffffc0000000004
0xfffffc0000000004:  ldah   gp,1(gp)
(qemu) c
(qemu) PCI: 00:00:0 class 0300 id 1013:00b8
PCI:   region 0: 10000000
PCI:   region 1: 12000000
PCI: 00:01:0 class 0200 id 8086:100e
PCI:   region 0: 12020000
PCI:   region 1: 0000c000
PCI: 00:02:0 class 0101 id 1095:0646
PCI:   region 0: 0000c040
PCI:   region 1: 0000c048
PCI:   region 3: 0000c04c
Quoted 1 line
Quoted 1 line
Quoted 1 line

QEMU: Terminated

$ more err
IN: __start
0xfffffc0000000000:  br gp,0xfffffc0000000004
0xfffffc0000000004:  ldah   gp,1(gp)
0xfffffc0000000008:  lda    gp,12108(gp)
0xfffffc000000000c:  hw_mtpr    gp,0x32
0xfffffc0000000010:  lda    t0,7
---
 disas.c            | 5 -----
 target-alpha/cpu.c | 8 ++++++++
 2 files changed, 8 insertions(+), 5 deletions(-)
disas.c +0 -5
index 28decc9..4c1a129 100644
@@ -238,9 +238,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
     }
     s.info.disassembler_options = (char *)"any";
     s.info.print_insn = print_insn_ppc;
-#elif defined(TARGET_ALPHA)
-    s.info.mach = bfd_mach_alpha_ev6;
-    s.info.print_insn = print_insn_alpha;
 #endif
     if (s.info.print_insn == NULL) {
         s.info.print_insn = print_insn_od_target;

@@ -422,8 +419,6 @@ void monitor_disas(Monitor *mon, CPUState *cpu,
         s.info.mach = bfd_mach_i386_i386;
     }
     s.info.print_insn = print_insn_i386;
-#elif defined(TARGET_ALPHA)
-    s.info.print_insn = print_insn_alpha;
 #elif defined(TARGET_PPC)
     if (flags & 0xFFFF) {
         /* If we have a precise definition of the instruction set, use it. */
target-alpha/cpu.c +8 -0
index 421d7e5..49625cf 100644
@@ -46,6 +46,12 @@ static bool alpha_cpu_has_work(CPUState *cs)
                                     | CPU_INTERRUPT_MCHK);
 }
 
+static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+    info->mach = bfd_mach_alpha_ev6;
+    info->print_insn = print_insn_alpha;
+}
+
 static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
 {
     CPUState *cs = CPU(dev);

@@ -298,6 +304,8 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
     dc->vmsd = &vmstate_alpha_cpu;
 #endif
     cc->gdb_num_core_regs = 67;
+
+    cc->disas_set_info = alpha_cpu_disas_set_info;
 }
 
 static const TypeInfo alpha_cpu_type_info = {
Signature · 1 line
1.9.1
author
#15 lore raw

Re: [Qemu-devel] [PATCH 8/8] disas: alpha: QOMify target specific disas setup

Ping!

Quoted 99 lines · Peter Crosthwaite

From: Peter Crosthwaite <[email protected]>

Move the target_disas() alpha specifics to the QOM disas_set_info hook and delete the #ifdef specific code in disas.c.

This also makes monitor_disas() consistent with target_disas(), as monitor_disas() was missing a set of the BFD (This was an omission from commit b9bec751c8c8b08d8055da32306eb105db03031b).

Cc Richard Henderson <[email protected]>
Signed-off-by Peter Crosthwaite <[email protected]>

---
Testing:

$ ./alpha-softmmu/qemu-system-alpha -nographic -d in_asm -S 2> err
QEMU 2.3.90 monitor - type 'help' for more information
(qemu) info registers
     PC  fffffc0000000000
...
(qemu) x/i 0xfffffc0000000000
0xfffffc0000000000:  br gp,0xfffffc0000000004
(qemu) x/i 0xfffffc0000000004
0xfffffc0000000004:  ldah   gp,1(gp)
(qemu) c
(qemu) PCI: 00:00:0 class 0300 id 1013:00b8
PCI:   region 0: 10000000
PCI:   region 1: 12000000
PCI: 00:01:0 class 0200 id 8086:100e
PCI:   region 0: 12020000
PCI:   region 1: 0000c000
PCI: 00:02:0 class 0101 id 1095:0646
PCI:   region 0: 0000c040
PCI:   region 1: 0000c048
PCI:   region 3: 0000c04c
Quoted 1 line
Quoted 1 line
Quoted 1 line

QEMU: Terminated

$ more err
IN: __start
0xfffffc0000000000:  br gp,0xfffffc0000000004
0xfffffc0000000004:  ldah   gp,1(gp)
0xfffffc0000000008:  lda    gp,12108(gp)
0xfffffc000000000c:  hw_mtpr    gp,0x32
0xfffffc0000000010:  lda    t0,7
---
 disas.c            | 5 -----
 target-alpha/cpu.c | 8 ++++++++
 2 files changed, 8 insertions(+), 5 deletions(-)
disas.c +0 -5
index 28decc9..4c1a129 100644
@@ -238,9 +238,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
     }
     s.info.disassembler_options = (char *)"any";
     s.info.print_insn = print_insn_ppc;
-#elif defined(TARGET_ALPHA)
-    s.info.mach = bfd_mach_alpha_ev6;
-    s.info.print_insn = print_insn_alpha;
 #endif
     if (s.info.print_insn == NULL) {
         s.info.print_insn = print_insn_od_target;

@@ -422,8 +419,6 @@ void monitor_disas(Monitor *mon, CPUState *cpu,
         s.info.mach = bfd_mach_i386_i386;
     }
     s.info.print_insn = print_insn_i386;
-#elif defined(TARGET_ALPHA)
-    s.info.print_insn = print_insn_alpha;
 #elif defined(TARGET_PPC)
     if (flags & 0xFFFF) {
         /* If we have a precise definition of the instruction set, use it. */
target-alpha/cpu.c +8 -1
index 421d7e5..49625cf 100644
@@ -46,6 +46,12 @@ static bool alpha_cpu_has_work(CPUState *cs)
                                     | CPU_INTERRUPT_MCHK);
 }
 
+static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+    info->mach = bfd_mach_alpha_ev6;
+    info->print_insn = print_insn_alpha;
+}
+
 static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
 {
     CPUState *cs = CPU(dev);

@@ -298,6 +304,8 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
     dc->vmsd = &vmstate_alpha_cpu;
 #endif
     cc->gdb_num_core_regs = 67;
+
+    cc->disas_set_info = alpha_cpu_disas_set_info;
 }
 
 static const TypeInfo alpha_cpu_type_info = {
--

1.9.1

#16 lore raw
In reply to Peter Crosthwaite

Am 12.07.2015 um 03:59 schrieb Peter Crosthwaite:

Quoted 5 lines

Continue QOMifying target-specific disassembly. Convert all arches except for X86 and PPC. They will be round 3 and are non-trivial.

This brings us close to no arch-specific code in disas.c allow conversion to common-obj and preparing these arches for inclusion in multi-arch.

I was about to say that this is for individual target maintainers now, for lack of CPUClass changes, but I guess they'll collide in disas.c...

Once it's reviewed I can queue it on qom-cpu-next, unless Peter or someone wants to.

Thanks for your efforts,
Andreas

Signature · 3 lines
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Dilip Upmanyu, Graham Norton; HRB
21284 (AG Nürnberg)
author
#17 lore raw

Ping!

This rebases cleanly following the unfreeze.

Regards,
Peter

Quoted 20 lines · Andreas Färber

Am 12.07.2015 um 03:59 schrieb Peter Crosthwaite:

Quoted 5 lines

Continue QOMifying target-specific disassembly. Convert all arches except for X86 and PPC. They will be round 3 and are non-trivial.

This brings us close to no arch-specific code in disas.c allow conversion to common-obj and preparing these arches for inclusion in multi-arch.

I was about to say that this is for individual target maintainers now, for lack of CPUClass changes, but I guess they'll collide in disas.c...

Once it's reviewed I can queue it on qom-cpu-next, unless Peter or someone wants to.

Thanks for your efforts,
Andreas

--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Dilip Upmanyu, Graham Norton; HRB 21284 (AG Nürnberg)

author
#18 lore raw

Ping^2!

Quoted 28 lines · Peter Crosthwaite

Ping!

This rebases cleanly following the unfreeze.

Regards,
Peter

Quoted 20 lines · Andreas Färber

Am 12.07.2015 um 03:59 schrieb Peter Crosthwaite:

Quoted 5 lines

Continue QOMifying target-specific disassembly. Convert all arches except for X86 and PPC. They will be round 3 and are non-trivial.

This brings us close to no arch-specific code in disas.c allow conversion to common-obj and preparing these arches for inclusion in multi-arch.

I was about to say that this is for individual target maintainers now, for lack of CPUClass changes, but I guess they'll collide in disas.c...

Once it's reviewed I can queue it on qom-cpu-next, unless Peter or someone wants to.

Thanks for your efforts,
Andreas

--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Dilip Upmanyu, Graham Norton; HRB 21284 (AG Nürnberg)

Applied
#19 lore raw
In reply to Andreas Färber

Am 12.07.2015 um 06:18 schrieb Andreas Färber:

Quoted 4 lines

Am 12.07.2015 um 03:59 schrieb Peter Crosthwaite:

Quoted 3 lines

Continue QOMifying target-specific disassembly. Convert all arches except for X86 and PPC. They will be round 3 and are non-trivial.

Quoted 8 lines
Quoted 2 lines

This brings us close to no arch-specific code in disas.c allow conversion to common-obj and preparing these arches for inclusion in multi-arch.

I was about to say that this is for individual target maintainers now, for lack of CPUClass changes, but I guess they'll collide in disas.c...

Once it's reviewed I can queue it on qom-cpu-next, unless Peter or someone wants to.

I have queued them on qom-cpu-next now (subjects to be adjusted), but I am still missing acks for s390x, moxie, sparc and alpha.

https://github.com/afaerber/qemu-cpu/commits/qom-cpu-next

Regards,
Andreas

Quoted 4 lines

Thanks for your efforts,
Andreas

Signature · 2 lines
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton; HRB 21284 (AG Nürnberg)
Acked-by
#20 lore raw
Quoted 8 lines · Andreas Färber

Am 12.07.2015 um 06:18 schrieb Andreas Färber:

Quoted 7 lines

Am 12.07.2015 um 03:59 schrieb Peter Crosthwaite:

Quoted 5 lines

Continue QOMifying target-specific disassembly. Convert all arches except for X86 and PPC. They will be round 3 and are non-trivial.

This brings us close to no arch-specific code in disas.c allow conversion to common-obj and preparing these arches for inclusion in multi-arch.

Quoted 8 lines
Quoted 5 lines

I was about to say that this is for individual target maintainers now, for lack of CPUClass changes, but I guess they'll collide in disas.c...

Once it's reviewed I can queue it on qom-cpu-next, unless Peter or someone wants to.

I have queued them on qom-cpu-next now (subjects to be adjusted), but I am still missing acks for s390x, moxie, sparc and alpha.

Really? I thought I'd given them ages ago. For s390 and alpha at least,

Acked-by Richard Henderson <[email protected]>

r~

#21 lore raw

Am 27.08.2015 um 22:20 schrieb Richard Henderson:

Quoted 17 lines · Andreas Färber
Quoted 16 lines

Am 12.07.2015 um 06:18 schrieb Andreas Färber:

Quoted 14 lines

Am 12.07.2015 um 03:59 schrieb Peter Crosthwaite:

Quoted 7 lines

Continue QOMifying target-specific disassembly. Convert all arches except for
X86 and PPC. They will be round 3 and are non-trivial.

This brings us close to no arch-specific code in disas.c allow conversion to
common-obj and preparing these arches for inclusion in multi-arch.

I was about to say that this is for individual target maintainers now, for lack of CPUClass changes, but I guess they'll collide in disas.c...

Once it's reviewed I can queue it on qom-cpu-next, unless Peter or someone wants to.

Quoted 6 lines
Quoted 2 lines

I have queued them on qom-cpu-next now (subjects to be adjusted), but I am still missing acks for s390x, moxie, sparc and alpha.

Really? I thought I'd given them ages ago. For s390 and alpha at least,

Acked-by Richard Henderson <[email protected]>

Ah, you may have done so on IRC when we discussed who was supposed to handle them, so they didn't show up here. Updated.

Two to go, moxie as the next one untested by Peter.

Thanks,
Andreas

Signature · 2 lines
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton; HRB 21284 (AG Nürnberg)
#22 lore raw
Quoted 1 line · Andreas Färber

Two to go, moxie as the next one untested by Peter.

The last email on qemu-devel from the moxie maintainer was in 2013, so I wouldn't hold your breath.

-- PMM

author
#23 lore raw
Quoted 6 lines · Peter Maydell
Quoted 1 line · Andreas Färber

Two to go, moxie as the next one untested by Peter.

The last email on qemu-devel from the moxie maintainer was in 2013, so I wouldn't hold your breath.

It is also unfortunately the only arch I couldn't get low effort test cases on. I can dig around to see if I can get a basic elf going to bring it up to same level of testing as other archs if we are really worried.

Longer term though, maybe these homogeneous every-arch change patterns should only need a critical mass of acks from the arch maintainers for the whole thing to go through. It's unlikely that I botched moxie with most of the other arches reviewed, so chasing that ack from the last maintainer might not be needed. That or a generic reviewer should be able to ack ones like this, and it's almost candidate for trivial.

Regards,
Peter

Quoted 1 line

-- PMM

#24 lore raw
Quoted 6 lines · Peter Crosthwaite

Longer term though, maybe these homogeneous every-arch change patterns should only need a critical mass of acks from the arch maintainers for the whole thing to go through. It's unlikely that I botched moxie with most of the other arches reviewed, so chasing that ack from the last maintainer might not be needed. That or a generic reviewer should be able to ack ones like this, and it's almost candidate for trivial.

I think that's reasonable. I don't have a great deal of sympathy if the minor architectures break if they don't have maintainers who are willing to actually stick around on qemu-devel and review changes to their code, rather than just dumping a patchset on us and vanishing.

-- PMM