ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr

PATCH Superseded Adrian Alonso 4 participants 11 messages Jul 7, 2015 – Jul 23, 2015

Subsystems (4)

Arm i.MX and Layerscape GPIO Pin control Pin controller - Freescale

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Adrian Alonso

author

2015-07-07 19:02 UTC #0 lore raw

PATCH v3 1/1 ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr

* Extend pinctrl-imx driver to support iomux lpsr conntroller,
* iMX7D has two iomuxc controllers, iomuxc controller similar as previous iMX SoC generation and iomuxc-lpsr which provides low power state rentetion capabilities on gpios that are part of iomuxc-lpsr (GPIO1_IO7..GPIO1_IO0).
* Use IOMUXC_LPSR_SUPPORT and iput_val most significant bits to properly configure iomuxc/iomuxc-lpsr settings.

Signed-off-by Adrian Alonso <[email protected]>

* Change from v1 to v2:
- Add suggested comment for input select register shared between iomuxc-lpsr and normal iomuxc controller.
- Use IOMUXC_LPSR_MASK to extract pad group id and aling pin_id to 16 bit representation.
* Change from v2 to v3
- Use devm_ioremap_resource instead of of_iomap to get iomuxc-lpsr base register address.

---
 drivers/pinctrl/freescale/pinctrl-imx.c | 72 ++++++++++++++++++++++-----------
 drivers/pinctrl/freescale/pinctrl-imx.h |  7 +++-
 2 files changed, 55 insertions(+), 24 deletions(-)

drivers/pinctrl/freescale/pinctrl-imx.c +49 ~~-23~~

index d7b98ba..aef4ca3 100644
@@ -1,7 +1,7 @@
 /*
  * Core driver for the imx pin controller
  *
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc.
  * Copyright (C) 2012 Linaro Ltd.
  *
  * Author: Dong Aisheng <[email protected]>

@@ -38,7 +38,6 @@
 struct imx_pinctrl {
 	struct device *dev;
 	struct pinctrl_dev *pctl;
-	void __iomem *base;
 	const struct imx_pinctrl_soc_info *info;
 };

@@ -212,12 +211,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 
 		if (info->flags & SHARE_MUX_CONF_REG) {
 			u32 reg;
-			reg = readl(ipctl->base + pin_reg->mux_reg);
+			reg = readl(pin_reg->base + pin_reg->mux_reg);
 			reg &= ~(0x7 << 20);
 			reg |= (pin->mux_mode << 20);
-			writel(reg, ipctl->base + pin_reg->mux_reg);
+			writel(reg, pin_reg->base + pin_reg->mux_reg);
 		} else {
-			writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
+			writel(pin->mux_mode, pin_reg->base + pin_reg->mux_reg);
 		}
 		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
 			pin_reg->mux_reg, pin->mux_mode);

@@ -245,16 +244,22 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 			 * The input_reg[i] here is actually some IOMUXC general
 			 * purpose register, not regular select input register.
 			 */
-			val = readl(ipctl->base + pin->input_reg);
+			val = readl(pin_reg->base + pin->input_reg);
 			val &= ~mask;
 			val |= select << shift;
-			writel(val, ipctl->base + pin->input_reg);
+			writel(val, pin_reg->base + pin->input_reg);
 		} else if (pin->input_reg) {
 			/*
 			 * Regular select input register can never be at offset
 			 * 0, and we only print register value for regular case.
 			 */
-			writel(pin->input_val, ipctl->base + pin->input_reg);
+			if (info->flags & IOMUXC_LPSR_SUPPORT &&
+					IOMUXC_LPSR_MASK(pin->input_val))
+			/* iomuxc-lpsr select input register shared with normal iomuxc */
+				writel(pin->input_val, info->base + pin->input_reg);
+			else
+				writel(pin->input_val, pin_reg->base + pin->input_reg);
+
 			dev_dbg(ipctl->dev,
 				"==>select_input: offset 0x%x val 0x%x\n",
 				pin->input_reg, pin->input_val);

@@ -326,10 +331,10 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
 	return -EINVAL;
 
 mux_pin:
-	reg = readl(ipctl->base + pin_reg->mux_reg);
+	reg = readl(pin_reg->base + pin_reg->mux_reg);
 	reg &= ~(0x7 << 20);
 	reg |= imx_pin->config;
-	writel(reg, ipctl->base + pin_reg->mux_reg);
+	writel(reg, pin_reg->base + pin_reg->mux_reg);
 
 	return 0;
 }

@@ -354,12 +359,12 @@ static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 		return -EINVAL;
 
 	/* IBE always enabled allows us to read the value "on the wire" */
-	reg = readl(ipctl->base + pin_reg->mux_reg);
+	reg = readl(pin_reg->base + pin_reg->mux_reg);
 	if (input)
 		reg &= ~0x2;
 	else
 		reg |= 0x2;
-	writel(reg, ipctl->base + pin_reg->mux_reg);
+	writel(reg, pin_reg->base + pin_reg->mux_reg);
 
 	return 0;
 }

@@ -386,7 +391,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 		return -EINVAL;
 	}
 
-	*config = readl(ipctl->base + pin_reg->conf_reg);
+	*config = readl(pin_reg->base + pin_reg->conf_reg);
 
 	if (info->flags & SHARE_MUX_CONF_REG)
 		*config &= 0xffff;

@@ -415,12 +420,12 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 	for (i = 0; i < num_configs; i++) {
 		if (info->flags & SHARE_MUX_CONF_REG) {
 			u32 reg;
-			reg = readl(ipctl->base + pin_reg->conf_reg);
+			reg = readl(pin_reg->base + pin_reg->conf_reg);
 			reg &= ~0xffff;
 			reg |= configs[i];
-			writel(reg, ipctl->base + pin_reg->conf_reg);
+			writel(reg, pin_reg->base + pin_reg->conf_reg);
 		} else {
-			writel(configs[i], ipctl->base + pin_reg->conf_reg);
+			writel(configs[i], pin_reg->base + pin_reg->conf_reg);
 		}
 		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
 			pin_reg->conf_reg, configs[i]);

@@ -442,7 +447,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 		return;
 	}
 
-	config = readl(ipctl->base + pin_reg->conf_reg);
+	config = readl(pin_reg->base + pin_reg->conf_reg);
 	seq_printf(s, "0x%lx", config);
 }

@@ -551,14 +556,25 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
 		}
 
 		pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+
+		pin->input_reg = be32_to_cpu(*list++);
+		pin->mux_mode = be32_to_cpu(*list++);
+		pin->input_val = be32_to_cpu(*list++);
+
+		if (info->flags & IOMUXC_LPSR_SUPPORT &&
+			IOMUXC_LPSR_MASK(pin->input_val))
+				pin_id = IOMUXC_LPSR_MASK(pin->input_val);
+
 		pin_reg = &info->pin_regs[pin_id];
 		pin->pin = pin_id;
 		grp->pin_ids[i] = pin_id;
 		pin_reg->mux_reg = mux_reg;
 		pin_reg->conf_reg = conf_reg;
-		pin->input_reg = be32_to_cpu(*list++);
-		pin->mux_mode = be32_to_cpu(*list++);
-		pin->input_val = be32_to_cpu(*list++);
+		pin_reg->base = info->base;
+
+		if (info->flags & IOMUXC_LPSR_SUPPORT &&
+			IOMUXC_LPSR_MASK(pin->input_val))
+				pin_reg->base = info->base_lpsr;
 
 		/* SION bit is in mux register */
 		config = be32_to_cpu(*list++);

@@ -709,9 +725,19 @@ int imx_pinctrl_probe(struct platform_device *pdev,
 	}
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	ipctl->base = devm_ioremap_resource(&pdev->dev, res);
-	if (IS_ERR(ipctl->base))
-		return PTR_ERR(ipctl->base);
+	info->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(info->base))
+		return PTR_ERR(info->base);
+
+	if (info->flags & IOMUXC_LPSR_SUPPORT) {
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		info->base_lpsr = devm_ioremap_resource(&pdev->dev, res);
+		if (IS_ERR(info->base_lpsr)) {
+			dev_err(&pdev->dev,
+				"iomuxc-lpsr base address not found\n");
+			return PTR_ERR(info->base_lpsr);
+		}
+	}
 
 	imx_pinctrl_desc.name = dev_name(&pdev->dev);
 	imx_pinctrl_desc.pins = info->pins;

drivers/pinctrl/freescale/pinctrl-imx.h +6 -1

index 49e55d3..5e0f2e0 100644
@@ -1,7 +1,7 @@
 /*
  * IMX pinmux core definitions
  *
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc.
  * Copyright (C) 2012 Linaro Ltd.
  *
  * Author: Dong Aisheng <[email protected]>

@@ -69,6 +69,7 @@ struct imx_pmx_func {
 struct imx_pin_reg {
 	s16 mux_reg;
 	s16 conf_reg;
+	void __iomem *base;
 };
 
 struct imx_pinctrl_soc_info {

@@ -81,9 +82,13 @@ struct imx_pinctrl_soc_info {
 	struct imx_pmx_func *functions;
 	unsigned int nfunctions;
 	unsigned int flags;
+	void __iomem *base;
+	void __iomem *base_lpsr;
 };
 
 #define SHARE_MUX_CONF_REG	0x1
+#define IOMUXC_LPSR_SUPPORT 	0x2
+#define IOMUXC_LPSR_MASK(id)	((id >> 0x10) & 0xffff)
 
 #define NO_MUX		0x0
 #define NO_PAD		0x0

Signature · 1 line

2.1.4

Linus Walleij

2015-07-14 09:06 UTC #1 lore raw

PATCH v3 1/1 ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr

Quoted 10 lines · Adrian Alonso

* Extend pinctrl-imx driver to support iomux lpsr conntroller,
* iMX7D has two iomuxc controllers, iomuxc controller similar as previous iMX SoC generation and iomuxc-lpsr which provides low power state rentetion capabilities on gpios that are part of iomuxc-lpsr (GPIO1_IO7..GPIO1_IO0).
* Use IOMUXC_LPSR_SUPPORT and iput_val most significant bits to properly configure iomuxc/iomuxc-lpsr settings.
Signed-off-by Adrian Alonso <[email protected]>

Quoted 8 lines

* Change from v1 to v2:
- Add suggested comment for input select register shared between iomuxc-lpsr and normal iomuxc controller.
- Use IOMUXC_LPSR_MASK to extract pad group id and aling pin_id to 16 bit representation.
* Change from v2 to v3
- Use devm_ioremap_resource instead of of_iomap to get iomuxc-lpsr base register address.

I'm waiting for Shawn to review these patches.

Yours,
Linus Walleij

Shawn Guo

2015-07-15 07:23 UTC #2 lore raw

PATCH v3 1/1 ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr

In reply to Adrian Alonso

Quoted 9 lines · Adrian Alonso

* Extend pinctrl-imx driver to support iomux lpsr conntroller,
* iMX7D has two iomuxc controllers, iomuxc controller similar as previous iMX SoC generation and iomuxc-lpsr which provides low power state rentetion capabilities on gpios that are part of iomuxc-lpsr (GPIO1_IO7..GPIO1_IO0).
* Use IOMUXC_LPSR_SUPPORT and iput_val most significant bits to properly configure iomuxc/iomuxc-lpsr settings.
Signed-off-by Adrian Alonso <[email protected]>

It took me quite some time to understand what the patch does. Before I gave specific comments on your implementation, I would discuss if there is a better solution, as I do not like the idea of encoding these artificial pin id of LPSR pads in the input_val.

Ideally, the LPSR controller should be implemented as a second instance of IOMUXC. But the problem seems to be the select input register is shared between these two instances. Is my understanding correct?

How select input register is shared? With different bits in a single register which is only laid on normal IOMUXC controller?

I need more details to understand the problem.

Shawn

Zhi Li

2015-07-15 13:57 UTC #3 lore raw

PATCH v3 1/1 ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr

Quoted 11 lines · Shawn Guo

Quoted 9 lines · Adrian Alonso
* Extend pinctrl-imx driver to support iomux lpsr conntroller,
* iMX7D has two iomuxc controllers, iomuxc controller similar as previous iMX SoC generation and iomuxc-lpsr which provides low power state rentetion capabilities on gpios that are part of iomuxc-lpsr (GPIO1_IO7..GPIO1_IO0).
* Use IOMUXC_LPSR_SUPPORT and iput_val most significant bits to properly configure iomuxc/iomuxc-lpsr settings.
Signed-off-by Adrian Alonso <[email protected]>

Quoted 8 lines

It took me quite some time to understand what the patch does. Before I gave specific comments on your implementation, I would discuss if there is a better solution, as I do not like the idea of encoding these artificial pin id of LPSR pads in the input_val.
Ideally, the LPSR controller should be implemented as a second instance of IOMUXC. But the problem seems to be the select input register is shared between these two instances. Is my understanding correct?

There are two problem.
1. LPSR IOMUX share input select with IOMUX.
2. If use two instance, the pin ID will be the same. If there are a group mix use LPSR IOMUX and normal IOMUX, system will be confused. For example:

UART_pin:
{
LPSR_IOMUX_RX,
NORMAL_IOMUX_TX,
}

IOMUX driver don't distinguish it.

best regards
Frank Li

Quoted 7 lines

How select input register is shared? With different bits in a single register which is only laid on normal IOMUXC controller?
I need more details to understand the problem.
Shawn

Alonso Adrian

author

2015-07-15 15:55 UTC #4 lore raw

PATCH v3 1/1 ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr

In reply to Shawn Guo

Hi Shawn,

Comments inline, thanks for reviewing :)

Regards
Adrian

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Wednesday, July 15, 2015 2:23 AM
To: Alonso Lazcano Adrian-B38018
Cc: linux-arm-kernel at lists.infradead.org; shawn.guo at linaro.org; linus.walleij at linaro.org; lznuaa at gmail.com; devicetree at vger.kernel.org; Li Frank-B20596; Garg Nitin-B37173; Huang Yongcai-B20788; linux-gpio at vger.kernel.org; robh+dt at kernel.org; Gong Yibin-B38343
Subject: Re: [PATCH][v3] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr

Quoted 9 lines · Adrian Alonso

* Extend pinctrl-imx driver to support iomux lpsr conntroller,
* iMX7D has two iomuxc controllers, iomuxc controller similar as previous iMX SoC generation and iomuxc-lpsr which provides low power state rentetion capabilities on gpios that are part of iomuxc-lpsr (GPIO1_IO7..GPIO1_IO0).
* Use IOMUXC_LPSR_SUPPORT and iput_val most significant bits to properly configure iomuxc/iomuxc-lpsr settings.
Signed-off-by Adrian Alonso <[email protected]>

[Adrian] Yes that's the case SELECT_INPUT register is shared between IOMUXC and IOMUXC-LPSR controllers.

How select input register is shared? With different bits in a single register which is only laid on normal IOMUXC controller?

[Adrian] IOMUXC and IOMUXC-LPSR are in different base address; each controller provides SW_PAD_CTL (CONF_REG) and SW_MUX_CTL (MUX_REG) but only IOMUXC provides SELECT_INPUT registers for pad daisy chain configuration, so pads from IOMUXC-LPSR that need daisy chain settings need to access the IOMUXC register space address to access SELECT_INPUT.

[Adrian] One disadvantage that we found if we created two driver instances for IOMUXC and IOMUXC-LPSR controllers is that in the device tree machine files "end-users" could be creating pinctrl nodes mixing pads from different IOMUXC controllers resulting that pad that doesn't belong to that domain controller it will not be configured properly.

For example a valid pad configuration for I2C1 could use pads as shown below:

&iomuxc {
	pinctrl_i2c1_1: i2c1grp-1 {
		fsl,pins = <
			MX7D_PAD_GPIO1_IO04__I2C1_SCL  	/* IOMUXC-LPSR domain */
			MX7D_PAD_I2C1_SDA__I2C1_SDA   	/* IOMUXC domain */
		>;
	};
};

By extending pinctrl-imx to support both controllers the above configuration is supported, Otherwise using two driver instances "end-users" will need to do something like:

&iomuxc {
	pinctrl_i2c1_1: i2c1grp-1 {
		fsl,pins = <
			MX7D_PAD_I2C1_SDA__I2C1_SDA   	/* IOMUXC domain */
		>;
	};
};

&iomuxc_lpsr {
	pinctrl_i2c1_1: i2c1grp-1 {
		fsl,pins = <
			MX7D_PAD_GPIO1_IO04__I2C1_SCL  	/* IOMUXC-LPSR domain */
		>;
	};
};

And this is something that we will like to avoid so "end-user" don't have to worry about and configure pads as they are used to.

[Adrian] For the artificial encoding of pad group id's for IOMUXC-LPSR, I think there is no other way to do it (limited imagination here :P); Pad group id's are extracted from MUX_REG offset address (pad_id = mux_reg / 4) but when combining both IOMUXC and IOMUXC-LPSR Pad group ID's overlap so end up encoding the pad_id for IOMUXC-LPSR to resolve the proper pad group ID.

I need more details to understand the problem.

Shawn

Shawn Guo

2015-07-16 15:50 UTC #5 lore raw

PATCH v3 1/1 ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr

Adrian,

Please configure your email client to use bottom-posting rather than top-posting.

Quoted 2 lines · Alonso Adrian

[Adrian] IOMUXC and IOMUXC-LPSR are in different base address; each controller provides SW_PAD_CTL (CONF_REG) and SW_MUX_CTL (MUX_REG) but only IOMUXC provides SELECT_INPUT registers for pad daisy chain configuration, so pads from IOMUXC-LPSR that need daisy chain settings need to access the IOMUXC register space address to access SELECT_INPUT.

Thanks for the explanation.

Quoted 31 lines

[Adrian] One disadvantage that we found if we created two driver instances for IOMUXC and IOMUXC-LPSR controllers is that in the device tree machine files "end-users" could be creating pinctrl nodes mixing pads from different IOMUXC controllers resulting that pad that doesn't belong to that domain controller it will not be configured properly.
For example a valid pad configuration for I2C1 could use pads as shown below:
&iomuxc {
	pinctrl_i2c1_1: i2c1grp-1 {
		fsl,pins = <
			MX7D_PAD_GPIO1_IO04__I2C1_SCL  	/* IOMUXC-LPSR domain */
			MX7D_PAD_I2C1_SDA__I2C1_SDA   	/* IOMUXC domain */
		>;
	};
};
By extending pinctrl-imx to support both controllers the above configuration is supported, Otherwise using two driver instances "end-users" will need to do something like:
&iomuxc {
	pinctrl_i2c1_1: i2c1grp-1 {
		fsl,pins = <
			MX7D_PAD_I2C1_SDA__I2C1_SDA   	/* IOMUXC domain */
		>;
	};
};
&iomuxc_lpsr {
	pinctrl_i2c1_1: i2c1grp-1 {
		fsl,pins = <
			MX7D_PAD_GPIO1_IO04__I2C1_SCL  	/* IOMUXC-LPSR domain */
		>;
	};
};

Quoted 2 lines

And this is something that we will like to avoid so "end-user" don't have to worry about and configure pads as they are used to.

This is exactly how hardware is designed, and having device tree describe how hardware is laid out is the right thing to do. In that case, when people check the device tree source with a i.MX7D Reference Manual on hands, they can easily understand how hardware is represented in device tree.

Also, your example with pins for a single device across IOMUXC and IOMUXC-LPSR should be the rare case except GPIO pins. For your I2C1 example, a sane hardware design would chose one group among the following instead of the one you put above.

MX7D_PAD_I2C1_SCL__I2C1_SCL
MX7D_PAD_I2C1_SDA__I2C1_SDA

MX7D_PAD_UART1_RX_DATA__I2C1_SCL
MX7D_PAD_UART1_TX_DATA__I2C1_SDA

MX7D_PAD_GPIO1_IO04__I2C1_SCL
MX7D_PAD_GPIO1_IO05__I2C1_SDA

So this is not really a problem for us to implement two IOMUXC instances. The only problem we need to solve is the select input register access for IOMUXC-LPSR driver. I have some idea for that, i.e. honestly represent how hardware is laid out. I will give more details on that tomorrow.

Quoted 3 lines

[Adrian] For the artificial encoding of pad group id's for IOMUXC-LPSR, I think there is no other way to do it (limited imagination here :P); Pad group id's are extracted from MUX_REG offset address (pad_id = mux_reg / 4) but when combining both IOMUXC and IOMUXC-LPSR Pad group ID's overlap so end up encoding the pad_id for IOMUXC-LPSR to resolve the proper pad group ID.

One big missing piece from your patch is the update to bindings document Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt. Have you thought about how you will document all these magics and hacks you have done here?

Shawn

Zhi Li

2015-07-16 16:22 UTC #6 lore raw

PATCH v3 1/1 ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr

Quoted 45 lines · Shawn Guo

Adrian,
Please configure your email client to use bottom-posting rather than top-posting.
Quoted 2 lines · Alonso Adrian
[Adrian] IOMUXC and IOMUXC-LPSR are in different base address; each controller provides SW_PAD_CTL (CONF_REG) and SW_MUX_CTL (MUX_REG) but only IOMUXC provides SELECT_INPUT registers for pad daisy chain configuration, so pads from IOMUXC-LPSR that need daisy chain settings need to access the IOMUXC register space address to access SELECT_INPUT.
Thanks for the explanation.
Quoted 31 lines
[Adrian] One disadvantage that we found if we created two driver instances for IOMUXC and IOMUXC-LPSR controllers is that in the device tree machine files "end-users" could be creating pinctrl nodes mixing pads from different IOMUXC controllers resulting that pad that doesn't belong to that domain controller it will not be configured properly.
For example a valid pad configuration for I2C1 could use pads as shown below:
&iomuxc {
      pinctrl_i2c1_1: i2c1grp-1 {
              fsl,pins = <
                      MX7D_PAD_GPIO1_IO04__I2C1_SCL   /* IOMUXC-LPSR domain */
                      MX7D_PAD_I2C1_SDA__I2C1_SDA     /* IOMUXC domain */
              >;
      };
};
By extending pinctrl-imx to support both controllers the above configuration is supported, Otherwise using two driver instances "end-users" will need to do something like:
&iomuxc {
      pinctrl_i2c1_1: i2c1grp-1 {
              fsl,pins = <
                      MX7D_PAD_I2C1_SDA__I2C1_SDA     /* IOMUXC domain */
              >;
      };
};
&iomuxc_lpsr {
      pinctrl_i2c1_1: i2c1grp-1 {
              fsl,pins = <
                      MX7D_PAD_GPIO1_IO04__I2C1_SCL   /* IOMUXC-LPSR domain */
              >;
      };
};
Quoted 2 lines
And this is something that we will like to avoid so "end-user" don't have to worry about and configure pads as they are used to.

Quoted 8 lines

This is exactly how hardware is designed, and having device tree describe how hardware is laid out is the right thing to do. In that case, when people check the device tree source with a i.MX7D Reference Manual on hands, they can easily understand how hardware is represented in device tree.
Also, your example with pins for a single device across IOMUXC and IOMUXC-LPSR should be the rare case except GPIO pins.

Although cross IOMUX and IOMUXC-LPSR is rare, it will be headache if there are one boards.

Some SD card, ENET have reset\wp\cd pin.

pinctrl_usdhc1: usdhc1grp {
                        fsl,pins = <
                                MX7D_PAD_SD1_CMD__SD1_CMD               0x59
                                MX7D_PAD_SD1_CLK__SD1_CLK               0x19
                                MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
                                MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
                                MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
                                MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
                                MX7D_PAD_SD1_CD_B__GPIO5_IO0
 0x59 /* CD */
                                MX7D_PAD_SD1_WP__GPIO5_IO1
 0x59 /* WP */
                                MX7D_PAD_SD1_RESET_B__GPIO5_IO2
 0x59 /* vmmc */
                        >;

Customer may choose below pin to IOMUX-lPSR.

MX7D_PAD_SD1_CD_B__GPIO5_IO0
MX7D_PAD_SD1_WP__GPIO5_IO1
MX7D_PAD_SD1_RESET_B__GPIO5_IO2

FEC have Phy Reset GPIO, which possibly choose IOMUX-lPSR.

Quoted 10 lines

For your I2C1
example, a sane hardware design would chose one group among the following instead of the one you put above.
MX7D_PAD_I2C1_SCL__I2C1_SCL
MX7D_PAD_I2C1_SDA__I2C1_SDA
MX7D_PAD_UART1_RX_DATA__I2C1_SCL
MX7D_PAD_UART1_TX_DATA__I2C1_SDA

Quoted 8 lines

MX7D_PAD_GPIO1_IO04__I2C1_SCL
MX7D_PAD_GPIO1_IO05__I2C1_SDA
So this is not really a problem for us to implement two IOMUXC instances. The only problem we need to solve is the select input register access for IOMUXC-LPSR driver. I have some idea for that, i.e. honestly represent how hardware is laid out. I will give more details on that tomorrow.

It is very easy to make mistake.
According to pin NAME macro, it is not easy to distinguish between IOMUX and IOMUX-LPSR.

Internal kernel tree use two pinctrl instance.

It will be simple if we think IOMUX and IOMUX-LPSR together, and one module have two group registers.

best regards
Frank Li

Quoted 11 lines

Quoted 4 lines
[Adrian] For the artificial encoding of pad group id's for IOMUXC-LPSR, I think there is no other way to do it (limited imagination here :P); Pad group id's are extracted from MUX_REG offset address (pad_id = mux_reg / 4) but when combining both IOMUXC and IOMUXC-LPSR Pad group ID's overlap so end up encoding the pad_id for IOMUXC-LPSR to resolve the proper pad group ID.
One big missing piece from your patch is the update to bindings document Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt. Have you thought about how you will document all these magics and hacks you have done here?
Shawn

Alonso Adrian

author

2015-07-16 20:39 UTC #7 lore raw

PATCH v3 1/1 ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr

Hi All,

I will sent a new patch series including documentation for pad group id encoding in Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt

Thanks for your comments :)
-
Adrian

Quoted 156 lines

-----Original Message-----
From: Zhi Li [mailto:lznuaa at gmail.com]
Sent: Thursday, July 16, 2015 11:22 AM
To: Shawn Guo
Cc: Alonso Lazcano Adrian-B38018; devicetree at vger.kernel.org; Li Frank- B20596; Garg Nitin-B37173; linus.walleij at linaro.org; linux- gpio at vger.kernel.org; robh+dt at kernel.org; shawn.guo at linaro.org; Huang Yongcai-B20788; linux-arm-kernel at lists.infradead.org; Gong Yibin-B38343
Subject: Re: [PATCH][v3] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr
Quoted 7 lines · Shawn Guo
Adrian,
Please configure your email client to use bottom-posting rather than top-posting.
Quoted 1 line · Alonso Adrian
[Adrian] IOMUXC and IOMUXC-LPSR are in different base address; each
controller provides SW_PAD_CTL (CONF_REG) and SW_MUX_CTL (MUX_REG) but only IOMUXC provides SELECT_INPUT registers for pad daisy chain configuration, so pads from IOMUXC-LPSR that need daisy chain settings need to access the IOMUXC register space address to access SELECT_INPUT.
Quoted 5 lines
Quoted 1 line
Thanks for the explanation.
Quoted 1 line
[Adrian] One disadvantage that we found if we created two driver instances
for IOMUXC and IOMUXC-LPSR controllers is that in the device tree machine files "end-users" could be creating pinctrl nodes mixing pads from different IOMUXC controllers resulting that pad that doesn't belong to that domain controller it will not be configured properly.
Quoted 2 lines
Quoted 2 lines
For example a valid pad configuration for I2C1 could use pads as shown
below:
Quoted 4 lines
Quoted 4 lines
&iomuxc {
      pinctrl_i2c1_1: i2c1grp-1 {
              fsl,pins = <
                      MX7D_PAD_GPIO1_IO04__I2C1_SCL   /* IOMUXC-LPSR domain
*/
Quoted 7 lines
Quoted 7 lines
                      MX7D_PAD_I2C1_SDA__I2C1_SDA     /* IOMUXC domain */
              >;
      };
};
By extending pinctrl-imx to support both controllers the above configuration is supported, Otherwise using two driver instances "end-
users" will need to do something like:
Quoted 9 lines
Quoted 9 lines
&iomuxc {
      pinctrl_i2c1_1: i2c1grp-1 {
              fsl,pins = <
                      MX7D_PAD_I2C1_SDA__I2C1_SDA     /* IOMUXC domain */
              >;
      };
};
Quoted 4 lines
Quoted 4 lines
&iomuxc_lpsr {
      pinctrl_i2c1_1: i2c1grp-1 {
              fsl,pins = <
                      MX7D_PAD_GPIO1_IO04__I2C1_SCL   /* IOMUXC-LPSR domain
*/
Quoted 5 lines
Quoted 5 lines
              >;
      };
};
And this is something that we will like to avoid so "end-user" don't have to
worry about and configure pads as they are used to.
Quoted 10 lines
Quoted 1 line
This is exactly how hardware is designed, and having device tree describe how hardware is laid out is the right thing to do. In that case, when people check the device tree source with a i.MX7D Reference Manual on hands, they can easily understand how hardware is represented in device tree.
Also, your example with pins for a single device across IOMUXC and IOMUXC-LPSR should be the rare case except GPIO pins.
Although cross IOMUX and IOMUXC-LPSR is rare, it will be headache if there are one boards.
Some SD card, ENET have reset\wp\cd pin.
pinctrl_usdhc1: usdhc1grp {
                        fsl,pins = <
                                MX7D_PAD_SD1_CMD__SD1_CMD               0x59
                                MX7D_PAD_SD1_CLK__SD1_CLK               0x19
                                MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
                                MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
                                MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
                                MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
                                MX7D_PAD_SD1_CD_B__GPIO5_IO0
 0x59 /* CD */
                                MX7D_PAD_SD1_WP__GPIO5_IO1
 0x59 /* WP */
                                MX7D_PAD_SD1_RESET_B__GPIO5_IO2
 0x59 /* vmmc */
                        >;
Customer may choose below pin to IOMUX-lPSR.
MX7D_PAD_SD1_CD_B__GPIO5_IO0
MX7D_PAD_SD1_WP__GPIO5_IO1
MX7D_PAD_SD1_RESET_B__GPIO5_IO2
FEC have Phy Reset GPIO, which possibly choose IOMUX-lPSR.
Quoted 10 lines
For your I2C1
example, a sane hardware design would chose one group among the following instead of the one you put above.
MX7D_PAD_I2C1_SCL__I2C1_SCL
MX7D_PAD_I2C1_SDA__I2C1_SDA
MX7D_PAD_UART1_RX_DATA__I2C1_SCL
MX7D_PAD_UART1_TX_DATA__I2C1_SDA
Quoted 8 lines
MX7D_PAD_GPIO1_IO04__I2C1_SCL
MX7D_PAD_GPIO1_IO05__I2C1_SDA
So this is not really a problem for us to implement two IOMUXC instances. The only problem we need to solve is the select input register access for IOMUXC-LPSR driver. I have some idea for that, i.e. honestly represent how hardware is laid out. I will give more details on that tomorrow.
It is very easy to make mistake.
According to pin NAME macro, it is not easy to distinguish between IOMUX and IOMUX-LPSR.
Internal kernel tree use two pinctrl instance.
It will be simple if we think IOMUX and IOMUX-LPSR together, and one module have two group registers.
best regards
Frank Li
Quoted 4 lines
Quoted 4 lines
[Adrian] For the artificial encoding of pad group id's for IOMUXC-LPSR, I think there is no other way to do it (limited imagination here :P); Pad group id's are extracted from MUX_REG offset
address (pad_id = mux_reg / 4) but when combining both IOMUXC and IOMUXC-LPSR Pad group ID's overlap so end up encoding the pad_id for IOMUXC-LPSR to resolve the proper pad group ID.
Quoted 5 lines
One big missing piece from your patch is the update to bindings document Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt. Have you thought about how you will document all these magics and hacks you
have done here?
Quoted 2 lines
Shawn

Shawn Guo

2015-07-17 03:34 UTC #8 lore raw

PATCH v3 1/1 ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr

Quoted 6 lines · Alonso Adrian

Hi All,
I will sent a new patch series including documentation for pad group id encoding in Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
Thanks for your comments :)

Do not get me wrong. The problem with the patch is not merely missing the document update.

Shawn

Alonso Adrian

author

2015-07-23 19:34 UTC #9 lore raw

PATCH v3 1/1 ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr

Hi Shawn,

The approach you mention is already supported in FSL kernel tree see
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.14.38_6ul7d_beta&id=a37ea06ddccbefb8660af0ac259c30d98540bdc2

I will rework and proposed a new patch series soon.

Thanks for your reviews :)

Regards
Adrian

Quoted 29 lines

-----Original Message-----
From: linux-gpio-owner at vger.kernel.org [mailto:linux-gpio-
owner at vger.kernel.org] On Behalf Of Shawn Guo
Sent: Thursday, July 16, 2015 10:34 PM
To: Alonso Lazcano Adrian-B38018
Cc: Zhi Li; devicetree at vger.kernel.org; Li Frank-B20596; Garg Nitin-B37173; linus.walleij at linaro.org; linux-gpio at vger.kernel.org; robh+dt at kernel.org; shawn.guo at linaro.org; Huang Yongcai-B20788; linux-arm-
kernel at lists.infradead.org; Gong Yibin-B38343
Subject: Re: [PATCH][v3] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr
Quoted 7 lines · Alonso Adrian
Hi All,
I will sent a new patch series including documentation for pad group id encoding in Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
Thanks for your comments :)
Do not get me wrong. The problem with the patch is not merely missing the document update.
Shawn
--
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Shawn Guo

2015-07-17 03:31 UTC #10 lore raw

PATCH v3 1/1 ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr

In reply to Zhi Li

Quoted 22 lines · Zhi Li

On Thu, Jul 16, 2015 at 10:50 AM, Shawn Guo <[email protected]> wrote:
Although cross IOMUX and IOMUXC-LPSR is rare, it will be headache if there are one boards.

Some SD card, ENET have reset\wp\cd pin.

pinctrl_usdhc1: usdhc1grp {
                        fsl,pins = <
                                MX7D_PAD_SD1_CMD__SD1_CMD               0x59
                                MX7D_PAD_SD1_CLK__SD1_CLK               0x19
                                MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
                                MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
                                MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
                                MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
                                MX7D_PAD_SD1_CD_B__GPIO5_IO0
 0x59 /* CD */
                                MX7D_PAD_SD1_WP__GPIO5_IO1
 0x59 /* WP */
                                MX7D_PAD_SD1_RESET_B__GPIO5_IO2
 0x59 /* vmmc */
                        >;

Quoted 7 lines

Customer may choose below pin to IOMUX-lPSR.
MX7D_PAD_SD1_CD_B__GPIO5_IO0
MX7D_PAD_SD1_WP__GPIO5_IO1
MX7D_PAD_SD1_RESET_B__GPIO5_IO2
FEC have Phy Reset GPIO, which possibly choose IOMUX-lPSR.

I do not understand why it would be a headache. The following is what I have in my head, and I think it's nicer and easier to implement. Most importantly, this maps how hardware is laid out exactly, save us all those magics and hacks.

iomuxc: iomuxc at 30330000 {
	compatible = "fsl,imx7d-iomuxc";
	reg = <0x30330000 0x10000>;
};

iomuxc_lpsr: iomuxc-lpsr at 302c0000 {
	compatible = "fsl,imx7d-iomuxc-lpsr";
	reg = <0x302c0000 0x10000>;
	fsl,select-input-controller = <&iomuxc>;
};

&iomuxc {
	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX7D_PAD_SD1_CMD__SD1_CMD	0x59
			MX7D_PAD_SD1_CLK__SD1_CLK	0x19
			MX7D_PAD_SD1_DATA0__SD1_DATA0	0x59
			MX7D_PAD_SD1_DATA1__SD1_DATA1	0x59
			MX7D_PAD_SD1_DATA2__SD1_DATA2	0x59
			MX7D_PAD_SD1_DATA3__SD1_DATA3	0x59
		>;
	};
};

&iomuxc_lpsr {
	pinctrl_usdhc1_lpsr: usdhc1lpsrgrp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO0__GPIO1_IO0  0x59 /* CD */
			MX7D_PAD_LPSR_GPIO1_IO1__GPIO1_IO1  0x59 /* WP */
			MX7D_PAD_LPSR_GPIO1_IO2__GPIO1_IO2  0x59 /* vmmc */
		>;
	};
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_lpsr>;
};

Quoted 3 lines

It is very easy to make mistake.
According to pin NAME macro, it is not easy to distinguish between IOMUX and IOMUX-LPSR.

That's easy to resolve. As I demonstrated above, having LPSR in the macro names and putting all those LPSR pad macros in a separate header like imx7d-lpsr-pinfunc.h would make it easy to remember.

Quoted 1 line

Internal kernel tree use two pinctrl instance.

I think this is the right approach. You should post that solution for upstream instead.

Quoted 2 lines

It will be simple if we think IOMUX and IOMUX-LPSR together, and one module have two group registers.

No, they are two instances of IOMUX controller from perspective of hardware design. And Linux pinctrl subsystem is well-designed to fit there.

Shawn