LPC18xx DTS changes for 4.3
Subsystems (3)
cover LPC18xx DTS changes for 4.3
This patch set adds DT nodes for all the drivers that went upstream in 4.2 and should represent the bulk of DTS changes for 4.3. All nodes added are documented and some of patches carries a ack from subsystem maintainer. It also features updates to the EA4357 dev- kit and a new board from Ezequiel Garcia.
Note that there might be one more batch of DTS changes for 4.3 if any new drivers goes upstream and also some changes for the Hitex eval board might come.
Patches also available on:
https://github.com/manabian/linux-lpc.git lpc18xx_43xx_dts_4.3
Ezequiel Garcia (2):
of: add vendor prefix for CIAA project
ARM: dts: add DT for CIAA LPC4337 industrial computer
Joachim Eastwood (15):
ARM: dts: lpc18xx: add cgu and ccu clock-controller nodes
ARM: dts: lpc18xx: add uart new compat string and clk names
ARM: dts: lpc18xx: add pinctrl node
ARM: dts: lpc18xx: add gpio node
ARM: dts: lpc18xx: add ssp nodes
ARM: dts: lpc18xx: add can nodes
ARM: dts: lpc18xx: add mmcsd node
ARM: dts: lpc18xx: add creg (syscon) node
ARM: dts: lpc18xx: add ethernet node
ARM: dts: lpc18xx: add usb nodes
ARM: dts: lpc4357-ea4357: add pinctrl and uart0 muxing
ARM: dts: lpc4357-ea4357: add mmcsd
ARM: dts: lpc4357-ea4357: add gpio joystick
ARM: dts: lpc4357-ea4357: add ethernet
ARM: dts: lpc4357-ea4357: add uart3
.../devicetree/bindings/vendor-prefixes.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/lpc18xx.dtsi | 235 +++++++++++++++++++-- arch/arm/boot/dts/lpc4337-ciaa.dts | 187 ++++++++++++++++ arch/arm/boot/dts/lpc4350-hitex-eval.dts | 4 - arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 214 +++++++++++++++++++ 6 files changed, 620 insertions(+), 22 deletions(-) create mode 100644 arch/arm/boot/dts/lpc4337-ciaa.dts
Signature · 1 line
1.8.0
PATCH 1/17 ARM: dts: lpc18xx: add cgu and ccu clock-controller nodes
Add CGU and CCU clock-controller nodes for lpc18xx together with the fixed input clocks. Also remove the temporary fixed-factor pll1 clock from both lpc18xx and lpc4350-hitex-eval DTS now that proper clock drivers are inplace.
Signed-off-by Joachim Eastwood <[email protected]>
--- arch/arm/boot/dts/lpc18xx.dtsi | 85 ++++++++++++++++++++++++++------ arch/arm/boot/dts/lpc4350-hitex-eval.dts | 4 -- 2 files changed, 71 insertions(+), 18 deletions(-)
arch/arm/boot/dts/lpc18xx.dtsi +71 -14
@@ -13,6 +13,9 @@ #include "armv7-m.dtsi" +#include "dt-bindings/clock/lpc18xx-cgu.h" +#include "dt-bindings/clock/lpc18xx-ccu.h" + / { cpus { #address-cells = <1>;
@@ -22,6 +25,7 @@ compatible = "arm,cortex-m3"; device_type = "cpu"; reg = <0x0>; + clocks = <&ccu1 CLK_CPU_CORE>; }; };
@@ -32,23 +36,76 @@ clock-frequency = <12000000>; }; - /* Temporary hardcode PLL1 until clk drivers are merged */ - pll1: pll1 { - compatible = "fixed-factor-clock"; - clocks = <&xtal>; + xtal32: xtal32 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + enet_rx_clk: enet_rx_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "enet_rx_clk"; + }; + + enet_tx_clk: enet_tx_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "enet_tx_clk"; + }; + + gp_clkin: gp_clkin { + compatible = "fixed-clock"; #clock-cells = <0>; - clock-div = <1>; - clock-mult = <12>; + clock-frequency = <0>; + clock-output-names = "gp_clkin"; }; }; soc { + cgu: clock-controller at 40050000 { + compatible = "nxp,lpc1850-cgu"; + reg = <0x40050000 0x1000>; + #clock-cells = <1>; + clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; + }; + + ccu1: clock-controller at 40051000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40051000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, + <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, + <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, + <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; + clock-names = "base_apb3_clk", "base_apb1_clk", + "base_spifi_clk", "base_cpu_clk", + "base_periph_clk", "base_usb0_clk", + "base_usb1_clk", "base_spi_clk"; + }; + + ccu2: clock-controller at 40052000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40052000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, + <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, + <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, + <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; + clock-names = "base_audio_clk", "base_uart3_clk", + "base_uart2_clk", "base_uart1_clk", + "base_uart0_clk", "base_ssp1_clk", + "base_ssp0_clk", "base_sdio_clk"; + }; + uart0: serial at 40081000 { compatible = "ns16550a"; reg = <0x40081000 0x1000>; reg-shift = <2>; interrupts = <24>; - clocks = <&pll1>; + clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; status = "disabled"; };
@@ -57,7 +114,7 @@ reg = <0x40082000 0x1000>; reg-shift = <2>; interrupts = <25>; - clocks = <&pll1>; + clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; status = "disabled"; };
@@ -65,7 +122,7 @@ compatible = "nxp,lpc3220-timer"; reg = <0x40084000 0x1000>; interrupts = <12>; - clocks = <&pll1>; + clocks = <&ccu1 CLK_CPU_TIMER0>; clock-names = "timerclk"; };
@@ -73,7 +130,7 @@ compatible = "nxp,lpc3220-timer"; reg = <0x40085000 0x1000>; interrupts = <13>; - clocks = <&pll1>; + clocks = <&ccu1 CLK_CPU_TIMER1>; clock-names = "timerclk"; };
@@ -82,7 +139,7 @@ reg = <0x400c1000 0x1000>; reg-shift = <2>; interrupts = <26>; - clocks = <&pll1>; + clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; status = "disabled"; };
@@ -91,7 +148,7 @@ reg = <0x400c2000 0x1000>; reg-shift = <2>; interrupts = <27>; - clocks = <&pll1>; + clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; status = "disabled"; };
@@ -99,7 +156,7 @@ compatible = "nxp,lpc3220-timer"; reg = <0x400c3000 0x1000>; interrupts = <14>; - clocks = <&pll1>; + clocks = <&ccu1 CLK_CPU_TIMER2>; clock-names = "timerclk"; };
@@ -107,7 +164,7 @@ compatible = "nxp,lpc3220-timer"; reg = <0x400c4000 0x1000>; interrupts = <15>; - clocks = <&pll1>; + clocks = <&ccu1 CLK_CPU_TIMER3>; clock-names = "timerclk"; }; };
arch/arm/boot/dts/lpc4350-hitex-eval.dts +0 -4
@@ -36,10 +36,6 @@ }; }; -&pll1 { - clock-mult = <15>; -}; - &uart0 { status = "okay"; };
Signature · 1 line
1.8.0
PATCH 2/17 ARM: dts: lpc18xx: add uart new compat string and clk names
In reply to Joachim EastwoodAdd lpc1850-uart compatible string on uarts together with proper clock-names.
Signed-off-by Joachim Eastwood <[email protected]>
--- arch/arm/boot/dts/lpc18xx.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)
arch/arm/boot/dts/lpc18xx.dtsi +8 -4
@@ -101,20 +101,22 @@ }; uart0: serial at 40081000 { - compatible = "ns16550a"; + compatible = "nxp,lpc1850-uart", "ns16550a"; reg = <0x40081000 0x1000>; reg-shift = <2>; interrupts = <24>; clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; + clock-names = "uartclk", "reg"; status = "disabled"; }; uart1: serial at 40082000 { - compatible = "ns16550a"; + compatible = "nxp,lpc1850-uart", "ns16550a"; reg = <0x40082000 0x1000>; reg-shift = <2>; interrupts = <25>; clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; + clock-names = "uartclk", "reg"; status = "disabled"; };
@@ -135,20 +137,22 @@ }; uart2: serial at 400c1000 { - compatible = "ns16550a"; + compatible = "nxp,lpc1850-uart", "ns16550a"; reg = <0x400c1000 0x1000>; reg-shift = <2>; interrupts = <26>; clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; + clock-names = "uartclk", "reg"; status = "disabled"; }; uart3: serial at 400c2000 { - compatible = "ns16550a"; + compatible = "nxp,lpc1850-uart", "ns16550a"; reg = <0x400c2000 0x1000>; reg-shift = <2>; interrupts = <27>; clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; + clock-names = "uartclk", "reg"; status = "disabled"; };
Signature · 1 line
1.8.0
PATCH 3/17 ARM: dts: lpc18xx: add pinctrl node
In reply to Joachim EastwoodAdd pinctrl node for lpc1850-scu.
Signed-off-by Joachim Eastwood <[email protected]>
Acked-by Linus Walleij <[email protected]>
--- arch/arm/boot/dts/lpc18xx.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)
arch/arm/boot/dts/lpc18xx.dtsi +6 -0
@@ -136,6 +136,12 @@ clock-names = "timerclk"; }; + pinctrl: pinctrl at 40086000 { + compatible = "nxp,lpc1850-scu"; + reg = <0x40086000 0x1000>; + clocks = <&ccu1 CLK_CPU_SCU>; + }; + uart2: serial at 400c1000 { compatible = "nxp,lpc1850-uart", "ns16550a"; reg = <0x400c1000 0x1000>;
Signature · 1 line
1.8.0
PATCH 4/17 ARM: dts: lpc18xx: add gpio node
In reply to Joachim EastwoodAdd gpio and mapping between pinctrl/gpio namespace with gpio-ranges property.
Signed-off-by Joachim Eastwood <[email protected]>
Acked-by Linus Walleij <[email protected]>
--- arch/arm/boot/dts/lpc18xx.dtsi | 51 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+)
arch/arm/boot/dts/lpc18xx.dtsi +51 -0
@@ -16,6 +16,9 @@ #include "dt-bindings/clock/lpc18xx-cgu.h" #include "dt-bindings/clock/lpc18xx-ccu.h" +#define LPC_PIN(port, pin) (0x##port * 32 + pin) +#define LPC_GPIO(port, pin) (port * 32 + pin) + / { cpus { #address-cells = <1>;
@@ -177,5 +180,53 @@ clocks = <&ccu1 CLK_CPU_TIMER3>; clock-names = "timerclk"; }; + + gpio: gpio at 400f4000 { + compatible = "nxp,lpc1850-gpio"; + reg = <0x400f4000 0x4000>; + clocks = <&ccu1 CLK_CPU_GPIO>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, + <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>, + <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>, + <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>, + <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>, + <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>, + <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>, + <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>, + <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>, + <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>, + <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>, + <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>, + <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>, + <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>, + <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>, + <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>, + <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>, + <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>, + <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>, + <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>, + <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>, + <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>, + <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>, + <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>, + <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>, + <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>, + <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>, + <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>, + <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>, + <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>, + <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>, + <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>, + <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>, + <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>, + <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>, + <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>, + <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>, + <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>, + <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>, + <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; + }; }; };
Signature · 1 line
1.8.0
PATCH 5/17 ARM: dts: lpc18xx: add ssp nodes
In reply to Joachim EastwoodAdd nodes for the ARM SSP controllers on lpc18xx.
Signed-off-by Joachim Eastwood <[email protected]>
--- arch/arm/boot/dts/lpc18xx.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
arch/arm/boot/dts/lpc18xx.dtsi +22 -0
@@ -123,6 +123,17 @@ status = "disabled"; }; + ssp0: spi at 40083000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x40083000 0x1000>; + interrupts = <22>; + clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>; + clock-names = "sspclk", "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + timer0: timer at 40084000 { compatible = "nxp,lpc3220-timer"; reg = <0x40084000 0x1000>;
@@ -181,6 +192,17 @@ clock-names = "timerclk"; }; + ssp1: spi at 400c5000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x400c5000 0x1000>; + interrupts = <23>; + clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>; + clock-names = "sspclk", "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpio: gpio at 400f4000 { compatible = "nxp,lpc1850-gpio"; reg = <0x400f4000 0x4000>;
Signature · 1 line
1.8.0
PATCH 6/17 ARM: dts: lpc18xx: add can nodes
In reply to Joachim EastwoodSigned-off-by Joachim Eastwood <[email protected]>
--- arch/arm/boot/dts/lpc18xx.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
arch/arm/boot/dts/lpc18xx.dtsi +16 -0
@@ -156,6 +156,14 @@ clocks = <&ccu1 CLK_CPU_SCU>; }; + can1: can at 400a4000 { + compatible = "bosch,c_can"; + reg = <0x400a4000 0x1000>; + interrupts = <43>; + clocks = <&ccu1 CLK_APB1_CAN1>; + status = "disabled"; + }; + uart2: serial at 400c1000 { compatible = "nxp,lpc1850-uart", "ns16550a"; reg = <0x400c1000 0x1000>;
@@ -203,6 +211,14 @@ status = "disabled"; }; + can0: can at 400e2000 { + compatible = "bosch,c_can"; + reg = <0x400e2000 0x1000>; + interrupts = <51>; + clocks = <&ccu1 CLK_APB3_CAN0>; + status = "disabled"; + }; + gpio: gpio at 400f4000 { compatible = "nxp,lpc1850-gpio"; reg = <0x400f4000 0x4000>;
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1.8.0
PATCH 7/17 ARM: dts: lpc18xx: add mmcsd node
In reply to Joachim EastwoodSigned-off-by Joachim Eastwood <[email protected]>
--- arch/arm/boot/dts/lpc18xx.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
arch/arm/boot/dts/lpc18xx.dtsi +10 -0
@@ -68,6 +68,16 @@ }; soc { + mmcsd: mmcsd at 40004000 { + compatible = "snps,dw-mshc"; + reg = <0x40004000 0x1000>; + interrupts = <6>; + num-slots = <1>; + clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>; + clock-names = "ciu", "biu"; + status = "disabled"; + }; + cgu: clock-controller at 40050000 { compatible = "nxp,lpc1850-cgu"; reg = <0x40050000 0x1000>;
Signature · 1 line
1.8.0
PATCH 8/17 ARM: dts: lpc18xx: add creg (syscon) node
In reply to Joachim EastwoodThe CREG block contains a collection of miscellaneous configuration register like Ethernet phy mode, low power clocks and DMA multiplexer. These registers needs to be accessed from other drivers and syscon provides this capability.
Signed-off-by Joachim Eastwood <[email protected]>
--- arch/arm/boot/dts/lpc18xx.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)
arch/arm/boot/dts/lpc18xx.dtsi +6 -0
@@ -78,6 +78,12 @@ status = "disabled"; }; + creg: syscon at 40043000 { + compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; + reg = <0x40043000 0x1000>; + clocks = <&ccu1 CLK_CPU_CREG>; + }; + cgu: clock-controller at 40050000 { compatible = "nxp,lpc1850-cgu"; reg = <0x40050000 0x1000>;
Signature · 1 line
1.8.0
PATCH 9/17 ARM: dts: lpc18xx: add ethernet node
In reply to Joachim EastwoodSigned-off-by Joachim Eastwood <[email protected]>
--- arch/arm/boot/dts/lpc18xx.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
arch/arm/boot/dts/lpc18xx.dtsi +10 -0
@@ -78,6 +78,16 @@ status = "disabled"; }; + mac: ethernet at 40010000 { + compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; + reg = <0x40010000 0x2000>; + interrupts = <5>; + interrupt-names = "macirq"; + clocks = <&ccu1 CLK_CPU_ETHERNET>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + creg: syscon at 40043000 { compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; reg = <0x40043000 0x1000>;
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1.8.0
PATCH 10/17 ARM: dts: lpc18xx: add usb nodes
In reply to Joachim EastwoodAdd nodes for the two USB EHCI controllers found on lpc18xx.
Signed-off-by Joachim Eastwood <[email protected]>
--- arch/arm/boot/dts/lpc18xx.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
arch/arm/boot/dts/lpc18xx.dtsi +17 -0
@@ -78,6 +78,23 @@ status = "disabled"; }; + usb0: ehci at 40006100 { + compatible = "nxp,lpc1850-ehci", "generic-ehci"; + reg = <0x40006100 0x100>; + interrupts = <8>; + clocks = <&ccu1 CLK_CPU_USB0>; + has-transaction-translator; + status = "disabled"; + }; + + usb1: ehci at 40007100 { + compatible = "nxp,lpc1850-ehci", "generic-ehci"; + reg = <0x40007100 0x100>; + interrupts = <9>; + clocks = <&ccu1 CLK_CPU_USB1>; + status = "disabled"; + }; + mac: ethernet at 40010000 { compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; reg = <0x40010000 0x2000>;
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1.8.0
PATCH 11/17 ARM: dts: lpc4357-ea4357: add pinctrl and uart0 muxing
In reply to Joachim EastwoodSetup pin muxing and properties for the debug console on uart0.
Signed-off-by Joachim Eastwood <[email protected]>
Acked-by Linus Walleij <[email protected]>
--- arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +20 -0
@@ -36,6 +36,26 @@ }; }; +&pinctrl { + uart0_pins: uart0-pins { + uart0_rx_cfg { + pins = "pf_11"; + function = "uart0"; + input-schmitt-disable; + bias-disable; + input-enable; + }; + + uart0_tx_cfg { + pins = "pf_10"; + function = "uart0"; + bias-pull-down; + }; + }; +}; + &uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; };
Signature · 1 line
1.8.0
PATCH 12/17 ARM: dts: lpc4357-ea4357: add mmcsd
In reply to Joachim EastwoodEnable the MMC/SD controller on EA4357 devkit and add pin muxing plus a regulator.
Signed-off-by Joachim Eastwood <[email protected]>
--- arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 47 +++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+)
arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +47 -0
@@ -34,9 +34,48 @@ device_type = "memory"; reg = <0x28000000 0x2000000>; /* 32 MB */ }; + + /* vmmc is controlled by sdmmc host internally */ + vmmc: vmmc_fixed { + compatible = "regulator-fixed"; + regulator-name = "vmmc-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &pinctrl { + sdmmc_pins: sdmmc-pins { + sdmmc_clk_cfg { + pins = "pc_0"; + function = "sdmmc"; + slew-rate = <1>; + bias-pull-down; + }; + + sdmmc_cmd_dat0_3_cfg { + pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10"; + function = "sdmmc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + sdmmc_cd_cfg { + pins = "pc_8"; + function = "sdmmc"; + bias-pull-down; + input-enable; + }; + + sdmmc_pow_cfg { + pins = "pc_9"; + function = "sdmmc"; + bias-pull-down; + }; + }; + uart0_pins: uart0-pins { uart0_rx_cfg { pins = "pf_11";
@@ -54,6 +93,14 @@ }; }; +&mmcsd { + status = "okay"; + bus-width = <4>; + vmmc-supply = <&vmmc>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pins>; +}; + &uart0 { status = "okay"; pinctrl-names = "default";
Signature · 1 line
1.8.0
PATCH 13/17 ARM: dts: lpc4357-ea4357: add gpio joystick
In reply to Joachim EastwoodHook up the small joystick found on the EA4357 devkit.
Signed-off-by Joachim Eastwood <[email protected]>
--- arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 52 +++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+)
arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +52 -0
@@ -15,6 +15,9 @@ #include "lpc18xx.dtsi" #include "lpc4357.dtsi" +#include "dt-bindings/input/input.h" +#include "dt-bindings/gpio/gpio.h" + / { model = "Embedded Artists' LPC4357 Developer's Kit"; compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350";
@@ -42,9 +45,58 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + gpio_joystick { + compatible = "gpio-keys-polled"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_joystick_pins>; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + autorepeat; + + button at 0 { + label = "joy_enter"; + linux,code = <KEY_ENTER>; + gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>; + }; + + button at 1 { + label = "joy_left"; + linux,code = <KEY_LEFT>; + gpios = <&gpio LPC_GPIO(4,9) GPIO_ACTIVE_LOW>; + }; + + button at 2 { + label = "joy_up"; + linux,code = <KEY_UP>; + gpios = <&gpio LPC_GPIO(4,10) GPIO_ACTIVE_LOW>; + }; + + button at 3 { + label = "joy_right"; + linux,code = <KEY_RIGHT>; + gpios = <&gpio LPC_GPIO(4,12) GPIO_ACTIVE_LOW>; + }; + + button at 4 { + label = "joy_down"; + linux,code = <KEY_DOWN>; + gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>; + }; + }; }; &pinctrl { + gpio_joystick_pins: gpio-joystick-pins { + gpio_joystick_cfg { + pins = "p9_0", "p9_1", "pa_1", "pa_2", "pa_3"; + function = "gpio"; + input-enable; + bias-disable; + }; + }; + sdmmc_pins: sdmmc-pins { sdmmc_clk_cfg { pins = "pc_0";
Signature · 1 line
1.8.0
PATCH 14/17 ARM: dts: lpc4357-ea4357: add ethernet
In reply to Joachim EastwoodEnable Ethernet and add pin muxing and set the correct frequency on the enet tx clock input.
Signed-off-by Joachim Eastwood <[email protected]>
--- arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 73 +++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+)
arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +73 -0
@@ -88,6 +88,68 @@ }; &pinctrl { + enet_rmii_pins: enet-rmii-pins { + enet_rmii_rxd_cfg { + pins = "p1_15", "p0_0"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_txd_cfg { + pins = "p1_18", "p1_20"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_rx_dv_cfg { + pins = "p1_16"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_tx_en_cfg { + pins = "p0_1"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_ref_clk_cfg { + pins = "p1_19"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_mdio_cfg { + pins = "p1_17"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_mdc_cfg { + pins = "pc_1"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + }; + gpio_joystick_pins: gpio-joystick-pins { gpio_joystick_cfg { pins = "p9_0", "p9_1", "pa_1", "pa_2", "pa_3";
@@ -145,6 +207,17 @@ }; }; +&enet_tx_clk { + clock-frequency = <50000000>; +}; + +&mac { + status = "okay"; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&enet_rmii_pins>; +}; + &mmcsd { status = "okay"; bus-width = <4>;
Signature · 1 line
1.8.0
PATCH 15/17 ARM: dts: lpc4357-ea4357: add uart3
In reply to Joachim EastwoodEnable UART3 that is routed to the J17 DSUB9 connector on the EA4357 devkit.
Signed-off-by Joachim Eastwood <[email protected]>
--- arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +22 -0
@@ -205,6 +205,22 @@ bias-pull-down; }; }; + + uart3_pins: uart3-pins { + uart3_rx_cfg { + pins = "p2_4"; + function = "uart3"; + input-schmitt-disable; + bias-disable; + input-enable; + }; + + uart3_tx_cfg { + pins = "p9_3"; + function = "uart3"; + bias-pull-down; + }; + }; }; &enet_tx_clk {
@@ -231,3 +247,9 @@ pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; }; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +};
Signature · 1 line
1.8.0
PATCH 16/17 of: add vendor prefix for CIAA project
In reply to Joachim EastwoodFrom: Ezequiel Garcia <[email protected]>
CIAA stands for Argentine Open Industrial Computer. The CIAA project is an initiative sponsored by universities and private companies. Its main goal is to promote local embedded systems development.
Among other devices, the project developed a NXP LPC4337-based reference design.
Signed-off-by Ezequiel Garcia <[email protected]>
Signed-off-by Joachim Eastwood <[email protected]>
--- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/vendor-prefixes.txt +1 -0
@@ -46,6 +46,7 @@ chipone ChipOne chipspark ChipSPARK chrp Common Hardware Reference Platform chunghwa Chunghwa Picture Tubes Ltd. +ciaa Computadora Industrial Abierta Argentina cirrus Cirrus Logic, Inc. cloudengines Cloud Engines, Inc. cnm Chips&Media, Inc.
Signature · 1 line
1.8.0
PATCH 17/17 ARM: dts: add DT for CIAA LPC4337 industrial computer
In reply to Joachim EastwoodFrom: Ezequiel Garcia <[email protected]>
Add basic support for CIAA (Argentine Open Industrial Computer) LPC4337 board. This commit enables the following peripherals:
* UART
* SSP
* Ethernet
Signed-off-by Ezequiel Garcia <[email protected]>
Signed-off-by Joachim Eastwood <[email protected]>
--- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/lpc4337-ciaa.dts | 187 +++++++++++++++++++++++++++++++++++++ 2 files changed, 188 insertions(+) create mode 100644 arch/arm/boot/dts/lpc4337-ciaa.dts
arch/arm/boot/dts/Makefile +1 -0
@@ -211,6 +211,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-ts419-6281.dtb \ kirkwood-ts419-6282.dtb dtb-$(CONFIG_ARCH_LPC18XX) += \ + lpc4337-ciaa.dtb \ lpc4350-hitex-eval.dtb \ lpc4357-ea4357-devkit.dtb dtb-$(CONFIG_ARCH_LPC32XX) += \
arch/arm/boot/dts/lpc4337-ciaa.dts new file +187 -0
187 lines not on this page · raw message
Signature · 1 line
1.8.0
cover LPC18xx DTS changes for 4.3
In reply to Joachim EastwoodHi Joachim,
Quoted 6 lines · Joachim Eastwood
This patch set adds DT nodes for all the drivers that went upstream in 4.2 and should represent the bulk of DTS changes for 4.3. All nodes added are documented and some of patches carries a ack from subsystem maintainer. It also features updates to the EA4357 dev- kit and a new board from Ezequiel Garcia.
Quoted 6 lines
Note that there might be one more batch of DTS changes for 4.3 if any new drivers goes upstream and also some changes for the Hitex eval board might come.
Patches also available on:
https://github.com/manabian/linux-lpc.git lpc18xx_43xx_dts_4.3
The patchset looks good. I've merged the branch with the description above.
In the future, please feel free to start using a signed tag even if your key might not be signed by others yet, and over time collect signatures from other developers. That way we get the merge description automatically when we pull the tag.
Thanks,
-Olof