ARM: sunxi: Switch to clock indices

PATCH Superseded Maxime Ripard 3 participants 14 messages Jul 26, 2015 – Jul 30, 2015

Subsystems (4)

Device tree bindings Common clk Arm/Allwinner sunXi SoC support Arm/Allwinner SoC Clock Support

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Maxime Ripard

author

2015-07-26 21:14 UTC #0 lore raw

cover ARM: sunxi: Switch to clock indices

Hi,

We currently have in our clock driver a logic very similar to the one that clock-indices is supposed to cover.

Using this property, we can create a new driver generic for all gates that will get the valid indices directly from the device tree, instead of storing that in the driver itself.

While we're at it, we also move to using CLK_OF_DECLARE for that new driver, which should ease the orphan clocks breakage we saw.

Let me know what you think,
Maxime

Maxime Ripard (7):
ARM: sun4i: Add clock indices
ARM: sun5i: Add clock indices
ARM: sun6i: Add clock indices
ARM: sun7i: Add clock indices
ARM: sun8i: Add clock indices
ARM: sun9i: Add clock indices
clk: sunxi: Add a simple gates driver

 arch/arm/boot/dts/sun4i-a10.dtsi     |  69 ++++++++++----
 arch/arm/boot/dts/sun5i-a10s.dtsi    |  23 ++++-
 arch/arm/boot/dts/sun5i-a13.dtsi     |  18 +++-
 arch/arm/boot/dts/sun5i.dtsi         |   1 +
 arch/arm/boot/dts/sun6i-a31.dtsi     |  24 +++++
 arch/arm/boot/dts/sun7i-a20.dtsi     |  23 +++++
 arch/arm/boot/dts/sun8i-a23-a33.dtsi |  15 +++
 arch/arm/boot/dts/sun9i-a80.dtsi     |  32 +++++--
 drivers/clk/sunxi/Makefile           |   1 +
 drivers/clk/sunxi/clk-simple-gates.c | 159 +++++++++++++++++++++++++++++++
 drivers/clk/sunxi/clk-sunxi.c        | 177 -----------------------------------
 11 files changed, 335 insertions(+), 207 deletions(-)
 create mode 100644 drivers/clk/sunxi/clk-simple-gates.c

Signature · 1 line

2.4.6

Maxime Ripard

author

2015-07-26 21:14 UTC #1 lore raw

PATCH 1/7 ARM: sun4i: Add clock indices

The A10 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun4i-a10.dtsi | 69 ++++++++++++++++++++++++++++++----------
 1 file changed, 52 insertions(+), 17 deletions(-)

arch/arm/boot/dts/sun4i-a10.dtsi +52 ~~-17~~

index 61c03d1fe530..ab0e131587bb 100644
@@ -241,6 +241,7 @@
 			compatible = "allwinner,sun4i-a10-axi-gates-clk";
 			reg = <0x01c2005c 0x4>;
 			clocks = <&axi>;
+			clock-indices = <0>;
 			clock-output-names = "axi_dram";
 		};

@@ -257,17 +258,36 @@
 			compatible = "allwinner,sun4i-a10-ahb-gates-clk";
 			reg = <0x01c20060 0x8>;
 			clocks = <&ahb>;
+			clock-indices = <0>, <1>,
+					<2>, <3>,
+					<4>, <5>, <6>,
+					<7>, <8>, <9>,
+					<10>, <11>, <12>,
+					<13>, <14>, <16>,
+					<17>, <18>, <20>,
+					<21>, <22>, <23>,
+					<24>, <25>, <26>,
+					<32>, <33>, <34>,
+					<35>, <36>, <37>,
+					<40>, <41>, <43>,
+					<44>, <45>,
+					<46>, <47>,
+					<50>, <52>;
 			clock-output-names = "ahb_usb0", "ahb_ehci0",
-				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
-				"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
-				"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
-				"ahb_sdram", "ahb_ace",	"ahb_emac", "ahb_ts",
-				"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
-				"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
-				"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
-				"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
-				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
-				"ahb_de_fe1", "ahb_mp", "ahb_mali400";
+					     "ahb_ohci0", "ahb_ehci1",
+					     "ahb_ohci1", "ahb_ss", "ahb_dma",
+					     "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+					     "ahb_mmc2", "ahb_mmc3", "ahb_ms",
+					     "ahb_nand", "ahb_sdram", "ahb_ace",
+					     "ahb_emac", "ahb_ts", "ahb_spi0",
+					     "ahb_spi1", "ahb_spi2", "ahb_spi3",
+					     "ahb_pata", "ahb_sata", "ahb_gps",
+					     "ahb_ve", "ahb_tvd", "ahb_tve0",
+					     "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
+					     "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+					     "ahb_de_be0", "ahb_de_be1",
+					     "ahb_de_fe0", "ahb_de_fe1",
+					     "ahb_mp", "ahb_mali400";
 		};
 
 		apb0: apb0 at 01c20054 {

@@ -283,9 +303,14 @@
 			compatible = "allwinner,sun4i-a10-apb0-gates-clk";
 			reg = <0x01c20068 0x4>;
 			clocks = <&apb0>;
+			clock-indices = <0>, <1>,
+					<2>, <3>,
+					<5>, <6>,
+					<7>, <10>;
 			clock-output-names = "apb0_codec", "apb0_spdif",
-				"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
-				"apb0_ir1", "apb0_keypad";
+					     "apb0_ac97", "apb0_iis",
+					     "apb0_pio", "apb0_ir0",
+					     "apb0_ir1", "apb0_keypad";
 		};
 
 		apb1: clk at 01c20058 {

@@ -301,12 +326,22 @@
 			compatible = "allwinner,sun4i-a10-apb1-gates-clk";
 			reg = <0x01c2006c 0x4>;
 			clocks = <&apb1>;
+			clock-indices = <0>, <1>,
+					<2>, <4>,
+					<5>, <6>,
+					<7>, <16>,
+					<17>, <18>,
+					<19>, <20>,
+					<21>, <22>,
+					<23>;
 			clock-output-names = "apb1_i2c0", "apb1_i2c1",
-				"apb1_i2c2", "apb1_can", "apb1_scr",
-				"apb1_ps20", "apb1_ps21", "apb1_uart0",
-				"apb1_uart1", "apb1_uart2", "apb1_uart3",
-				"apb1_uart4", "apb1_uart5", "apb1_uart6",
-				"apb1_uart7";
+					     "apb1_i2c2", "apb1_can",
+					     "apb1_scr", "apb1_ps20",
+					     "apb1_ps21", "apb1_uart0",
+					     "apb1_uart1", "apb1_uart2",
+					     "apb1_uart3", "apb1_uart4",
+					     "apb1_uart5", "apb1_uart6",
+					     "apb1_uart7";
 		};
 
 		nand_clk: clk at 01c20080 {

Signature · 1 line

2.4.6

Maxime Ripard

author

2015-07-26 21:14 UTC #2 lore raw

PATCH 2/7 ARM: sun5i: Add clock indices

In reply to Maxime Ripard

The A10s and A13 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun5i-a10s.dtsi | 23 +++++++++++++++++++++--
 arch/arm/boot/dts/sun5i-a13.dtsi  | 18 +++++++++++++++++-
 arch/arm/boot/dts/sun5i.dtsi      |  1 +
 3 files changed, 39 insertions(+), 3 deletions(-)

arch/arm/boot/dts/sun5i-a10s.dtsi +21 -2

index f11efb722bbb..a513b416a807 100644
@@ -85,6 +85,17 @@
 			compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
 			reg = <0x01c20060 0x8>;
 			clocks = <&ahb>;
+			clock-indices = <0>, <1>,
+					<2>, <5>, <6>,
+					<7>, <8>, <9>,
+					<10>, <13>,
+					<14>, <17>, <18>,
+					<20>, <21>, <22>,
+					<26>, <28>, <32>,
+					<34>, <36>, <40>,
+					<43>, <44>,
+					<46>, <51>,
+					<52>;
 			clock-output-names = "ahb_usbotg", "ahb_ehci",
 					     "ahb_ohci", "ahb_ss", "ahb_dma",
 					     "ahb_bist", "ahb_mmc0", "ahb_mmc1",

@@ -103,6 +114,9 @@
 			compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
 			reg = <0x01c20068 0x4>;
 			clocks = <&apb0>;
+			clock-indices = <0>, <3>,
+					<5>, <6>,
+					<10>;
 			clock-output-names = "apb0_codec", "apb0_iis",
 					     "apb0_pio", "apb0_ir",
 					     "apb0_keypad";

@@ -113,9 +127,14 @@
 			compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
 			reg = <0x01c2006c 0x4>;
 			clocks = <&apb1>;
+			clock-indices = <0>, <1>,
+					<2>, <16>,
+					<17>, <18>,
+					<19>;
 			clock-output-names = "apb1_i2c0", "apb1_i2c1",
-				"apb1_i2c2", "apb1_uart0", "apb1_uart1",
-				"apb1_uart2", "apb1_uart3";
+					     "apb1_i2c2", "apb1_uart0",
+					     "apb1_uart1", "apb1_uart2",
+					     "apb1_uart3";
 		};
 	};

arch/arm/boot/dts/sun5i-a13.dtsi +17 -1

index 976d4faa2179..f3631c9c6fa2 100644
@@ -104,6 +104,16 @@
 			compatible = "allwinner,sun5i-a13-ahb-gates-clk";
 			reg = <0x01c20060 0x8>;
 			clocks = <&ahb>;
+			clock-indices = <0>, <1>,
+					<2>, <5>, <6>,
+					<7>, <8>, <9>,
+					<10>, <13>,
+					<14>, <20>,
+					<21>, <22>,
+				        <28>, <32>, <36>,
+				        <40>, <44>,
+					<46>, <51>,
+					<52>;
 			clock-output-names = "ahb_usbotg", "ahb_ehci",
 					     "ahb_ohci", "ahb_ss", "ahb_dma",
 					     "ahb_bist", "ahb_mmc0", "ahb_mmc1",

@@ -121,6 +131,8 @@
 			compatible = "allwinner,sun5i-a13-apb0-gates-clk";
 			reg = <0x01c20068 0x4>;
 			clocks = <&apb0>;
+			clock-indices = <0>, <5>,
+					<6>;
 			clock-output-names = "apb0_codec", "apb0_pio",
 					     "apb0_ir";
 		};

@@ -130,8 +142,12 @@
 			compatible = "allwinner,sun5i-a13-apb1-gates-clk";
 			reg = <0x01c2006c 0x4>;
 			clocks = <&apb1>;
+			clock-indices = <0>, <1>,
+					<2>, <17>,
+					<19>;
 			clock-output-names = "apb1_i2c0", "apb1_i2c1",
-				"apb1_i2c2", "apb1_uart1", "apb1_uart3";
+					     "apb1_i2c2", "apb1_uart1",
+					     "apb1_uart3";
 		};
 	};
 };

arch/arm/boot/dts/sun5i.dtsi +1 -0

index 54b097830434..427c0e7289fa 100644
@@ -178,6 +178,7 @@
 			compatible = "allwinner,sun4i-a10-axi-gates-clk";
 			reg = <0x01c2005c 0x4>;
 			clocks = <&axi>;
+			clock-indices = <0>;
 			clock-output-names = "axi_dram";
 		};

Signature · 1 line

2.4.6

Maxime Ripard

author

2015-07-26 21:14 UTC #3 lore raw

PATCH 3/7 ARM: sun6i: Add clock indices

In reply to Maxime Ripard

The A31 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun6i-a31.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

arch/arm/boot/dts/sun6i-a31.dtsi +24 -0

index 008047a018cf..3ec456fa03a4 100644
@@ -252,6 +252,20 @@
 			compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
 			reg = <0x01c20060 0x8>;
 			clocks = <&ahb1>;
+			clock-indices = <1>, <5>,
+					<6>, <8>, <9>,
+					<10>, <11>, <12>,
+					<13>, <14>,
+					<17>, <18>, <19>,
+					<20>, <21>, <22>,
+					<23>, <24>, <26>,
+					<27>, <29>,
+					<30>, <31>, <32>,
+					<36>, <37>, <40>,
+					<43>, <44>, <45>,
+					<46>, <47>, <50>,
+					<52>, <55>, <56>,
+					<57>, <58>;
 			clock-output-names = "ahb1_mipidsi", "ahb1_ss",
 					"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
 					"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",

@@ -281,6 +295,9 @@
 			compatible = "allwinner,sun6i-a31-apb1-gates-clk";
 			reg = <0x01c20068 0x4>;
 			clocks = <&apb1>;
+			clock-indices = <0>, <4>,
+					<5>, <12>,
+					<13>;
 			clock-output-names = "apb1_codec", "apb1_digital_mic",
 					"apb1_pio", "apb1_daudio0",
 					"apb1_daudio1";

@@ -299,6 +316,10 @@
 			compatible = "allwinner,sun6i-a31-apb2-gates-clk";
 			reg = <0x01c2006c 0x4>;
 			clocks = <&apb2>;
+			clock-indices = <0>, <1>,
+					<2>, <3>, <16>,
+					<17>, <18>, <19>,
+					<20>, <21>;
 			clock-output-names = "apb2_i2c0", "apb2_i2c1",
 					     "apb2_i2c2", "apb2_i2c3",
 					     "apb2_uart0", "apb2_uart1",

@@ -384,6 +405,9 @@
 			compatible = "allwinner,sun6i-a31-usb-clk";
 			reg = <0x01c200cc 0x4>;
 			clocks = <&osc24M>;
+			clock-indices = <8>, <9>, <10>,
+					<16>, <17>,
+					<18>;
 			clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
 					     "usb_ohci0", "usb_ohci1",
 					     "usb_ohci2";

Signature · 1 line

2.4.6

Maxime Ripard

author

2015-07-26 21:14 UTC #4 lore raw

PATCH 4/7 ARM: sun7i: Add clock indices

In reply to Maxime Ripard

The A20 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun7i-a20.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

arch/arm/boot/dts/sun7i-a20.dtsi +23 -0

index 6a63f30c9a69..ca0b01a96c52 100644
@@ -267,6 +267,19 @@
 			compatible = "allwinner,sun7i-a20-ahb-gates-clk";
 			reg = <0x01c20060 0x8>;
 			clocks = <&ahb>;
+			clock-indices = <0>, <1>,
+					<2>, <3>, <4>,
+					<5>, <6>, <7>, <8>,
+					<9>, <10>, <11>, <12>,
+					<13>, <14>, <16>,
+					<17>, <18>, <20>, <21>,
+					<22>, <23>, <25>,
+					<28>, <32>, <33>, <34>,
+					<35>, <36>, <37>, <40>,
+					<41>, <42>, <43>,
+					<44>, <45>, <46>,
+					<47>, <49>, <50>,
+					<52>;
 			clock-output-names = "ahb_usb0", "ahb_ehci0",
 				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
 				"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",

@@ -295,6 +308,10 @@
 			compatible = "allwinner,sun7i-a20-apb0-gates-clk";
 			reg = <0x01c20068 0x4>;
 			clocks = <&apb0>;
+			clock-indices = <0>, <1>,
+					<2>, <3>, <4>,
+					<5>, <6>, <7>,
+					<8>, <10>;
 			clock-output-names = "apb0_codec", "apb0_spdif",
 				"apb0_ac97", "apb0_iis0", "apb0_iis1",
 				"apb0_pio", "apb0_ir0", "apb0_ir1",

@@ -314,6 +331,12 @@
 			compatible = "allwinner,sun7i-a20-apb1-gates-clk";
 			reg = <0x01c2006c 0x4>;
 			clocks = <&apb1>;
+			clock-indices = <0>, <1>,
+					<2>, <3>, <4>,
+					<5>, <6>, <7>,
+					<15>, <16>, <17>,
+					<18>, <19>, <20>,
+					<21>, <22>, <23>;
 			clock-output-names = "apb1_i2c0", "apb1_i2c1",
 				"apb1_i2c2", "apb1_i2c3", "apb1_can",
 				"apb1_scr", "apb1_ps20", "apb1_ps21",

Signature · 1 line

2.4.6

Maxime Ripard

author

2015-07-26 21:14 UTC #5 lore raw

PATCH 5/7 ARM: sun8i: Add clock indices

In reply to Maxime Ripard

The A23 and A33 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

arch/arm/boot/dts/sun8i-a23-a33.dtsi +15 -0

index 7abd0ae3143d..c318c770b6c1 100644
@@ -180,6 +180,15 @@
 			compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
 			reg = <0x01c20060 0x8>;
 			clocks = <&ahb1>;
+			clock-indices = <1>, <6>,
+					<8>, <9>, <10>,
+					<13>, <14>,
+					<19>, <20>,
+					<21>, <24>, <26>,
+					<29>, <32>, <36>,
+					<40>, <44>, <46>,
+					<52>, <54>,
+					<57>;
 			clock-output-names = "ahb1_mipidsi", "ahb1_dma",
 					"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
 					"ahb1_nand", "ahb1_sdram",

@@ -196,6 +205,8 @@
 			compatible = "allwinner,sun8i-a23-apb1-gates-clk";
 			reg = <0x01c20068 0x4>;
 			clocks = <&apb1>;
+			clock-indices = <0>, <5>,
+					<12>, <13>;
 			clock-output-names = "apb1_codec", "apb1_pio",
 					"apb1_daudio0",	"apb1_daudio1";
 		};

@@ -213,6 +224,10 @@
 			compatible = "allwinner,sun8i-a23-apb2-gates-clk";
 			reg = <0x01c2006c 0x4>;
 			clocks = <&apb2>;
+			clock-indices = <0>, <1>,
+					<2>, <16>,
+					<17>, <18>,
+					<19>, <20>;
 			clock-output-names = "apb2_i2c0", "apb2_i2c1",
 					"apb2_i2c2", "apb2_uart0",
 					"apb2_uart1", "apb2_uart2",

Signature · 1 line

2.4.6

Maxime Ripard

author

2015-07-26 21:14 UTC #6 lore raw

PATCH 6/7 ARM: sun9i: Add clock indices

In reply to Maxime Ripard

The A80 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun9i-a80.dtsi | 32 ++++++++++++++++++++++----------
 1 file changed, 22 insertions(+), 10 deletions(-)

arch/arm/boot/dts/sun9i-a80.dtsi +22 ~~-10~~

index a43ad779ee2f..5908e3dcf965 100644
@@ -277,9 +277,12 @@
 			compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
 			reg = <0x06000580 0x4>;
 			clocks = <&ahb0>;
-			clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
-					<14>, <15>, <16>, <18>, <20>, <21>,
-					<22>, <23>;
+			clock-indices = <0>, <1>, <3>,
+					<5>, <8>, <12>,
+					<13>, <14>,
+					<15>, <16>, <18>,
+					<20>, <21>, <22>,
+					<23>;
 			clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
 					"ahb0_ss", "ahb0_sd", "ahb0_nand1",
 					"ahb0_nand0", "ahb0_sdram",

@@ -293,7 +296,10 @@
 			compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
 			reg = <0x06000584 0x4>;
 			clocks = <&ahb1>;
-			clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
+			clock-indices = <0>, <1>,
+					<17>, <21>,
+					<22>, <23>,
+					<24>;
 			clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
 					"ahb1_gmac", "ahb1_msgbox",
 					"ahb1_spinlock", "ahb1_hstimer",

@@ -305,8 +311,9 @@
 			compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
 			reg = <0x06000588 0x4>;
 			clocks = <&ahb2>;
-			clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
-					<11>;
+			clock-indices = <0>, <1>,
+					<2>, <4>, <5>,
+					<7>, <8>, <11>;
 			clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
 					"ahb2_edp", "ahb2_csi", "ahb2_hdmi",
 					"ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";

@@ -317,8 +324,10 @@
 			compatible = "allwinner,sun9i-a80-apb0-gates-clk";
 			reg = <0x06000590 0x4>;
 			clocks = <&apb0>;
-			clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
-					<17>, <18>, <19>;
+			clock-indices = <1>, <5>,
+					<11>, <12>, <13>,
+					<15>, <17>, <18>,
+					<19>;
 			clock-output-names = "apb0_spdif", "apb0_pio",
 					"apb0_ac97", "apb0_i2s0", "apb0_i2s1",
 					"apb0_lradc", "apb0_gpadc", "apb0_twd",

@@ -330,8 +339,11 @@
 			compatible = "allwinner,sun9i-a80-apb1-gates-clk";
 			reg = <0x06000594 0x4>;
 			clocks = <&apb1>;
-			clock-indices = <0>, <1>, <2>, <3>, <4>,
-					<16>, <17>, <18>, <19>, <20>, <21>;
+			clock-indices = <0>, <1>,
+					<2>, <3>, <4>,
+					<16>, <17>,
+					<18>, <19>,
+					<20>, <21>;
 			clock-output-names = "apb1_i2c0", "apb1_i2c1",
 					"apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
 					"apb1_uart0", "apb1_uart1",

Signature · 1 line

2.4.6

Chen-Yu Tsai

2015-07-30 07:44 UTC #7 lore raw

PATCH 6/7 ARM: sun9i: Add clock indices

Quoted 2 lines · Maxime Ripard

The A80 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this.

The commit message does not match the patch, which is just a reformatting of existing clock-indices properties.

Quoted 79 lines

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun9i-a80.dtsi | 32 ++++++++++++++++++++++----------
 1 file changed, 22 insertions(+), 10 deletions(-)

arch/arm/boot/dts/sun9i-a80.dtsi +22 ~~-11~~

index a43ad779ee2f..5908e3dcf965 100644
@@ -277,9 +277,12 @@
                        compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
                        reg = <0x06000580 0x4>;
                        clocks = <&ahb0>;
-                       clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
-                                       <14>, <15>, <16>, <18>, <20>, <21>,
-                                       <22>, <23>;
+                       clock-indices = <0>, <1>, <3>,
+                                       <5>, <8>, <12>,
+                                       <13>, <14>,
+                                       <15>, <16>, <18>,
+                                       <20>, <21>, <22>,
+                                       <23>;
                        clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
                                        "ahb0_ss", "ahb0_sd", "ahb0_nand1",
                                        "ahb0_nand0", "ahb0_sdram",

@@ -293,7 +296,10 @@
                        compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
                        reg = <0x06000584 0x4>;
                        clocks = <&ahb1>;
-                       clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
+                       clock-indices = <0>, <1>,
+                                       <17>, <21>,
+                                       <22>, <23>,
+                                       <24>;
                        clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
                                        "ahb1_gmac", "ahb1_msgbox",
                                        "ahb1_spinlock", "ahb1_hstimer",

@@ -305,8 +311,9 @@
                        compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
                        reg = <0x06000588 0x4>;
                        clocks = <&ahb2>;
-                       clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
-                                       <11>;
+                       clock-indices = <0>, <1>,
+                                       <2>, <4>, <5>,
+                                       <7>, <8>, <11>;
                        clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
                                        "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
                                        "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";

@@ -317,8 +324,10 @@
                        compatible = "allwinner,sun9i-a80-apb0-gates-clk";
                        reg = <0x06000590 0x4>;
                        clocks = <&apb0>;
-                       clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
-                                       <17>, <18>, <19>;
+                       clock-indices = <1>, <5>,
+                                       <11>, <12>, <13>,
+                                       <15>, <17>, <18>,
+                                       <19>;
                        clock-output-names = "apb0_spdif", "apb0_pio",
                                        "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
                                        "apb0_lradc", "apb0_gpadc", "apb0_twd",

@@ -330,8 +339,11 @@
                        compatible = "allwinner,sun9i-a80-apb1-gates-clk";
                        reg = <0x06000594 0x4>;
                        clocks = <&apb1>;
-                       clock-indices = <0>, <1>, <2>, <3>, <4>,
-                                       <16>, <17>, <18>, <19>, <20>, <21>;
+                       clock-indices = <0>, <1>,
+                                       <2>, <3>, <4>,
+                                       <16>, <17>,
+                                       <18>, <19>,
+                                       <20>, <21>;
                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
                                        "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
                                        "apb1_uart0", "apb1_uart1",
--

2.4.6

Maxime Ripard

author

2015-07-30 10:12 UTC #8 lore raw

PATCH 6/7 ARM: sun9i: Add clock indices

Quoted 7 lines · Chen-Yu Tsai

Quoted 2 lines · Maxime Ripard
The A80 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this.
The commit message does not match the patch, which is just a reformatting of existing clock-indices properties.

Indeed... That's what happens when you automate too much things.. :)

Thanks!
Maxime

Signature · 10 lines

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Maxime Ripard

author

2015-07-26 21:14 UTC #9 lore raw

PATCH 7/7 clk: sunxi: Add a simple gates driver

In reply to Maxime Ripard

The gates were handled with a common piece of framework that was registering all gates array, that was not using the CLK_OF_DECLARE logic, and was not using clock-indices but some private masks that were pretty much equivalent.

Move this code in a new driver that handles all the gates array and solves both these issues.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/clk/sunxi/Makefile           |   1 +
 drivers/clk/sunxi/clk-simple-gates.c | 159 +++++++++++++++++++++++++++++++
 drivers/clk/sunxi/clk-sunxi.c        | 177 -----------------------------------
 3 files changed, 160 insertions(+), 177 deletions(-)
 create mode 100644 drivers/clk/sunxi/clk-simple-gates.c

drivers/clk/sunxi/Makefile +1 -0

index 058f273d6154..f5a35b82cc1a 100644
@@ -6,6 +6,7 @@ obj-y += clk-sunxi.o clk-factors.o
 obj-y += clk-a10-hosc.o
 obj-y += clk-a20-gmac.o
 obj-y += clk-mod0.o
+obj-y += clk-simple-gates.o
 obj-y += clk-sun8i-mbus.o
 obj-y += clk-sun9i-core.o
 obj-y += clk-sun9i-mmc.o

drivers/clk/sunxi/clk-simple-gates.c new file +159 -0

159 lines not on this page · raw message

drivers/clk/sunxi/clk-sunxi.c +0 ~~-177~~

207 lines not on this page · raw message

Signature · 1 line

2.4.6

Stephen Boyd

2015-07-27 20:26 UTC #10 lore raw

PATCH 7/7 clk: sunxi: Add a simple gates driver

Quoted 14 lines · Maxime Ripard

drivers/clk/sunxi/clk-simple-gates.c new file +8 -0

new file mode 100644
index 000000000000..1a3963a8a686
@@ -0,0 +1,159 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or

drivers/clk/sunxi/clk-simple-gates.c line 18

Quoted 10 lines

drivers/clk/sunxi/clk-simple-gates.c new file +10 -0

+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>

Is this used?

drivers/clk/sunxi/clk-simple-gates.c line 21

Quoted 3 lines

drivers/clk/sunxi/clk-simple-gates.c new file +3 -0
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/reset-controller.h>

Is this used?

drivers/clk/sunxi/clk-simple-gates.c line 23

Quoted 2 lines

drivers/clk/sunxi/clk-simple-gates.c new file +2 -0
+#include <linux/spinlock.h>
+#include <linux/log2.h>

Is this used?

Quoted 3 lines

drivers/clk/sunxi/clk-simple-gates.c new file +3 -0
+
+static DEFINE_SPINLOCK(gates_lock);
+

[...]

drivers/clk/sunxi/clk-simple-gates.c

Quoted 2 lines

drivers/clk/sunxi/clk-simple-gates.c new file +2 -0
+
+static const int sun4i_a10_ahb_critical_clocks[] __initdata = {

Shouldn't it be __initconst ?

Quoted 3 lines

drivers/clk/sunxi/clk-simple-gates.c new file +3 -0
+	14,	/* ahb_sdram */
+};
+

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Chen-Yu Tsai

2015-07-30 07:55 UTC #11 lore raw

PATCH 7/7 clk: sunxi: Add a simple gates driver

Quoted 15 lines · Stephen Boyd

Quoted 14 lines · Maxime Ripard

drivers/clk/sunxi/clk-simple-gates.c new file +8 -0

new file mode 100644
index 000000000000..1a3963a8a686
@@ -0,0 +1,159 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or

Quoted 8 lines

drivers/clk/sunxi/clk-simple-gates.c line 16

Quoted 8 lines

drivers/clk/sunxi/clk-simple-gates.c new file +8 -0

+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+

I'm guessing the following were copied from clk-sunxi.c.

Quoted 4 lines

drivers/clk/sunxi/clk-simple-gates.c line 18
Quoted 2 lines
drivers/clk/sunxi/clk-simple-gates.c new file +2 -0
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
Is this used?

clk_register_clkdev() is not used in this file, so not needed.

Quoted 5 lines

drivers/clk/sunxi/clk-simple-gates.c line 21
Quoted 3 lines
drivers/clk/sunxi/clk-simple-gates.c new file +3 -0
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/reset-controller.h>
Is this used?

A remnant of the USB clocks, which has been moved to clk-usb.c.

Not needed here nor in clk-sunxi.c.

Quoted 4 lines

drivers/clk/sunxi/clk-simple-gates.c line 23
Quoted 2 lines
drivers/clk/sunxi/clk-simple-gates.c new file +2 -0
+#include <linux/spinlock.h>
+#include <linux/log2.h>
Is this used?

This is only used for clock factor calculation. Not applicable in clk-simple-gates.c, so no.

Quoted 8 lines

Quoted 3 lines
drivers/clk/sunxi/clk-simple-gates.c new file +3 -0
+
+static DEFINE_SPINLOCK(gates_lock);
+
[...]
drivers/clk/sunxi/clk-simple-gates.c
Quoted 2 lines
drivers/clk/sunxi/clk-simple-gates.c new file +2 -0
+
+static const int sun4i_a10_ahb_critical_clocks[] __initdata = {
Shouldn't it be __initconst ?

Not sure why our critical clocks lists are __initdata...

Quoted 10 lines

drivers/clk/sunxi/clk-simple-gates.c line 146
Quoted 3 lines
drivers/clk/sunxi/clk-simple-gates.c new file +3 -0
+     14,     /* ahb_sdram */
+};
+
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo at vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html

Maxime Ripard

author

2015-07-30 10:17 UTC #12 lore raw

PATCH 7/7 clk: sunxi: Add a simple gates driver

Quoted 44 lines · Chen-Yu Tsai

Quoted 15 lines · Stephen Boyd
Quoted 14 lines · Maxime Ripard
drivers/clk/sunxi/clk-simple-gates.c new file +8 -0
new file mode 100644
index 000000000000..1a3963a8a686
@@ -0,0 +1,159 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
Quoted 8 lines
drivers/clk/sunxi/clk-simple-gates.c line 16
Quoted 8 lines
drivers/clk/sunxi/clk-simple-gates.c new file +8 -0
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
I'm guessing the following were copied from clk-sunxi.c.
Quoted 4 lines
drivers/clk/sunxi/clk-simple-gates.c line 18
Quoted 2 lines
drivers/clk/sunxi/clk-simple-gates.c new file +2 -0
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
Is this used?
clk_register_clkdev() is not used in this file, so not needed.
Quoted 5 lines
drivers/clk/sunxi/clk-simple-gates.c line 21
Quoted 3 lines
drivers/clk/sunxi/clk-simple-gates.c new file +3 -0
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/reset-controller.h>
Is this used?
A remnant of the USB clocks, which has been moved to clk-usb.c.
Not needed here nor in clk-sunxi.c.

Quoted 7 lines

Quoted 4 lines
drivers/clk/sunxi/clk-simple-gates.c line 23
Quoted 2 lines
drivers/clk/sunxi/clk-simple-gates.c new file +2 -0
+#include <linux/spinlock.h>
+#include <linux/log2.h>
Is this used?
This is only used for clock factor calculation. Not applicable in clk-simple-gates.c, so no.

You're right, we don't need any of these...

Quoted 9 lines

Quoted 7 lines
Quoted 2 lines
drivers/clk/sunxi/clk-simple-gates.c new file +2 -0
+static DEFINE_SPINLOCK(gates_lock);
+
[...]
drivers/clk/sunxi/clk-simple-gates.c
Quoted 2 lines
drivers/clk/sunxi/clk-simple-gates.c new file +2 -0
+
+static const int sun4i_a10_ahb_critical_clocks[] __initdata = {
Shouldn't it be __initconst ?
Not sure why our critical clocks lists are __initdata...

Why shouldn't it be?

CLK_OF_DECLARE callbacks only run at of_clk_init time, which is way before the init memory is discarded.

Maxime

Signature · 10 lines

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Chen-Yu Tsai

2015-07-30 14:34 UTC #13 lore raw

PATCH 7/7 clk: sunxi: Add a simple gates driver

Quoted 63 lines · Maxime Ripard

Quoted 44 lines · Chen-Yu Tsai
Quoted 15 lines · Stephen Boyd
Quoted 14 lines · Maxime Ripard
drivers/clk/sunxi/clk-simple-gates.c new file +8 -0
new file mode 100644
index 000000000000..1a3963a8a686
@@ -0,0 +1,159 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
Quoted 8 lines
drivers/clk/sunxi/clk-simple-gates.c line 16
Quoted 8 lines
drivers/clk/sunxi/clk-simple-gates.c new file +8 -0
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
I'm guessing the following were copied from clk-sunxi.c.
Quoted 4 lines
drivers/clk/sunxi/clk-simple-gates.c line 18
Quoted 2 lines
drivers/clk/sunxi/clk-simple-gates.c new file +2 -0
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
Is this used?
clk_register_clkdev() is not used in this file, so not needed.
Quoted 5 lines
drivers/clk/sunxi/clk-simple-gates.c line 21
Quoted 3 lines
drivers/clk/sunxi/clk-simple-gates.c new file +3 -0
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/reset-controller.h>
Is this used?
A remnant of the USB clocks, which has been moved to clk-usb.c.
Not needed here nor in clk-sunxi.c.
Quoted 7 lines
Quoted 4 lines
drivers/clk/sunxi/clk-simple-gates.c line 23
Quoted 2 lines
drivers/clk/sunxi/clk-simple-gates.c new file +2 -0
+#include <linux/spinlock.h>
+#include <linux/log2.h>
Is this used?
This is only used for clock factor calculation. Not applicable in clk-simple-gates.c, so no.
You're right, we don't need any of these...
Quoted 8 lines
Quoted 7 lines
Quoted 2 lines
drivers/clk/sunxi/clk-simple-gates.c new file +2 -0
+static DEFINE_SPINLOCK(gates_lock);
+
[...]
drivers/clk/sunxi/clk-simple-gates.c
Quoted 2 lines
drivers/clk/sunxi/clk-simple-gates.c new file +2 -0
+
+static const int sun4i_a10_ahb_critical_clocks[] __initdata = {
Shouldn't it be __initconst ?

Quoted 6 lines

Quoted 1 line
Not sure why our critical clocks lists are __initdata...
Why shouldn't it be?
CLK_OF_DECLARE callbacks only run at of_clk_init time, which is way before the init memory is discarded.

Sorry, I meant why __initdata and not __initconst.

ChenYu