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sunxi: nand: Basic NAND driver for SPL

PATCH Superseded Piotr Zierhoffer 7 participants 26 messages Jul 23, 2015 – Aug 27, 2015

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#0 lore raw

v3 cover sunxi: nand: Basic NAND driver for SPL

This is a basic driver for the sunxi NAND controller for Allwinner A20. It supports only SPL.

The driver uses DMA for data transfers. It does not support writing.

Changes in v3:
- moved pinmux and clock to board level
- code cleanup with significant size reduction
- renamed the driver file
- renamed constants to match Kconfig convention
- moved defines from .h to .c, and renamed them to be consistent with each other
- removed more magic values
- changed ecc_errors from static to local variable
- other minor changes
- added new options in Kconfig to support different chips
- changed descriptions to comply with patman rules

Changes in v2:
- removed traces of non-SPL-specific code
- moved the driver from boards/sunxi to drivers/mtd/nand
- moved magic values to defines (whenever possible)
- removed unnecesary late initialisation code
- code style changes as suggested for the first patch set:
- changed visibility of some symbols
- renamed unclear variables
- renamed header protector
- changed types of pointer variables
- other minor changes
- removed traces of non-SPL specific code
- renamed defines to be more relevant
- moved Kconfig entry for the driver to drivers/mtd/nand
- reworded Kconfig entry help

Karol Gugala (1):
sunxi: nand: Add pinmux and clock settings for NAND support

Piotr Zierhoffer (3):
sunxi: nand: Add basic sunxi NAND driver for SPL with DMA support
sunxi: nand: Add board configuration options
sunxi: nand: Add information to sunxi that it was run from NAND in SPL

 arch/arm/cpu/armv7/sunxi/board.c              |   4 +
 arch/arm/include/asm/arch-sunxi/clock_sun4i.h |   2 +
 arch/arm/include/asm/arch-sunxi/gpio.h        |   1 +
 board/sunxi/board.c                           |  27 ++
 drivers/mtd/nand/Kconfig                      |  40 +++
 drivers/mtd/nand/Makefile                     |   1 +
 drivers/mtd/nand/sunxi_nand_spl.c             | 353 ++++++++++++++++++++++++++
 include/configs/sunxi-common.h                |  10 +
 8 files changed, 438 insertions(+)
 create mode 100644 drivers/mtd/nand/sunxi_nand_spl.c
Signature · 1 line
2.3.6
#1 lore raw

PATCH v3 1/4 sunxi: nand: Add pinmux and clock settings for NAND support

From: Karol Gugala <[email protected]>

To enable NAND flash in sunxi SPL,
pins 0-6, 8-22 and 24 on port C are configured.

---

Changes in v3:
- moved pinmux and clock to board level
- code cleanup with significant size reduction

Changes in v2: None

 arch/arm/include/asm/arch-sunxi/clock_sun4i.h |  2 ++
 arch/arm/include/asm/arch-sunxi/gpio.h        |  1 +
 board/sunxi/board.c                           | 27 +++++++++++++++++++++++++++
 3 files changed, 30 insertions(+)
arch/arm/include/asm/arch-sunxi/clock_sun4i.h +2 -0
index 58aff16..01d3e28 100644
@@ -267,6 +267,8 @@ struct sunxi_ccm_reg {
 #define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2
 #define CCM_MBUS_CTRL_GATE (0x1 << 31)
 
+#define CCM_NAND_CTRL_ENABLE		(0x1 << 31)
+
 #define CCM_MMC_CTRL_M(x)		((x) - 1)
 #define CCM_MMC_CTRL_OCLK_DLY(x)	((x) << 8)
 #define CCM_MMC_CTRL_N(x)		((x) << 16)
arch/arm/include/asm/arch-sunxi/gpio.h +1 -0
index 8e67b3b..8382101 100644
@@ -158,6 +158,7 @@ enum sunxi_gpio_number {
 #define SUN8I_GPB_UART2		2
 #define SUN8I_A33_GPB_UART0	3
 
+#define SUNXI_GPC_NAND		2
 #define SUNXI_GPC_SDC2		3
 #define SUN6I_GPC_SDC3		4
 
board/sunxi/board.c +27 -0
index ed60e74..096b5c3 100644
@@ -108,6 +108,28 @@ int dram_init(void)
 	return 0;
 }
 
+#if defined(CONFIG_SPL_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
+static void nand_pinmux_setup(void)
+{
+	unsigned int pin;
+	for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(6); pin++)
+		sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
+
+	for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(22); pin++)
+		sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
+
+	sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
+}
+
+static void nand_clock_setup(void)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
+	setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
+}
+#endif
+
 #ifdef CONFIG_GENERIC_MMC
 static void mmc_pinmux_setup(int sdc)
 {
@@ -434,6 +456,11 @@ void sunxi_board_init(void)
 	power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT);
 #endif
 
+#ifdef CONFIG_SPL_NAND_SUNXI
+	nand_pinmux_setup();
+	nand_clock_setup();
+#endif
+
 	printf("DRAM:");
 	ramsize = sunxi_dram_init();
 	printf(" %lu MiB\n", ramsize >> 20);
Signature · 1 line
2.3.6
#2 lore raw

PATCH v3 2/4 sunxi: nand: Add basic sunxi NAND driver for SPL with DMA support

In reply to Piotr Zierhoffer

This driver adds NAND support to SPL.
It was tested on Allwinner A20.

---

Changes in v3:
- renamed the driver file
- renamed constants to match Kconfig convention
- moved defines from .h to .c, and renamed them to be consistent with each other
- removed more magic values
- changed ecc_errors from static to local variable
- other minor changes

Changes in v2:
- removed traces of non-SPL-specific code
- moved the driver from boards/sunxi to drivers/mtd/nand
- moved magic values to defines (whenever possible)
- removed unnecesary late initialisation code
- code style changes as suggested for the first patch set:
- changed visibility of some symbols
- renamed unclear variables
- renamed header protector
- changed types of pointer variables
- other minor changes

 drivers/mtd/nand/Makefile         |   1 +
 drivers/mtd/nand/sunxi_nand_spl.c | 353 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 354 insertions(+)
 create mode 100644 drivers/mtd/nand/sunxi_nand_spl.c
drivers/mtd/nand/Makefile +1 -0
index 347ea62..b40dda8 100644
@@ -12,6 +12,7 @@ NORMAL_DRIVERS=y
 endif
 
 obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
+obj-$(CONFIG_SPL_NAND_SUNXI) += sunxi_nand_spl.o
 obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o
 obj-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o
 obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
drivers/mtd/nand/sunxi_nand_spl.c new file +353 -0

353 lines not on this page · raw message

Signature · 1 line
2.3.6
#3 lore raw

PATCH v3 2/4 sunxi: nand: Add basic sunxi NAND driver for SPL with DMA support

Quoted 18 lines · Piotr Zierhoffer
drivers/mtd/nand/sunxi_nand_spl.c new file +18 -0
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
+{
+     void *current_dest;
+     uint32_t count;
+     uint32_t current_count;
+     uint32_t ecc_errors = 0;
+
+     memset(dest, 0x0, size); /* clean destination memory */
+     for (current_dest = dest;
+                     current_dest < (dest + size);
+                     current_dest += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE) {
+             nand_read_page(offs, offs
+                             < CONFIG_NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END,
+                            &ecc_errors);
+             count = current_dest - dest;
+
+             if (size - count > CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE)
+                     current_count = CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;

drivers/mtd/nand/sunxi_nand_spl.c line 351

Quoted 10 lines
drivers/mtd/nand/sunxi_nand_spl.c new file +10 -0
+             else
+                     current_count = size - count;
+
+             memcpy(current_dest,
+                    temp_buf,
+                    current_count);
+             offs += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
+     }
+     return ecc_errors ? -1 : 0;
+}

No bad block marker handling?

-Scott

#4 lore raw

PATCH v3 2/4 sunxi: nand: Add basic sunxi NAND driver for SPL with DMA support

Hi,

Quoted 23 lines · Scott Wood
Quoted 22 lines · Piotr Zierhoffer
drivers/mtd/nand/sunxi_nand_spl.c new file +22 -0
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
+{
+     void *current_dest;
+     uint32_t count;
+     uint32_t current_count;
+     uint32_t ecc_errors = 0;
+
+     memset(dest, 0x0, size); /* clean destination memory */
+     for (current_dest = dest;
+                     current_dest < (dest + size);
+                     current_dest += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE) {
+             nand_read_page(offs, offs
+                             < CONFIG_NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END,
+                            &ecc_errors);
+             count = current_dest - dest;
+
+             if (size - count > CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE)
+                     current_count = CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
+             else
+                     current_count = size - count;
+
+             memcpy(current_dest,
Quoted 8 lines

drivers/mtd/nand/sunxi_nand_spl.c line 351

Quoted 6 lines
drivers/mtd/nand/sunxi_nand_spl.c new file +6 -0
+                    temp_buf,
+                    current_count);
+             offs += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
+     }
+     return ecc_errors ? -1 : 0;
+}

No bad block marker handling?

The bootrom does not use bad block marker handling (and allwinner's own FTL does neither for the non boot area, the actually mess up things by writing metadata which looks like classic bad block markers).

What we should do (in a follow up patch) is run some sanity checks (checksum of the image, etc.) and retry at a different offset if that fails. This is also what the bootrom does for loading the SPL itself, it simply tries to read it at a number of fixed addresses at the beginningen of the nand, so we should do the same looking for u-boot.bin at those same addresses (taking into account that u-boot.bin will be written after the SPL).

Regards,

Hans

Quoted 3 lines

-Scott

#5 lore raw

PATCH v3 2/4 sunxi: nand: Add basic sunxi NAND driver for SPL with DMA support

Hi Hans,

Quoted 35 lines · On Fri, 31 Jul 2015 10:36:43 +0200 Hans de Goede <[email protected]> wrote:

Hi,

Quoted 23 lines · Scott Wood
Quoted 22 lines · Piotr Zierhoffer
drivers/mtd/nand/sunxi_nand_spl.c new file +22 -0
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
+{
+     void *current_dest;
+     uint32_t count;
+     uint32_t current_count;
+     uint32_t ecc_errors = 0;
+
+     memset(dest, 0x0, size); /* clean destination memory */
+     for (current_dest = dest;
+                     current_dest < (dest + size);
+                     current_dest += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE) {
+             nand_read_page(offs, offs
+                             < CONFIG_NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END,
+                            &ecc_errors);
+             count = current_dest - dest;
+
+             if (size - count > CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE)
+                     current_count = CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
+             else
+                     current_count = size - count;
+
+             memcpy(current_dest,
Quoted 8 lines

drivers/mtd/nand/sunxi_nand_spl.c line 351

Quoted 6 lines
drivers/mtd/nand/sunxi_nand_spl.c new file +6 -0
+                    temp_buf,
+                    current_count);
+             offs += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
+     }
+     return ecc_errors ? -1 : 0;
+}

No bad block marker handling?

Quoted 4 lines

The bootrom does not use bad block marker handling (and allwinner's own FTL does neither for the non boot area, the actually mess up things by writing metadata which looks like classic bad block markers).

Hm, checking for bad block markers (and skipping bad blocks) is always a good thing, even if it does not by itself guarantee that the data stored in there are not corrupted.

Quoted 9 lines

What we should do (in a follow up patch) is run some sanity checks (checksum of the image, etc.) and retry at a different offset if that fails. This is also what the bootrom does for loading the SPL itself, it simply tries to read it at a number of fixed addresses at the beginningen of the nand, so we should do the same looking for u-boot.bin at those same addresses (taking into account that u-boot.bin will be written after the SPL).

Yes that's a solution: putting the u-boot binary in 2 (or more) distinct blocks (and maybe we should also repeat it over a given block to be more robust against bitflips) should address the case where the main u-boot block becomes bad.

Best Regards,

Boris

Signature · 3 lines
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
#6 lore raw

PATCH v3 2/4 sunxi: nand: Add basic sunxi NAND driver for SPL with DMA support

Quoted 40 lines · Boris Brezillon

Hi Hans,

Quoted 35 lines · On Fri, 31 Jul 2015 10:36:43 +0200 Hans de Goede <[email protected]> wrote:

Hi,

Quoted 31 lines · Scott Wood
Quoted 18 lines · Piotr Zierhoffer
drivers/mtd/nand/sunxi_nand_spl.c new file +18 -0
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
+{
+     void *current_dest;
+     uint32_t count;
+     uint32_t current_count;
+     uint32_t ecc_errors = 0;
+
+     memset(dest, 0x0, size); /* clean destination memory */
+     for (current_dest = dest;
+                     current_dest < (dest + size);
+                     current_dest += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE) {
+             nand_read_page(offs, offs
+                             < CONFIG_NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END,
+                            &ecc_errors);
+             count = current_dest - dest;
+
+             if (size - count > CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE)
+                     current_count = CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;

drivers/mtd/nand/sunxi_nand_spl.c line 351

Quoted 10 lines
drivers/mtd/nand/sunxi_nand_spl.c new file +10 -0
+             else
+                     current_count = size - count;
+
+             memcpy(current_dest,
+                    temp_buf,
+                    current_count);
+             offs += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
+     }
+     return ecc_errors ? -1 : 0;
+}

No bad block marker handling?

Quoted 8 lines
Quoted 4 lines

The bootrom does not use bad block marker handling (and allwinner's own FTL does neither for the non boot area, the actually mess up things by writing metadata which looks like classic bad block markers).

Hm, checking for bad block markers (and skipping bad blocks) is always a good thing, even if it does not by itself guarantee that the data stored in there are not corrupted.

Not on Allwinner hardware. Allwinner tools write data to the nand which looks like bad block markers so skipping blocks which appear marked as bad will inevitably skip valid blocks on many (most ?) Allwinner devices.

Only in the case you soldered a new nand chip yourself and never used Allwinner tools with it will the bad block markers remain valid. This is overall very unlikely so it should not be something SPL handles.

If you build custom devices and write devicetree for them then adding an option there might be worthwhile.

Thanks

Michal

#7 lore raw

PATCH v3 2/4 sunxi: nand: Add basic sunxi NAND driver for SPL with DMA support

Hi,

Quoted 47 lines · Michal Suchanek
Quoted 45 lines · Boris Brezillon

Hi Hans,

Quoted 39 lines · On Fri, 31 Jul 2015 10:36:43 +0200 Hans de Goede <[email protected]> wrote:

Hi,

Quoted 23 lines · Scott Wood
Quoted 22 lines · Piotr Zierhoffer
drivers/mtd/nand/sunxi_nand_spl.c new file +22 -0
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
+{
+     void *current_dest;
+     uint32_t count;
+     uint32_t current_count;
+     uint32_t ecc_errors = 0;
+
+     memset(dest, 0x0, size); /* clean destination memory */
+     for (current_dest = dest;
+                     current_dest < (dest + size);
+                     current_dest += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE) {
+             nand_read_page(offs, offs
+                             < CONFIG_NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END,
+                            &ecc_errors);
+             count = current_dest - dest;
+
+             if (size - count > CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE)
+                     current_count = CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
+             else
+                     current_count = size - count;
+
+             memcpy(current_dest,
Quoted 8 lines

drivers/mtd/nand/sunxi_nand_spl.c line 351

Quoted 6 lines
drivers/mtd/nand/sunxi_nand_spl.c new file +6 -0
+                    temp_buf,
+                    current_count);
+             offs += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
+     }
+     return ecc_errors ? -1 : 0;
+}

No bad block marker handling?

The bootrom does not use bad block marker handling (and allwinner's own FTL does neither for the non boot area, the actually mess up things by writing metadata which looks like classic bad block markers).

Quoted 8 lines
Quoted 3 lines

Hm, checking for bad block markers (and skipping bad blocks) is always a good thing, even if it does not by itself guarantee that the data stored in there are not corrupted.

Not on Allwinner hardware. Allwinner tools write data to the nand which looks like bad block markers so skipping blocks which appear marked as bad will inevitably skip valid blocks on many (most ?) Allwinner devices.

Right this has been my observation as well.

Quoted 3 lines

Only in the case you soldered a new nand chip yourself and never used Allwinner tools with it will the bad block markers remain valid. This is overall very unlikely so it should not be something SPL handles.

Or if you've some device where the nand was not initialized from the factory, I think some Olinuxino devices with nand fall into this category.

I agree that is best to simply ignore bad block markers on sunxi though, as they tend to lead to many false positives (think 60% of the entire nand consisting of bad blocks in my experience)

Regards,

Hans

#8 lore raw

PATCH v3 2/4 sunxi: nand: Add basic sunxi NAND driver for SPL with DMA support

In reply to Michal Suchanek

Hi Michal,

Quoted 47 lines · On Fri, 31 Jul 2015 16:25:00 +0200 Michal Suchanek <[email protected]> wrote:
Quoted 45 lines · Boris Brezillon

Hi Hans,

Quoted 39 lines · On Fri, 31 Jul 2015 10:36:43 +0200 Hans de Goede <[email protected]> wrote:

Hi,

Quoted 23 lines · Scott Wood
Quoted 22 lines · Piotr Zierhoffer
drivers/mtd/nand/sunxi_nand_spl.c new file +22 -0
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
+{
+     void *current_dest;
+     uint32_t count;
+     uint32_t current_count;
+     uint32_t ecc_errors = 0;
+
+     memset(dest, 0x0, size); /* clean destination memory */
+     for (current_dest = dest;
+                     current_dest < (dest + size);
+                     current_dest += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE) {
+             nand_read_page(offs, offs
+                             < CONFIG_NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END,
+                            &ecc_errors);
+             count = current_dest - dest;
+
+             if (size - count > CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE)
+                     current_count = CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
+             else
+                     current_count = size - count;
+
+             memcpy(current_dest,
Quoted 8 lines

drivers/mtd/nand/sunxi_nand_spl.c line 351

Quoted 6 lines
drivers/mtd/nand/sunxi_nand_spl.c new file +6 -0
+                    temp_buf,
+                    current_count);
+             offs += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
+     }
+     return ecc_errors ? -1 : 0;
+}

No bad block marker handling?

The bootrom does not use bad block marker handling (and allwinner's own FTL does neither for the non boot area, the actually mess up things by writing metadata which looks like classic bad block markers).

Quoted 8 lines
Quoted 3 lines

Hm, checking for bad block markers (and skipping bad blocks) is always a good thing, even if it does not by itself guarantee that the data stored in there are not corrupted.

Not on Allwinner hardware. Allwinner tools write data to the nand which looks like bad block markers so skipping blocks which appear marked as bad will inevitably skip valid blocks on many (most ?) Allwinner devices.

First of all, that's not exactly true. The allwinner NAND layer (and probably the tools allowing you to flash a new image) is actually writing the appropriate good block pattern (0xff), but this pattern is then randomized by the hardware randomizer, which makes it look like a bad block (!= 0xff).

The other aspect is, do we really have to support images flashed with this tool? I mean, I'm flashing my images using fel and a standard u-boot, and they generate perfectly valid images with valid bad block markers.

Quoted 4 lines

Only in the case you soldered a new nand chip yourself and never used Allwinner tools with it will the bad block markers remain valid. This is overall very unlikely so it should not be something SPL handles.

Here you're talking about the bad block markers 'corrupted' by the libnand layer (or the flashing tool).
To restore valid bad block markers you just have to launch nand scrub in u-boot.
I'm also thinking about a way to retrieve the real bad blocks even when the NAND has been used with an allwinner kernel (the idea is to first check without the randomizer disabled, and if it does not return 0xff, try to enable the randomizer, then if it still does not return 0xff, it's a real bad block).

But unless we want to support both mainline and non-mainline systems using the same SPL, that aspect is just something that should be handled when your moving from an allwinner image to a mainline one.

Best Regards,

Boris

Signature · 3 lines
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
#9 lore raw

PATCH v3 2/4 sunxi: nand: Add basic sunxi NAND driver for SPL with DMA support

Quoted 67 lines · Boris Brezillon

Hi Michal,

Quoted 47 lines · On Fri, 31 Jul 2015 16:25:00 +0200 Michal Suchanek <[email protected]> wrote:
Quoted 45 lines · Boris Brezillon

Hi Hans,

Quoted 39 lines · On Fri, 31 Jul 2015 10:36:43 +0200 Hans de Goede <[email protected]> wrote:

Hi,

Quoted 23 lines · Scott Wood
Quoted 22 lines · Piotr Zierhoffer
drivers/mtd/nand/sunxi_nand_spl.c new file +22 -0
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
+{
+     void *current_dest;
+     uint32_t count;
+     uint32_t current_count;
+     uint32_t ecc_errors = 0;
+
+     memset(dest, 0x0, size); /* clean destination memory */
+     for (current_dest = dest;
+                     current_dest < (dest + size);
+                     current_dest += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE) {
+             nand_read_page(offs, offs
+                             < CONFIG_NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END,
+                            &ecc_errors);
+             count = current_dest - dest;
+
+             if (size - count > CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE)
+                     current_count = CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
+             else
+                     current_count = size - count;
+
+             memcpy(current_dest,
Quoted 8 lines

drivers/mtd/nand/sunxi_nand_spl.c line 351

Quoted 6 lines
drivers/mtd/nand/sunxi_nand_spl.c new file +6 -0
+                    temp_buf,
+                    current_count);
+             offs += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
+     }
+     return ecc_errors ? -1 : 0;
+}

No bad block marker handling?

The bootrom does not use bad block marker handling (and allwinner's own FTL does neither for the non boot area, the actually mess up things by writing metadata which looks like classic bad block markers).

Quoted 8 lines
Quoted 3 lines

Hm, checking for bad block markers (and skipping bad blocks) is always a good thing, even if it does not by itself guarantee that the data stored in there are not corrupted.

Not on Allwinner hardware. Allwinner tools write data to the nand which looks like bad block markers so skipping blocks which appear marked as bad will inevitably skip valid blocks on many (most ?) Allwinner devices.

First of all, that's not exactly true. The allwinner NAND layer (and probably the tools allowing you to flash a new image) is actually writing the appropriate good block pattern (0xff), but this pattern is then randomized by the hardware randomizer, which makes it look like a bad block (!= 0xff).

Quoted 4 lines

The other aspect is, do we really have to support images flashed with this tool? I mean, I'm flashing my images using fel and a standard u-boot, and they generate perfectly valid images with valid bad block markers.

If u-boot takes into account the broken bad block markers generated by Allwinner tools it will make perfectly unusable image with invalid bad block markers.

I tried flashing my image by booting Linux from SD card and formatting the nand and it certainly did not go well with some past version of the driver.

Quoted 6 lines
Quoted 5 lines

Only in the case you soldered a new nand chip yourself and never used Allwinner tools with it will the bad block markers remain valid. This is overall very unlikely so it should not be something SPL handles.

Quoted 9 lines

Here you're talking about the bad block markers 'corrupted' by the libnand layer (or the flashing tool).
To restore valid bad block markers you just have to launch nand scrub in u-boot.
I'm also thinking about a way to retrieve the real bad blocks even when the NAND has been used with an allwinner kernel (the idea is to first check without the randomizer disabled, and if it does not return 0xff, try to enable the randomizer, then if it still does not return 0xff, it's a real bad block).

That would be good if it just detected bad blocks whatever format the flash was in previously.

Quoted 5 lines

But unless we want to support both mainline and non-mainline systems using the same SPL, that aspect is just something that should be handled when your moving from an allwinner image to a mainline one.

We probably want to support no-nonsense reimaging regardless of the previous nand content. You cannot expect users to track what they used last to flash their device.

Thanks

Michal

#10 lore raw

PATCH v3 2/4 sunxi: nand: Add basic sunxi NAND driver for SPL with DMA support

In reply to Boris Brezillon
Quoted 65 lines · Boris Brezillon

Hi Michal,

Quoted 60 lines · On Fri, 31 Jul 2015 16:25:00 +0200 Michal Suchanek <[email protected]> wrote:
Quoted 45 lines · Boris Brezillon

Hi Hans,

Quoted 40 lines · On Fri, 31 Jul 2015 10:36:43 +0200 Hans de Goede <[email protected]> wrote:

Hi,

Quoted 36 lines · Scott Wood
Quoted 23 lines · Piotr Zierhoffer

+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)

drivers/mtd/nand/sunxi_nand_spl.c new file +10 -0
+{
+     void *current_dest;
+     uint32_t count;
+     uint32_t current_count;
+     uint32_t ecc_errors = 0;
+
+     memset(dest, 0x0, size); /* clean destination memory */
+     for (current_dest = dest;
+                     current_dest < (dest + size);
+                     current_dest += 

CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE) {

(quoted diff) +2 -0
+             nand_read_page(offs, offs
+                             < 

CONFIG_NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END,

drivers/mtd/nand/sunxi_nand_spl.c new file +4 -0
+                            &ecc_errors);
+             count = current_dest - dest;
+
+             if (size - count > 

CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE)
+ current_count =
CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;

drivers/mtd/nand/sunxi_nand_spl.c line 351

Quoted 10 lines
drivers/mtd/nand/sunxi_nand_spl.c new file +10 -0
+             else
+                     current_count = size - count;
+
+             memcpy(current_dest,
+                    temp_buf,
+                    current_count);
+             offs += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
+     }
+     return ecc_errors ? -1 : 0;
+}

No bad block marker handling?

Quoted 8 lines
Quoted 4 lines

The bootrom does not use bad block marker handling (and allwinner's own FTL does neither for the non boot area, the actually mess up things by writing metadata which looks like classic bad block markers).

Hm, checking for bad block markers (and skipping bad blocks) is always a good thing, even if it does not by itself guarantee that the data stored in there are not corrupted.

Not on Allwinner hardware. Allwinner tools write data to the nand which looks like bad block markers so skipping blocks which appear marked as bad will inevitably skip valid blocks on many (most ?) Allwinner devices.

So, how do you prevent the bad block check from happening in non-SPL NAND code?

Quoted 12 lines

First of all, that's not exactly true. The allwinner NAND layer (and probably the tools allowing you to flash a new image) is actually writing the appropriate good block pattern (0xff), but this pattern is then randomized by the hardware randomizer, which makes it look like a bad block (!= 0xff).

The other aspect is, do we really have to support images flashed with this tool? I mean, I'm flashing my images using fel and a standard u-boot, and they generate perfectly valid images with valid bad block markers.

Quoted 1 line
Quoted 8 lines
Quoted 3 lines

Only in the case you soldered a new nand chip yourself and never used Allwinner tools with it will the bad block markers remain valid. This is overall very unlikely so it should not be something SPL handles.

Here you're talking about the bad block markers 'corrupted' by the libnand layer (or the flashing tool).
To restore valid bad block markers you just have to launch nand scrub in u-boot.

Are you talking about using scrub only on blocks that read as valid when unrandomized? Does the tool that writes these randomized images skip blocks that are marked bad?

-Scott

#11 lore raw

PATCH v3 3/4 sunxi: nand: Add board configuration options

In reply to Piotr Zierhoffer

When SPL_NAND_SUNXI option is selected in config, set some configuration options for sunxi NAND.

This commit also introduces the configurable options in Kconfig.

---

Changes in v3:
- added new options in Kconfig to support different chips
- changed descriptions to comply with patman rules

Changes in v2:
- removed traces of non-SPL specific code
- renamed defines to be more relevant
- moved Kconfig entry for the driver to drivers/mtd/nand
- reworded Kconfig entry help

 drivers/mtd/nand/Kconfig       | 40 ++++++++++++++++++++++++++++++++++++++++
 include/configs/sunxi-common.h | 10 ++++++++++
 2 files changed, 50 insertions(+)
drivers/mtd/nand/Kconfig +40 -0
index 3024357..41ebfea 100644
@@ -85,6 +85,46 @@ config SPL_NAND_DENALI
 	  This is a small implementation of the Denali NAND controller
 	  for use on SPL.
 
+config SPL_NAND_SUNXI
+	bool "Support for NAND on Allwinner A20 in SPL"
+	depends on MACH_SUN7I
+	---help---
+	Enable support for NAND. This option allows SPL to read from
+	sunxi NAND using DMA transfers.
+	Depending on the NAND chip, values like ECC strength and page sizes
+	have to be configured.
+
+config NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END
+	hex "Size of syndrome partitions in sunxi NAND"
+	default 0x400000
+	depends on SPL_NAND_SUNXI
+	---help---
+	End address for boot partitions on NAND. Those partitions have a
+	different random seed that has to match the sunxi BROM setting.
+
+config NAND_SUNXI_SPL_ECC_STRENGTH
+	int "ECC Strength for sunxi NAND"
+	default 40
+	depends on SPL_NAND_SUNXI
+	---help---
+	ECC strength used by the sunxi NAND SPL driver. This is specific to the
+	chosen NAND chip and has to match the value used by the sunxi BROM.
+
+config NAND_SUNXI_SPL_ECC_PAGE_SIZE
+	hex "ECC page size for sunxi NAND"
+	default 0x400
+	depends on SPL_NAND_SUNXI
+	---help---
+	ECC page size used by the sunxi NAND SPL driver for syndrome partitions.
+	This setting has to match the value used by the sunxi BROM.
+
+config NAND_SUNXI_SPL_PAGE_SIZE
+	hex "Page size for sunxi NAND"
+	default 0x2000
+	depends on SPL_NAND_SUNXI
+	---help---
+	Page size of the NAND flash used by the sunxi NAND SPL driver. This is
+	specific to the chosen NAND chip.
 endif
 
 endmenu
include/configs/sunxi-common.h +10 -0
index 9576bc1..1855ade 100644
@@ -139,6 +139,16 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_SERIAL_TAG
 
+#if defined(CONFIG_SPL_NAND_SUNXI)
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_SUPPORT
+
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x008000
+
+#endif
+
+
 /* mmc config */
 #if !defined(CONFIG_UART0_PORT_F)
 #define CONFIG_MMC
Signature · 1 line
2.3.6
#12 lore raw

PATCH v3 4/4 sunxi: nand: Add information to sunxi that it was run from NAND in SPL

In reply to Piotr Zierhoffer

As SPL does not know which source to choose when booting U-Boot, choose NAND if it is capable of doing so.

---

Changes in v3:
- none

Changes in v2:
- none

 arch/arm/cpu/armv7/sunxi/board.c | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm/cpu/armv7/sunxi/board.c +4 -0
index 5f39aa0..e4b7d63 100644
@@ -128,6 +128,9 @@ void s_init(void)
  */
 u32 spl_boot_device(void)
 {
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	return BOOT_DEVICE_NAND;
+#else
 	/*
 	 * When booting from the SD card, the "eGON.BT0" signature is expected
 	 * to be found in memory at the address 0x0004 (see the "mksunxiboot"
@@ -148,6 +151,7 @@ u32 spl_boot_device(void)
 		return BOOT_DEVICE_MMC1;
 	else
 		return BOOT_DEVICE_BOARD;
+#endif
 }
 
 /* No confirmation data available in SPL yet. Hardcode bootmode */
Signature · 1 line
2.3.6
#13 lore raw

v3 cover sunxi: nand: Basic NAND driver for SPL

In reply to Piotr Zierhoffer
Quoted 2 lines · Piotr Zierhoffer

This is a basic driver for the sunxi NAND controller for Allwinner A20. It supports only SPL.

Can you please elaborate how exactly is this specific only to SPL? Why?

Best regards,
Marek Vasut

#14 lore raw

v3 cover sunxi: nand: Basic NAND driver for SPL

Hi Marek

As BROM requires SPL binary size to be limited, we wanted to keep it very minimal.

This driver has no integration with full U-Boot driver structure. What's more, it does not support writing.

It was tested as SPL driver, so that's why I am submitting it as such.

Best regards

Piotr Zierhoffer,
Antmicro Ltd | www.antmicro.com
*Piotr Zierhoffer*
mobile: +48 696 419 606
Antmicro Ltd | www.antmicro.com
Zwierzyniecka 3, 60-813 Poznan, Poland

2015-07-23 16:04 GMT+02:00 Marek Vasut <[email protected]>:

Quoted 8 lines · Piotr Zierhoffer
Quoted 2 lines

This is a basic driver for the sunxi NAND controller for Allwinner A20. It supports only SPL.

Can you please elaborate how exactly is this specific only to SPL? Why?

Best regards,
Marek Vasut

#15 lore raw

v3 cover sunxi: nand: Basic NAND driver for SPL

Quoted 1 line · Piotr Zierhoffer

Hi Marek

Hi,

Quoted 7 lines

As BROM requires SPL binary size to be limited, we wanted to keep it very minimal.

This driver has no integration with full U-Boot driver structure. What's more, it does not support writing.

It was tested as SPL driver, so that's why I am submitting it as such.

Ah OK. Btw please fix your mailer to stop top-posting :)

Quoted 18 lines

Best regards

Piotr Zierhoffer,
Antmicro Ltd | www.antmicro.com
*Piotr Zierhoffer*
mobile: +48 696 419 606
Antmicro Ltd | www.antmicro.com
Zwierzyniecka 3, 60-813 Poznan, Poland

2015-07-23 16:04 GMT+02:00 Marek Vasut <[email protected]>:

Quoted 8 lines · Piotr Zierhoffer
Quoted 2 lines

This is a basic driver for the sunxi NAND controller for Allwinner A20. It supports only SPL.

Can you please elaborate how exactly is this specific only to SPL? Why?

Best regards,
Marek Vasut

Best regards,
Marek Vasut

#16 lore raw

v3 cover sunxi: nand: Basic NAND driver for SPL

In reply to Piotr Zierhoffer

Hi,

Quoted 4 lines · Piotr Zierhoffer

This is a basic driver for the sunxi NAND controller for Allwinner A20. It supports only SPL.

The driver uses DMA for data transfers. It does not support writing.

Thanks for your work on this.

I've merged patches 1 - 3 in my sunxi-wip branch, and I'll include them in the next u-boot-sunxi pull-req.

We do need to do some more work on this, to support more different sunxi SoCs, and to add some retry logic in case the default boot pages of the nand are bad, but that can both be done in follow-up commits.

Regards,

Hans

Quoted 49 lines

Changes in v3:
- moved pinmux and clock to board level
- code cleanup with significant size reduction
- renamed the driver file
- renamed constants to match Kconfig convention
- moved defines from .h to .c, and renamed them to be consistent with each other
- removed more magic values
- changed ecc_errors from static to local variable
- other minor changes
- added new options in Kconfig to support different chips
- changed descriptions to comply with patman rules

Changes in v2:
- removed traces of non-SPL-specific code
- moved the driver from boards/sunxi to drivers/mtd/nand
- moved magic values to defines (whenever possible)
- removed unnecesary late initialisation code
- code style changes as suggested for the first patch set:
- changed visibility of some symbols
- renamed unclear variables
- renamed header protector
- changed types of pointer variables
- other minor changes
- removed traces of non-SPL specific code
- renamed defines to be more relevant
- moved Kconfig entry for the driver to drivers/mtd/nand
- reworded Kconfig entry help

Karol Gugala (1):
sunxi: nand: Add pinmux and clock settings for NAND support

Piotr Zierhoffer (3):
sunxi: nand: Add basic sunxi NAND driver for SPL with DMA support
sunxi: nand: Add board configuration options
sunxi: nand: Add information to sunxi that it was run from NAND in SPL

  arch/arm/cpu/armv7/sunxi/board.c              |   4 +
  arch/arm/include/asm/arch-sunxi/clock_sun4i.h |   2 +
  arch/arm/include/asm/arch-sunxi/gpio.h        |   1 +
  board/sunxi/board.c                           |  27 ++
  drivers/mtd/nand/Kconfig                      |  40 +++
  drivers/mtd/nand/Makefile                     |   1 +
  drivers/mtd/nand/sunxi_nand_spl.c             | 353 ++++++++++++++++++++++++++
  include/configs/sunxi-common.h                |  10 +
  8 files changed, 438 insertions(+)

create mode 100644 drivers/mtd/nand/sunxi_nand_spl.c

#17 lore raw

v3 cover sunxi: nand: Basic NAND driver for SPL

Hi Hans,

Quoted 6 lines · On Sat, 1 Aug 2015 14:15:53 +0200 Hans de Goede <[email protected]> wrote:

Hi,

Quoted 3 lines · Piotr Zierhoffer

This is a basic driver for the sunxi NAND controller for Allwinner A20. It supports only SPL.

Quoted 6 lines
Quoted 1 line

The driver uses DMA for data transfers. It does not support writing.

Thanks for your work on this.

I've merged patches 1 - 3 in my sunxi-wip branch, and I'll include them in the next u-boot-sunxi pull-req.

Shouldn't we at least wait for Scoot's approval?

Best Regards,

Boris

Signature · 3 lines
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
#18 lore raw

v3 cover sunxi: nand: Basic NAND driver for SPL

Quoted 11 lines · Boris Brezillon

Hi Hans,

Quoted 6 lines · On Sat, 1 Aug 2015 14:15:53 +0200 Hans de Goede <[email protected]> wrote:

Hi,

Quoted 3 lines · Piotr Zierhoffer

This is a basic driver for the sunxi NAND controller for Allwinner A20. It supports only SPL.

Quoted 8 lines
Quoted 6 lines
Quoted 1 line

The driver uses DMA for data transfers. It does not support writing.

Thanks for your work on this.

I've merged patches 1 - 3 in my sunxi-wip branch, and I'll include them in the next u-boot-sunxi pull-req.

Shouldn't we at least wait for Scoot's approval?

Or Scott's. :-)

ACK, though I'd encourage quickly implementing multiple spl payload locations to work around the breakage of the bad block marker mechanism, as was discussed.

-Scott

#19 lore raw

v3 cover sunxi: nand: Basic NAND driver for SPL

Hi,

Quoted 16 lines · Scott Wood
Quoted 15 lines · Boris Brezillon

Hi Hans,

Quoted 10 lines · On Sat, 1 Aug 2015 14:15:53 +0200 Hans de Goede <[email protected]> wrote:

Hi,

Quoted 4 lines · Piotr Zierhoffer

This is a basic driver for the sunxi NAND controller for Allwinner A20. It supports only SPL.

The driver uses DMA for data transfers. It does not support writing.

Thanks for your work on this.

Quoted 8 lines
Quoted 4 lines
Quoted 2 lines

I've merged patches 1 - 3 in my sunxi-wip branch, and I'll include them in the next u-boot-sunxi pull-req.

Shouldn't we at least wait for Scoot's approval?

Or Scott's. :-)

ACK

Thanks.

Quoted 3 lines

though I'd encourage quickly implementing multiple spl payload locations to work around the breakage of the bad block marker mechanism, as was discussed.

I agree 100%, I've added note to my sunxi todo list for this. Note I only have this on my todo list as a reminder, since a few other people are actively working on sunxi nand support I hope that someone else will tackle this.

Regards,

Hans

#20 lore raw

v3 cover sunxi: nand: Basic NAND driver for SPL

Hello

2015-08-02 14:56 GMT+02:00 Hans de Goede <[email protected]>:

Quoted 42 lines

Hi,

Quoted 24 lines · Scott Wood
Quoted 22 lines · Boris Brezillon

Hi Hans,

Quoted 14 lines · On Sat, 1 Aug 2015 14:15:53 +0200 Hans de Goede <[email protected]> wrote:

Hi,

Quoted 5 lines · Piotr Zierhoffer

This is a basic driver for the sunxi NAND controller for Allwinner A20. It supports only SPL.

The driver uses DMA for data transfers. It does not support writing.

Thanks for your work on this.

I've merged patches 1 - 3 in my sunxi-wip branch, and I'll include them in the next u-boot-sunxi pull-req.

Quoted 6 lines
Quoted 1 line

Shouldn't we at least wait for Scoot's approval?

Or Scott's. :-)

ACK

Thanks.

Quoted 3 lines

though I'd encourage quickly implementing multiple spl payload locations to work around the breakage of the bad block marker mechanism, as was discussed.

Quoted 5 lines

I agree 100%, I've added note to my sunxi todo list for this. Note I only have this on my todo list as a reminder, since a few other people are actively
working on sunxi nand support I hope that someone else will tackle this.

Thank you for your ACKs on this.

Unfortunately, we do not have manpower to implement features you have mentioned at the moment.

Of course we will be willing to help with testing and fixing if anything comes up.

Best regards, thank you for your support

Piotr Zierhoffer
Antmicro Ltd | antmicro.com

#21 lore raw

v3 cover sunxi: nand: Basic NAND driver for SPL

Hi,

I've not done sunxi development for a while. So I need to ask you guys about some details. I hope you don't mind. Please see questions below.

Quoted 7 lines · Piotr Zierhoffer
Quoted 7 lines
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines

I've merged patches 1 - 3 in my sunxi-wip branch, and I'll include them in the next u-boot-sunxi pull-req.

Shouldn't we at least wait for Scoot's approval?

Quoted 6 lines
Quoted 6 lines
Quoted 3 lines

Or Scott's. :-)

ACK

Thanks.

Okay, this driver SPL NAND is now integrated in mainline. Great.

But how about NAND support for the main U-Boot (load Linux from NAND etc.)? It seems to be missing. Is somebody working on this? Whats the current status here?

Thanks,
Stefan

#22 lore raw

v3 cover sunxi: nand: Basic NAND driver for SPL

Hi,

Quoted 14 lines · Stefan Roese

Hi,

I've not done sunxi development for a while. So I need to ask you guys about some details. I hope you don't mind. Please see questions below.

Quoted 9 lines · Piotr Zierhoffer
Quoted 9 lines
Quoted 9 lines
Quoted 5 lines
Quoted 2 lines

I've merged patches 1 - 3 in my sunxi-wip branch, and I'll include them in the next u-boot-sunxi pull-req.

Shouldn't we at least wait for Scoot's approval?

Or Scott's. :-)

Quoted 8 lines
Quoted 4 lines
Quoted 4 lines
Quoted 1 line

ACK

Thanks.

Okay, this driver SPL NAND is now integrated in mainline. Great.

But how about NAND support for the main U-Boot (load Linux from NAND etc.)? It seems to be missing. Is somebody working on this?

Yes, see:

https://github.com/NextThingCo/CHIP-u-boot
https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-nand-wip

Quoted 1 line

Whats the current status here?

We want to use the Linux kernel code for the main U-Boot, which is not fully upstream yet (and will likely not be for a while) as it needs per partition config (ecc / scrambler) settings, as well as merging of scrambler support into the upstream kernel first.

We will likely have a u-boot branch with this working soon-ish, but getting this merged is a different story.

Regards,

Hans

#23 lore raw

v3 cover sunxi: nand: Basic NAND driver for SPL

Hi Hans,

Quoted 9 lines · Hans de Goede
Quoted 4 lines

Okay, this driver SPL NAND is now integrated in mainline. Great.

But how about NAND support for the main U-Boot (load Linux from NAND etc.)? It seems to be missing. Is somebody working on this?

Yes, see:

https://github.com/NextThingCo/CHIP-u-boot
https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-nand-wip

Thanks.

Quoted 6 lines
Quoted 1 line

Whats the current status here?

We want to use the Linux kernel code for the main U-Boot, which is not fully upstream yet (and will likely not be for a while) as it needs per partition config (ecc / scrambler) settings, as well as merging of scrambler support into the upstream kernel first.

Ah, right. I remember seeing some mails on this.

Quoted 1 line

We will likely have a u-boot branch with this working soon-ish,

That sounds interesting. I will probably start with NAND on an A20 board in the next 1-2 weeks. And will get back to you by then.

Quoted 1 line

but getting this merged is a different story.

Right. Perhaps when we combine our "forces" this might be easier...

Thanks,
Stefan

#24 lore raw

v3 cover sunxi: nand: Basic NAND driver for SPL

Hi Hans,

Quoted 6 lines · Stefan Roese
Quoted 4 lines

Yes, see:

https://github.com/NextThingCo/CHIP-u-boot
https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-nand-wip

Thanks.

I've started on your "sunxi-nand-wip" branch. And noticed that its currently stuck / hangs in nand_onfi_set_features() called via sunxi_nand_chip_init_timings(). I've attached 2 patches now:

One with some whitespace / coding-style fixes and more important a 2nd one that actually fixes some buggy pointer initialization.

I just wanted to share this improvement, even if the driver still does not work correctly. But at least its not crashing that early with this fix.

Comments welcome.

BTW: What is the current status of this code? From my debugging (see 2nd patch) it seems that this should not be good enough to run on any board yet.

Thanks,
Stefan

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#25 lore raw

v3 cover sunxi: nand: Basic NAND driver for SPL

Quoted 9 lines · Stefan Roese
Quoted 4 lines
Quoted 2 lines

https://github.com/NextThingCo/CHIP-u-boot
https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-nand-wip

Thanks.

I've started on your "sunxi-nand-wip" branch. And noticed that its currently stuck / hangs in nand_onfi_set_features() called via sunxi_nand_chip_init_timings(). I've attached 2 patches now:

Quoted 5 lines

One with some whitespace / coding-style fixes and more important a 2nd one that actually fixes some buggy pointer initialization.

I just wanted to share this improvement, even if the driver still does not work correctly. But at least its not crashing that early with this fix.

I forgot to mention that NAND detection takes very long with this patch (like 10 seconds). And all NAND block are marked as bad.

Thanks,
Stefan