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ARM: imx6ul: add fec1 and fec2 support for i.MX6ul 14x14 evk board

PATCH New Fugang Duan 2 participants 6 messages Jul 28, 2015 – Aug 5, 2015

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Fugang Duan

author
#0 lore raw

v2 cover ARM: imx6ul: add fec1 and fec2 support for i.MX6ul 14x14 evk board

Currently, upstream kernel support i.MX6ul 14x14 evk board, but don't support ethernet that bringup some inconvenient for other modules debug and support.

The patch series just add fec1 and fec2 two MACs support for the board.

Patch#1 and #2:
FEC MAC refrence clock needs extra GPR bit set to select clock source. The board install KSZ8081 that also needs extra phyfix.
Patch#3 and #4:
Add fec support for SOC and evk board in dts file.

Changes:
V2:
* As Shawn's suggestion:
Group <linux/*> headers together and have them sort alphabetically Remove PHY_ID_KSZ8081 as it is defined in include/linux/micrel_phy.h file.

Fugang Duan (4):
ARM: imx6ul: add fec bits to GPR syscon definition
ARM: imx6ul: add fec MAC refrence clock and phy fixup init
ARM: dts: imx: add fec1 and fec2 nodes for SOC i.MX6UL
ARM: dts: imx6ul-14x14-evk: add fec1 and fec2 support

 arch/arm/boot/dts/imx6ul-14x14-evk.dts      | 29 +++++++++++++++++++
 arch/arm/boot/dts/imx6ul.dtsi               | 37 +++++++++++++++++++++++++
 arch/arm/mach-imx/mach-imx6ul.c             | 43 +++++++++++++++++++++++++++++
 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h |  8 ++++++
 4 files changed, 117 insertions(+)
Signature · 1 line
1.9.1
author
#1 lore raw

PATCH v2 1/4 ARM: imx6ul: add fec bits to GPR syscon definition

FEC requires additional bits to select refrence clock.

Signed-off-by Fugang Duan <[email protected]>
---
 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++
 1 file changed, 8 insertions(+)
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +8 -0
index d16f4c8..558a485 100644
@@ -435,4 +435,12 @@
 #define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS			(0x1 << 1)
 #define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK			(0x1 << 1)
 
+/* For imx6ul iomux gpr register field define */
+#define IMX6UL_GPR1_ENET1_CLK_DIR		(0x1 << 17)
+#define IMX6UL_GPR1_ENET2_CLK_DIR		(0x1 << 18)
+#define IMX6UL_GPR1_ENET1_CLK_OUTPUT		(0x1 << 17)
+#define IMX6UL_GPR1_ENET2_CLK_OUTPUT		(0x1 << 18)
+#define IMX6UL_GPR1_ENET_CLK_DIR		(0x3 << 17)
+#define IMX6UL_GPR1_ENET_CLK_OUTPUT		(0x3 << 17)
+
 #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
Signature · 1 line
1.9.1
author
#2 lore raw

PATCH v2 2/4 ARM: imx6ul: add fec MAC refrence clock and phy fixup init

In reply to Fugang Duan

Add FEC MAC refrence clock init.
Add phy fixup init for i.MX6ul 14x14 evk board that installs KSZ8081 phy. For the phy, there needs extra phy fixup for MII and RMII mode.

Signed-off-by Fugang Duan <[email protected]>
---
 arch/arm/mach-imx/mach-imx6ul.c | 43 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
arch/arm/mach-imx/mach-imx6ul.c +43 -0
index f206506..0d81152 100644
@@ -7,11 +7,53 @@
  */
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+#include <linux/micrel_phy.h>
+#include <linux/phy.h>
+#include <linux/regmap.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include "common.h"
 
+static void __init imx6ul_enet_clk_init(void)
+{
+	struct regmap *gpr;
+
+	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
+	if (!IS_ERR(gpr))
+		regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
+				   IMX6UL_GPR1_ENET_CLK_OUTPUT);
+	else
+		pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
+
+}
+
+static int ksz8081_phy_fixup(struct phy_device *dev)
+{
+	if (dev && dev->interface == PHY_INTERFACE_MODE_MII) {
+		phy_write(dev, 0x1f, 0x8110);
+		phy_write(dev, 0x16, 0x201);
+	} else if (dev && dev->interface == PHY_INTERFACE_MODE_RMII) {
+		phy_write(dev, 0x1f, 0x8190);
+		phy_write(dev, 0x16, 0x202);
+	}
+
+	return 0;
+}
+
+static void __init imx6ul_enet_phy_init(void)
+{
+	phy_register_fixup_for_uid(PHY_ID_KSZ8081, 0xffffffff, ksz8081_phy_fixup);
+}
+
+static inline void imx6ul_enet_init(void)
+{
+	imx6ul_enet_clk_init();
+	imx6ul_enet_phy_init();
+}
+
 static void __init imx6ul_init_machine(void)
 {
 	struct device *parent;

@@ -21,6 +63,7 @@ static void __init imx6ul_init_machine(void)
 		pr_warn("failed to initialize soc device\n");
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+	imx6ul_enet_init();
 	imx_anatop_init();
 }
Signature · 1 line
1.9.1
#3 lore raw

PATCH v2 2/4 ARM: imx6ul: add fec MAC refrence clock and phy fixup init

Quoted 14 lines · Fugang Duan

Add FEC MAC refrence clock init.
Add phy fixup init for i.MX6ul 14x14 evk board that installs KSZ8081 phy. For the phy, there needs extra phy fixup for MII and RMII mode.

Signed-off-by Fugang Duan <[email protected]>
---
 arch/arm/mach-imx/mach-imx6ul.c | 43 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
arch/arm/mach-imx/mach-imx6ul.c +0 -0
index f206506..0d81152 100644

arch/arm/mach-imx/mach-imx6ul.c line 12

Quoted 6 lines
arch/arm/mach-imx/mach-imx6ul.c +3 -0
@@ -7,11 +7,53 @@
  */
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+#include <linux/micrel_phy.h>

'm' should go above 'o', right? I fixed the ordering and applied the whole series.

Shawn

Quoted 64 lines
arch/arm/mach-imx/mach-imx6ul.c +40 -0
+#include <linux/phy.h>
+#include <linux/regmap.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include "common.h"
 
+static void __init imx6ul_enet_clk_init(void)
+{
+	struct regmap *gpr;
+
+	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
+	if (!IS_ERR(gpr))
+		regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
+				   IMX6UL_GPR1_ENET_CLK_OUTPUT);
+	else
+		pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
+
+}
+
+static int ksz8081_phy_fixup(struct phy_device *dev)
+{
+	if (dev && dev->interface == PHY_INTERFACE_MODE_MII) {
+		phy_write(dev, 0x1f, 0x8110);
+		phy_write(dev, 0x16, 0x201);
+	} else if (dev && dev->interface == PHY_INTERFACE_MODE_RMII) {
+		phy_write(dev, 0x1f, 0x8190);
+		phy_write(dev, 0x16, 0x202);
+	}
+
+	return 0;
+}
+
+static void __init imx6ul_enet_phy_init(void)
+{
+	phy_register_fixup_for_uid(PHY_ID_KSZ8081, 0xffffffff, ksz8081_phy_fixup);
+}
+
+static inline void imx6ul_enet_init(void)
+{
+	imx6ul_enet_clk_init();
+	imx6ul_enet_phy_init();
+}
+
 static void __init imx6ul_init_machine(void)
 {
 	struct device *parent;

@@ -21,6 +63,7 @@ static void __init imx6ul_init_machine(void)
 		pr_warn("failed to initialize soc device\n");
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+	imx6ul_enet_init();
 	imx_anatop_init();
 }
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author
#4 lore raw

PATCH v2 3/4 ARM: dts: imx: add fec1 and fec2 nodes for SOC i.MX6UL

In reply to Fugang Duan

SOC i.MX6UL has two ethernet MACs, add fec1 and fec2 support for i.MX6UL.

Signed-off-by Fugang Duan <[email protected]>
---
 arch/arm/boot/dts/imx6ul.dtsi | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
arch/arm/boot/dts/imx6ul.dtsi +37 -0
index dc0f5b4..3190e6c 100644
@@ -14,6 +14,8 @@
 
 / {
 	aliases {
+		ethernet0 = &fec1;
+		ethernet1 = &fec2;
 		gpio0 = &gpio1;
 		gpio1 = &gpio2;
 		gpio2 = &gpio3;

@@ -293,6 +295,23 @@
 				#interrupt-cells = <2>;
 			};
 
+			fec2: ethernet at 020b4000 {
+				compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
+				reg = <0x020b4000 0x4000>;
+				interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6UL_CLK_ENET>,
+					 <&clks IMX6UL_CLK_ENET_AHB>,
+					 <&clks IMX6UL_CLK_ENET_PTP>,
+					 <&clks IMX6UL_CLK_ENET2_REF_125M>,
+					 <&clks IMX6UL_CLK_ENET2_REF_125M>;
+				clock-names = "ipg", "ahb", "ptp",
+					      "enet_clk_ref", "enet_out";
+				fsl,num-tx-queues=<1>;
+				fsl,num-rx-queues=<1>;
+				status = "disabled";
+			};
+
 			wdog1: wdog at 020bc000 {
 				compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 				reg = <0x020bc000 0x4000>;

@@ -484,6 +503,24 @@
 			reg = <0x02100000 0x100000>;
 			ranges;
 
+			fec1: ethernet at 02188000 {
+				compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
+				reg = <0x02188000 0x4000>;
+				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6UL_CLK_ENET>,
+					 <&clks IMX6UL_CLK_ENET_AHB>,
+					 <&clks IMX6UL_CLK_ENET_PTP>,
+					 <&clks IMX6UL_CLK_ENET_REF>,
+					 <&clks IMX6UL_CLK_ENET_REF>;
+				clock-names = "ipg", "ahb", "ptp",
+					      "enet_clk_ref", "enet_out";
+				fsl,num-tx-queues=<1>;
+				fsl,num-rx-queues=<1>;
+				status = "disabled";
+			};
+
+
 			usdhc1: usdhc at 02190000 {
 				compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 				reg = <0x02190000 0x4000>;
Signature · 1 line
1.9.1
author
#5 lore raw

PATCH v2 4/4 ARM: dts: imx6ul-14x14-evk: add fec1 and fec2 support

In reply to Fugang Duan

Add ethernet fec1 and fec2 support for i.MX6ul 14x14 evk board.

Signed-off-by Fugang Duan <[email protected]>
---
 arch/arm/boot/dts/imx6ul-14x14-evk.dts | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
arch/arm/boot/dts/imx6ul-14x14-evk.dts +29 -0
index 61b41ee..ef93291 100644
@@ -44,6 +44,35 @@
 	soc-supply = <&reg_soc>;
 };
 
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy1>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy at 2 {
+			reg = <2>;
+		};
+
+		ethphy1: ethernet-phy at 1 {
+			reg = <1>;
+		};
+	};
+};
+
 &uart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1>;
Signature · 1 line
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