LPC18xx DTS changes for 4.3 part2
Subsystems (2)
cover LPC18xx DTS changes for 4.3 part2
Here is some more LPC18xx dts changes for v4.3. This is the dts changes for the drivers that will go in for v4.3. Note that the USB phy driver is not in next yet, but is queued on Kishon's phy next repo.
Changes include:
- Add USB OTG phy, PL111 LCD controller and PL172 memory controller nodes to lpc18xx.dtsi
- Enable USB0 on EA4357 Dev Kit
- Add static memory devices on EA4357 Dev Kit
- Enable UART0 pinmux and Ethernet on Hitex Eval Board from Ariel D'Alessandro
- Add static memory devices on Hitex Eval Board
Changes are also available in the git repository at:
https://github.com/manabian/linux-lpc.git tags/lpc18xx_dts_for_4.3-part2
Ariel D'Alessandro (2):
ARM: dts: lpc4350-hitex-eval: add pinctrl and uart0 muxing
ARM: dts: lpc4350-hitex-eval: add ethernet
Joachim Eastwood (7):
ARM: dts: lpc18xx: add usb otg phy node
ARM: dts: lpc18xx: add pl111 lcd controller node
ARM: dts: lpc18xx: add pl172 memory-controller node
ARM: dts: lpc4357-ea4357: add usb0
ARM: dts: lpc4357-ea4357: add emc pins and static memory devices
ARM: dts: lpc4357-ea4357: add mmio-gpio leds
ARM: dts: lpc4350-hitex-eval: add emc pins and static memory devices
arch/arm/boot/dts/lpc18xx.dtsi | 32 ++++ arch/arm/boot/dts/lpc4350-hitex-eval.dts | 244 +++++++++++++++++++++++++++ arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 253 ++++++++++++++++++++++++++++ 3 files changed, 529 insertions(+)
Signature · 1 line
1.8.0
PATCH 1/9 ARM: dts: lpc18xx: add usb otg phy node
Add the USB OTG phy under the CREG syscon node and attach it to the USB0 EHCI controller.
--- arch/arm/boot/dts/lpc18xx.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)
arch/arm/boot/dts/lpc18xx.dtsi +8 -0
@@ -83,6 +83,8 @@ reg = <0x40006100 0x100>; interrupts = <8>; clocks = <&ccu1 CLK_CPU_USB0>; + phys = <&usb0_otg_phy>; + phy-names = "usb"; has-transaction-translator; status = "disabled"; };
@@ -109,6 +111,12 @@ compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; reg = <0x40043000 0x1000>; clocks = <&ccu1 CLK_CPU_CREG>; + + usb0_otg_phy: phy at 004 { + compatible = "nxp,lpc1850-usb-otg-phy"; + clocks = <&ccu1 CLK_USB0>; + #phy-cells = <0>; + }; }; cgu: clock-controller at 40050000 {
Signature · 1 line
1.8.0
PATCH 2/9 ARM: dts: lpc18xx: add pl111 lcd controller node
In reply to Joachim EastwoodNXP LPC185x and LPC435x/70 devices contain a ARM PL111 lcd controller.
--- arch/arm/boot/dts/lpc18xx.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
arch/arm/boot/dts/lpc18xx.dtsi +10 -0
@@ -97,6 +97,16 @@ status = "disabled"; }; + lcdc: lcd-controller at 40008000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x40008000 0x1000>; + interrupts = <7>; + interrupt-names = "combined"; + clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>; + clock-names = "clcdclk", "apb_pclk"; + status = "disabled"; + }; + mac: ethernet at 40010000 { compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; reg = <0x40010000 0x2000>;
Signature · 1 line
1.8.0
PATCH 3/9 ARM: dts: lpc18xx: add pl172 memory-controller node
In reply to Joachim EastwoodAll devices in the LPC18xx/43xx familiy contain a ARM PL172 MultiPort Memory Controller (MPMC).
--- arch/arm/boot/dts/lpc18xx.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/boot/dts/lpc18xx.dtsi +14 -0
@@ -97,6 +97,20 @@ status = "disabled"; }; + emc: memory-controller at 40005000 { + compatible = "arm,pl172", "arm,primecell"; + reg = <0x40005000 0x1000>; + clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; + clock-names = "mpmcclk", "apb_pclk"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x1c000000 0x1000000 + 1 0 0x1d000000 0x1000000 + 2 0 0x1e000000 0x1000000 + 3 0 0x1f000000 0x1000000>; + status = "disabled"; + }; + lcdc: lcd-controller at 40008000 { compatible = "arm,pl111", "arm,primecell"; reg = <0x40008000 0x1000>;
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1.8.0
PATCH 4/9 ARM: dts: lpc4357-ea4357: add usb0
In reply to Joachim EastwoodEnable USB0 on the EA4357 devkit and setup the required USB0 control pins.
--- arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +20 -0
@@ -221,6 +221,20 @@ bias-pull-down; }; }; + + usb0_pins: usb0-pins { + usb0_pwr_enable { + pins = "p2_3"; + function = "usb0"; + }; + + usb0_pwr_fault { + pins = "p8_0"; + function = "usb0"; + bias-disable; + input-enable; + }; + }; }; &enet_tx_clk {
@@ -253,3 +267,9 @@ pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; + +&usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; +};
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1.8.0
PATCH 5/9 ARM: dts: lpc4357-ea4357: add emc pins and static memory devices
In reply to Joachim EastwoodSetup the emc pins used by external memory devices and add configuration for the devices found on the EA4357 devkit.
The EA4357 devkit has a NOR Flash attached to chip select 0 and a D-type flip-flop used for LEDs on chip select 2.
--- arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 164 ++++++++++++++++++++++++++++ 1 file changed, 164 insertions(+)
arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +164 -0
@@ -88,6 +88,110 @@ }; &pinctrl { + emc_pins: emc-pins { + emc_addr0_23_cfg { + pins = "p2_9", "p2_10", "p2_11", "p2_12", + "p2_13", "p1_0", "p1_1", "p1_2", + "p2_8", "p2_7", "p2_6", "p2_2", + "p2_1", "p2_0", "p6_8", "p6_7", + "pd_16", "pd_15", "pe_0", "pe_1", + "pe_2", "pe_3", "pe_4", "pa_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_data0_31_cfg { + pins = "p1_7", "p1_8", "p1_9", "p1_10", + "p1_11", "p1_12", "p1_13", "p1_14", + "p5_4", "p5_5", "p5_6", "p5_7", + "p5_0", "p5_1", "p5_2", "p5_3", + "pd_2", "pd_3", "pd_4", "pd_5", + "pd_6", "pd_7", "pd_8", "pd_9", + "pe_5", "pe_6", "pe_7", "pe_8", + "pe_9", "pe_10", "pe_11", "pe_12"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_we_oe_cfg { + pins = "p1_6", "p1_3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_bls0_3_cfg { + pins = "p1_4", "p6_6", "pd_13", "pd_10"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_cs0_3_cfg { + pins = "p1_5", "p6_3", "pd_12", "pd_11"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_dqm0_3_cfg { + pins = "p6_12", "p6_10", "pd_0", "pe_13"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_ras_cas_cfg { + pins = "p6_5", "p6_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_dycs0_cfg { + pins = "p6_9"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_cke_cfg { + pins = "p6_11"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_clock_cfg { + pins = "clk0", "clk1", "clk2", "clk3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + }; + enet_rmii_pins: enet-rmii-pins { enet_rmii_rxd_cfg { pins = "p1_15", "p0_0";
@@ -237,6 +341,66 @@ }; }; +&emc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&emc_pins>; + + cs0 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mpmc,cs = <0>; + mpmc,memory-width = <16>; + mpmc,byte-lane-low; + mpmc,write-enable-delay = <0>; + mpmc,output-enable-delay = <0>; + mpmc,read-access-delay = <70>; + mpmc,page-mode-read-delay = <70>; + + flash at 0,0 { + compatible = "sst,sst39vf320", "cfi-flash"; + reg = <0 0 0x400000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + partition at 0 { + label = "bootloader"; + reg = <0x000000 0x040000>; /* 256 KiB */ + }; + + partition at 1 { + label = "kernel"; + reg = <0x040000 0x2c0000>; /* 2.75 MiB */ + }; + + partition at 2 { + label = "rootfs"; + reg = <0x300000 0x100000>; /* 1 MiB */ + }; + }; + }; + + cs2 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mpmc,cs = <2>; + mpmc,memory-width = <16>; + + mmio_leds: gpio at 2,0 { + compatible = "ti,7416374"; + reg = <2 0 0x2>; + gpio-controller; + #gpio-cells = <2>; + }; + + }; +}; + &enet_tx_clk { clock-frequency = <50000000>; };
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1.8.0
PATCH 6/9 ARM: dts: lpc4357-ea4357: add mmio-gpio leds
In reply to Joachim EastwoodHook up LEDs on the outputs from the D-type flip-flop found on the address/data bus.
Note that the LEDx label in the schematics is reversed in regard to the bits on the data bus. Hence the reverse ordering used here.
--- arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 69 +++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+)
arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +69 -0
@@ -85,6 +85,75 @@ gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>; }; }; + + leds_mmio { + compatible = "gpio-leds"; + + led1 { + gpios = <&mmio_leds 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led2 { + gpios = <&mmio_leds 14 GPIO_ACTIVE_HIGH>; + }; + + led3 { + gpios = <&mmio_leds 13 GPIO_ACTIVE_HIGH>; + }; + + led4 { + gpios = <&mmio_leds 12 GPIO_ACTIVE_HIGH>; + }; + + led5 { + gpios = <&mmio_leds 11 GPIO_ACTIVE_HIGH>; + }; + + led6 { + gpios = <&mmio_leds 10 GPIO_ACTIVE_HIGH>; + }; + + led7 { + gpios = <&mmio_leds 9 GPIO_ACTIVE_HIGH>; + }; + + led8 { + gpios = <&mmio_leds 8 GPIO_ACTIVE_HIGH>; + }; + + led9 { + gpios = <&mmio_leds 7 GPIO_ACTIVE_HIGH>; + }; + + led10 { + gpios = <&mmio_leds 6 GPIO_ACTIVE_HIGH>; + }; + + led11 { + gpios = <&mmio_leds 5 GPIO_ACTIVE_HIGH>; + }; + + led12 { + gpios = <&mmio_leds 4 GPIO_ACTIVE_HIGH>; + }; + + led13 { + gpios = <&mmio_leds 3 GPIO_ACTIVE_HIGH>; + }; + + led14 { + gpios = <&mmio_leds 2 GPIO_ACTIVE_HIGH>; + }; + + led15 { + gpios = <&mmio_leds 1 GPIO_ACTIVE_HIGH>; + }; + + led16 { + gpios = <&mmio_leds 0 GPIO_ACTIVE_HIGH>; + }; + }; }; &pinctrl {
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1.8.0
PATCH 7/9 ARM: dts: lpc4350-hitex-eval: add pinctrl and uart0 muxing
In reply to Joachim EastwoodFrom: Ariel D'Alessandro <[email protected]>
Setup pin muxing and properties for the debug console on uart0.
--- arch/arm/boot/dts/lpc4350-hitex-eval.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
arch/arm/boot/dts/lpc4350-hitex-eval.dts +20 -0
@@ -36,6 +36,26 @@ }; }; +&pinctrl { + uart0_pins: uart0-pins { + uart0_rx_cfg { + pins = "pf_11"; + function = "uart0"; + input-schmitt-disable; + bias-disable; + input-enable; + }; + + uart0_tx_cfg { + pins = "pf_10"; + function = "uart0"; + bias-pull-down; + }; + }; +}; + &uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; };
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1.8.0
PATCH 8/9 ARM: dts: lpc4350-hitex-eval: add ethernet
In reply to Joachim EastwoodFrom: Ariel D'Alessandro <[email protected]>
Enable Ethernet and add pin muxing and set the correct frequency on the enet tx clock input.
--- arch/arm/boot/dts/lpc4350-hitex-eval.dts | 60 ++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+)
arch/arm/boot/dts/lpc4350-hitex-eval.dts +60 -0
@@ -37,6 +37,55 @@ }; &pinctrl { + enet_mii_pins: enet-mii-pins { + enet_mii_rxd0_3_cfg { + pins = "p1_15", "p0_0", "p9_3", "p9_2"; + function = "enet"; + bias-disable; + input-enable; + }; + + enet_mii_txd0_3_cfg { + pins = "p1_18", "p1_20", "p9_4", "p9_5"; + function = "enet"; + bias-disable; + }; + + enet_mii_crs_col_cfg { + pins = "p9_0", "p9_6"; + function = "enet"; + bias-disable; + input-enable; + }; + + enet_mii_rx_clk_dv_er_cfg { + pins = "pc_0", "p1_16", "p9_1"; + function = "enet"; + bias-disable; + input-enable; + }; + + enet_mii_tx_clk_en_cfg { + pins = "p1_19", "p0_1"; + function = "enet"; + bias-disable; + input-enable; + }; + + enet_mdio_cfg { + pins = "p1_17"; + function = "enet"; + bias-disable; + input-enable; + }; + + enet_mdc_cfg { + pins = "pc_1"; + function = "enet"; + bias-disable; + }; + }; + uart0_pins: uart0-pins { uart0_rx_cfg { pins = "pf_11";
@@ -54,6 +103,17 @@ }; }; +&enet_tx_clk { + clock-frequency = <25000000>; +}; + +&mac { + status = "okay"; + phy-mode = "mii"; + pinctrl-names = "default"; + pinctrl-0 = <&enet_mii_pins>; +}; + &uart0 { status = "okay"; pinctrl-names = "default";
Signature · 1 line
1.8.0
PATCH 9/9 ARM: dts: lpc4350-hitex-eval: add emc pins and static memory devices
In reply to Joachim EastwoodSetup the emc pins used by external memory devices and add configuration for the devices found on the Hitex eval board.
The Hitex eval board has a NOR Flash attached to chip select 0 and 512 kB of SRAM on chip select 2.
--- arch/arm/boot/dts/lpc4350-hitex-eval.dts | 164 +++++++++++++++++++++++++++++++ 1 file changed, 164 insertions(+)
arch/arm/boot/dts/lpc4350-hitex-eval.dts +164 -0
@@ -37,6 +37,106 @@ }; &pinctrl { + emc_pins: emc-pins { + emc_addr0_23_cfg { + pins = "p2_9", "p2_10", "p2_11", "p2_12", + "p2_13", "p1_0", "p1_1", "p1_2", + "p2_8", "p2_7", "p2_6", "p2_2", + "p2_1", "p2_0", "p6_8", "p6_7", + "pd_16", "pd_15", "pe_0", "pe_1", + "pe_2", "pe_3", "pe_4", "pa_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_data0_15_cfg { + pins = "p1_7", "p1_8", "p1_9", "p1_10", + "p1_11", "p1_12", "p1_13", "p1_14", + "p5_4", "p5_5", "p5_6", "p5_7", + "p5_0", "p5_1", "p5_2", "p5_3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_we_oe_cfg { + pins = "p1_6", "p1_3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_bls0_3_cfg { + pins = "p1_4", "p6_6", "pd_13", "pd_10"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_cs0_cs2_cfg { + pins = "p1_5", "pd_12"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_dqm0_3_cfg { + pins = "p6_12", "p6_10", "pd_0", "pe_13"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_ras_cas_cfg { + pins = "p6_5", "p6_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_dycs0_cfg { + pins = "p6_9"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_cke_cfg { + pins = "p6_11"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + emc_sdram_clock_cfg { + pins = "clk0", "clk1", "clk2", "clk3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + }; + enet_mii_pins: enet-mii-pins { enet_mii_rxd0_3_cfg { pins = "p1_15", "p0_0", "p9_3", "p9_2";
@@ -103,6 +203,70 @@ }; }; +&emc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&emc_pins>; + + cs0 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mpmc,cs = <0>; + mpmc,memory-width = <16>; + mpmc,byte-lane-low; + mpmc,write-enable-delay = <0>; + mpmc,output-enable-delay = <0>; + mpmc,read-access-delay = <70>; + mpmc,page-mode-read-delay = <70>; + + flash at 0,0 { + compatible = "sst,sst39vf320", "cfi-flash"; + reg = <0 0 0x400000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + partition at 0 { + label = "bootloader"; + reg = <0x000000 0x040000>; /* 256 KiB */ + }; + + partition at 1 { + label = "kernel"; + reg = <0x040000 0x2C0000>; /* 2.75 MiB */ + }; + + partition at 2 { + label = "rootfs"; + reg = <0x300000 0x100000>; /* 1 MiB */ + }; + }; + }; + + cs2 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mpmc,cs = <2>; + mpmc,memory-width = <16>; + mpmc,byte-lane-low; + mpmc,write-enable-delay = <0>; + mpmc,output-enable-delay = <30>; + mpmc,read-access-delay = <90>; + mpmc,page-mode-read-delay = <55>; + mpmc,write-access-delay = <55>; + mpmc,turn-round-delay = <55>; + + ext_sram: sram at 2,0 { + compatible = "mmio-sram"; + reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */ + }; + }; +}; + &enet_tx_clk { clock-frequency = <25000000>; };
Signature · 1 line
1.8.0
cover LPC18xx DTS changes for 4.3 part2
In reply to Joachim EastwoodQuoted 14 lines · Joachim Eastwood
Here is some more LPC18xx dts changes for v4.3. This is the dts changes for the drivers that will go in for v4.3. Note that the USB phy driver is not in next yet, but is queued on Kishon's phy next repo.
Changes include:
- Add USB OTG phy, PL111 LCD controller and PL172 memory controller nodes to
lpc18xx.dtsi- Enable USB0 on EA4357 Dev Kit
- Add static memory devices on EA4357 Dev Kit
Quoted 8 lines
- Enable UART0 pinmux and Ethernet on Hitex Eval Board from Ariel D'Alessandro
- Add static memory devices on Hitex Eval Board
Changes are also available in the git repository at:
https://github.com/manabian/linux-lpc.git tags/lpc18xx_dts_for_4.3-part2
Thanks, I missed the pull request until I had already applied them directly.
Feel free to use the standard git request-pull format in the future. :)
-Olof