x86: baytrail: Configure FSP UPD from device tree

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Signed-off-by Andrew Bradford <[email protected]>

---

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

I enabled the MRC debug messages as it was helpful to me as there are a set of FSP UPD device tree properties which during my development turned out to boot enough for the MRC code in the FSP to run but which would not actually end up starting u-boot. At least having the MRC debug message print out showed me that at least u-boot was operating enough to call into the FSP and that likely I had something misconfigured in the UPD memory settings. Probably not showing these debug messages is the right choice, as if someone wants more debug output then they can also use the FSPv4 debug build that Intel now provides.

Thanks for your help with this patch! :)
-Andrew

Hi Andrew,

Quoted 42 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

Quoted 4 lines

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

Hi Andrew,

Quoted 54 lines · Andrew Bradford

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 6 lines

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

OK, my test shows that ehci works fine in U-Boot on Bayley Bay.

Hi Simon,

What do you think regarding to xhci vs. ehci in U-Boot?

Hi Bin,

Quoted 69 lines · Bin Meng

Hi Andrew,

Quoted 54 lines · Andrew Bradford

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 6 lines

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

OK, my test shows that ehci works fine in U-Boot on Bayley Bay.

Hi Simon,

Quoted 1 line

What do you think regarding to xhci vs. ehci in U-Boot?

The problem is that USB is then broken in U-Boot. I think it is better to limit the speed for the moment until we have that fixed. It is quite useful to be able to use a keyboard or USB stick in U-Boot.

With my testing the bottom (blue) port works fine but the top port does not. This happens regardless of the xhci setting.

So overall I think we are in a better position to go with ehci for now, i.e. drop the fsp,enable-xhci property.

I think there is a little tweak needed to support both ports, but I haven't dug into it yet.

Hi Simon,

Quoted 72 lines · Simon Glass

Hi Bin,

Quoted 69 lines · Bin Meng

Hi Andrew,

Quoted 54 lines · Andrew Bradford

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 6 lines

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

OK, my test shows that ehci works fine in U-Boot on Bayley Bay.

Hi Simon,

Quoted 8 lines

Quoted 1 line

What do you think regarding to xhci vs. ehci in U-Boot?

The problem is that USB is then broken in U-Boot. I think it is better to limit the speed for the moment until we have that fixed. It is quite useful to be able to use a keyboard or USB stick in U-Boot.

With my testing the bottom (blue) port works fine but the top port does not. This happens regardless of the xhci setting.

There are 3 ports on Intel Bayley Bay. One USB 3 (blue port) and two USB 2 ports. The board user guide explicitly mentions that the top USB 2 port does not work and needs PCB rework. For the other two ports, I've tested U-Boot EHCI stack and it works fine. Interesting to hear that MinnowMax also has some USB port issue. Maybe the board design is following Bayley Bay.

Quoted 4 lines

So overall I think we are in a better position to go with ehci for now, i.e. drop the fsp,enable-xhci property.

OK, then could you please remove this for Bayley Bay as well? Also I think we need remove the MRC debug output as well.

Quoted 5 lines

I think there is a little tweak needed to support both ports, but I haven't dug into it yet.

This is not possible. According to Intel E3800 datasheet, the xHCI and EHCI are mutually exclusive. We can either use xHCI, or EHCI.

Hi Bin,

Quoted 84 lines · Bin Meng

Hi Simon,

Quoted 72 lines · Simon Glass

Hi Bin,

Quoted 69 lines · Bin Meng

Hi Andrew,

Quoted 54 lines · Andrew Bradford

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 6 lines

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

OK, my test shows that ehci works fine in U-Boot on Bayley Bay.

Hi Simon,

Quoted 8 lines

Quoted 1 line

What do you think regarding to xhci vs. ehci in U-Boot?

The problem is that USB is then broken in U-Boot. I think it is better to limit the speed for the moment until we have that fixed. It is quite useful to be able to use a keyboard or USB stick in U-Boot.

With my testing the bottom (blue) port works fine but the top port does not. This happens regardless of the xhci setting.

Quoted 6 lines

There are 3 ports on Intel Bayley Bay. One USB 3 (blue port) and two USB 2 ports. The board user guide explicitly mentions that the top USB 2 port does not work and needs PCB rework. For the other two ports, I've tested U-Boot EHCI stack and it works fine. Interesting to hear that MinnowMax also has some USB port issue. Maybe the board design is following Bayley Bay.

Maybe.

Quoted 7 lines

Quoted 4 lines

So overall I think we are in a better position to go with ehci for now, i.e. drop the fsp,enable-xhci property.

OK, then could you please remove this for Bayley Bay as well? Also I think we need remove the MRC debug output as well.

Yes will do.

Quoted 6 lines

Quoted 5 lines

I think there is a little tweak needed to support both ports, but I haven't dug into it yet.

Quoted 2 lines

This is not possible. According to Intel E3800 datasheet, the xHCI and EHCI are mutually exclusive. We can either use xHCI, or EHCI.

I believe you can put the ports into a mode where both work, although presumablly they are both either EHCI or xHCI. When I boot UEFI both ports work.

Hi Simon,

Quoted 115 lines · Simon Glass

Hi Bin,

Quoted 84 lines · Bin Meng

Hi Simon,

Quoted 72 lines · Simon Glass

Hi Bin,

Quoted 69 lines · Bin Meng

Hi Andrew,

Quoted 54 lines · Andrew Bradford

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 6 lines

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

OK, my test shows that ehci works fine in U-Boot on Bayley Bay.

Hi Simon,

Quoted 8 lines

Quoted 1 line

What do you think regarding to xhci vs. ehci in U-Boot?

The problem is that USB is then broken in U-Boot. I think it is better to limit the speed for the moment until we have that fixed. It is quite useful to be able to use a keyboard or USB stick in U-Boot.

With my testing the bottom (blue) port works fine but the top port does not. This happens regardless of the xhci setting.

Quoted 6 lines

There are 3 ports on Intel Bayley Bay. One USB 3 (blue port) and two USB 2 ports. The board user guide explicitly mentions that the top USB 2 port does not work and needs PCB rework. For the other two ports, I've tested U-Boot EHCI stack and it works fine. Interesting to hear that MinnowMax also has some USB port issue. Maybe the board design is following Bayley Bay.

Maybe.

Quoted 7 lines

Quoted 4 lines

So overall I think we are in a better position to go with ehci for now, i.e. drop the fsp,enable-xhci property.

OK, then could you please remove this for Bayley Bay as well? Also I think we need remove the MRC debug output as well.

Yes will do.

Quoted 8 lines

Quoted 5 lines

I think there is a little tweak needed to support both ports, but I haven't dug into it yet.

This is not possible. According to Intel E3800 datasheet, the xHCI and EHCI are mutually exclusive. We can either use xHCI, or EHCI.

Quoted 4 lines

I believe you can put the ports into a mode where both work, although presumablly they are both either EHCI or xHCI. When I boot UEFI both ports work.

Yep, that's what I meant. When using EHCI the USB 3 port will function as a USB 2 port and when using xHCI the USB 2 port will only get high speed.

Hi Bin,

Quoted 118 lines · Bin Meng

Hi Simon,

Quoted 115 lines · Simon Glass

Hi Bin,

Quoted 84 lines · Bin Meng

Hi Simon,

Quoted 72 lines · Simon Glass

Hi Bin,

Quoted 69 lines · Bin Meng

Hi Andrew,

Quoted 54 lines · Andrew Bradford

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 6 lines

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

OK, my test shows that ehci works fine in U-Boot on Bayley Bay.

Hi Simon,

Quoted 8 lines

Quoted 1 line

What do you think regarding to xhci vs. ehci in U-Boot?

The problem is that USB is then broken in U-Boot. I think it is better to limit the speed for the moment until we have that fixed. It is quite useful to be able to use a keyboard or USB stick in U-Boot.

With my testing the bottom (blue) port works fine but the top port does not. This happens regardless of the xhci setting.

Quoted 6 lines

There are 3 ports on Intel Bayley Bay. One USB 3 (blue port) and two USB 2 ports. The board user guide explicitly mentions that the top USB 2 port does not work and needs PCB rework. For the other two ports, I've tested U-Boot EHCI stack and it works fine. Interesting to hear that MinnowMax also has some USB port issue. Maybe the board design is following Bayley Bay.

Maybe.

Quoted 7 lines

Quoted 4 lines

So overall I think we are in a better position to go with ehci for now, i.e. drop the fsp,enable-xhci property.

OK, then could you please remove this for Bayley Bay as well? Also I think we need remove the MRC debug output as well.

Yes will do.

Quoted 8 lines

Quoted 5 lines

I think there is a little tweak needed to support both ports, but I haven't dug into it yet.

This is not possible. According to Intel E3800 datasheet, the xHCI and EHCI are mutually exclusive. We can either use xHCI, or EHCI.

Quoted 8 lines

Quoted 4 lines

I believe you can put the ports into a mode where both work, although presumablly they are both either EHCI or xHCI. When I boot UEFI both ports work.

Yep, that's what I meant. When using EHCI the USB 3 port will function as a USB 2 port and when using xHCI the USB 2 port will only get high speed.

Ah I see.

I fixed these up and also some 80col problems. Please let me know if anything is wrong.

Applied to u-boot-x86.

Hi Bin,

Quoted 69 lines · Bin Meng

Hi Andrew,

Quoted 54 lines · Andrew Bradford

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 6 lines

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

OK, my test shows that ehci works fine in U-Boot on Bayley Bay.

Hi Simon,

Quoted 1 line

What do you think regarding to xhci vs. ehci in U-Boot?

The problem is that USB is then broken in U-Boot. I think it is better to limit the speed for the moment until we have that fixed. It is quite useful to be able to use a keyboard or USB stick in U-Boot.

With my testing the bottom (blue) port works fine but the top port does not. This happens regardless of the xhci setting.

So overall I think we are in a better position to go with ehci for now, i.e. drop the fsp,enable-xhci property.

Hi Simon,

Quoted 72 lines · Simon Glass

Hi Bin,

Quoted 69 lines · Bin Meng

Hi Andrew,

Quoted 54 lines · Andrew Bradford

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 6 lines

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

OK, my test shows that ehci works fine in U-Boot on Bayley Bay.

Hi Simon,

Quoted 8 lines

Quoted 1 line

What do you think regarding to xhci vs. ehci in U-Boot?

The problem is that USB is then broken in U-Boot. I think it is better to limit the speed for the moment until we have that fixed. It is quite useful to be able to use a keyboard or USB stick in U-Boot.

With my testing the bottom (blue) port works fine but the top port does not. This happens regardless of the xhci setting.

Minnowmax has a USB power switch enable which determines if the VBUS2 net is turned on or not, which will supply or not supply power to the USB 2.0 port. The blue USB 3.0 port also has an enable. Both enables and the USB ports themselves are located on page 16 of the schematic that I have.

The switches to enable the VBUS for each port are active high and pulled down. So to turn them on, I believe that's the point of the pinmuxing and GPIO settings which are used in the minnowmax.dts. Can you verify if these are correctly turning on VBUS2 (since it sounds like they are turning on VBUS1)? If not, when you turn these GPIO on manually, does the USB 2.0 port work correctly?

Quoted 3 lines

So overall I think we are in a better position to go with ehci for now, i.e. drop the fsp,enable-xhci property.

OK, sounds good!

Thanks!
-Andrew

Hi Andrew,

Quoted 90 lines · Andrew Bradford

Hi Simon,

Quoted 72 lines · Simon Glass

Hi Bin,

Quoted 69 lines · Bin Meng

Hi Andrew,

Quoted 54 lines · Andrew Bradford

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 6 lines

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

OK, my test shows that ehci works fine in U-Boot on Bayley Bay.

Hi Simon,

Quoted 8 lines

Quoted 1 line

What do you think regarding to xhci vs. ehci in U-Boot?

The problem is that USB is then broken in U-Boot. I think it is better to limit the speed for the moment until we have that fixed. It is quite useful to be able to use a keyboard or USB stick in U-Boot.

With my testing the bottom (blue) port works fine but the top port does not. This happens regardless of the xhci setting.

Minnowmax has a USB power switch enable which determines if the VBUS2 net is turned on or not, which will supply or not supply power to the USB 2.0 port. The blue USB 3.0 port also has an enable. Both enables and the USB ports themselves are located on page 16 of the schematic that I have.

Quoted 6 lines

The switches to enable the VBUS for each port are active high and pulled down. So to turn them on, I believe that's the point of the pinmuxing and GPIO settings which are used in the minnowmax.dts. Can you verify if these are correctly turning on VBUS2 (since it sounds like they are turning on VBUS1)? If not, when you turn these GPIO on manually, does the USB 2.0 port work correctly?

I see power on the bottom port but not the top one.

Hi Simon,

Quoted 93 lines · Simon Glass

Hi Andrew,

Quoted 90 lines · Andrew Bradford

Hi Simon,

Quoted 72 lines · Simon Glass

Hi Bin,

Quoted 69 lines · Bin Meng

Hi Andrew,

Quoted 54 lines · Andrew Bradford

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 6 lines

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

OK, my test shows that ehci works fine in U-Boot on Bayley Bay.

Hi Simon,

Quoted 8 lines

Quoted 1 line

What do you think regarding to xhci vs. ehci in U-Boot?

The problem is that USB is then broken in U-Boot. I think it is better to limit the speed for the moment until we have that fixed. It is quite useful to be able to use a keyboard or USB stick in U-Boot.

With my testing the bottom (blue) port works fine but the top port does not. This happens regardless of the xhci setting.

Minnowmax has a USB power switch enable which determines if the VBUS2 net is turned on or not, which will supply or not supply power to the USB 2.0 port. The blue USB 3.0 port also has an enable. Both enables and the USB ports themselves are located on page 16 of the schematic that I have.

Quoted 8 lines

Quoted 6 lines

The switches to enable the VBUS for each port are active high and pulled down. So to turn them on, I believe that's the point of the pinmuxing and GPIO settings which are used in the minnowmax.dts. Can you verify if these are correctly turning on VBUS2 (since it sounds like they are turning on VBUS1)? If not, when you turn these GPIO on manually, does the USB 2.0 port work correctly?

I see power on the bottom port but not the top one.

OK, that's odd, but likely can be fixed with changes to the pin mux and pad settings in the dts. I believe that the "pad-offset" for pin_usb_host_en1 at 0 is wrong and that it should be 0x250 instead of 0x258.

arch/x86/dts/minnowmax.dts +1 -1

index d0c0fe6..4988163 100644
@@ -39,7 +39,7 @@
 
                pin_usb_host_en1 at 0 {
                        gpio-offset = <0x80 9>;
-                       pad-offset = <0x258>;
+                       pad-offset = <0x250>;
                        mode-gpio;
                        output-value = <1>;
                        direction = <PIN_OUTPUT>;

Does that fix it?

+Gabriel

Hi Andrew,

Quoted 124 lines · Andrew Bradford

Hi Simon,

Quoted 93 lines · Simon Glass

Hi Andrew,

Quoted 90 lines · Andrew Bradford

Hi Simon,

Quoted 72 lines · Simon Glass

Hi Bin,

Quoted 69 lines · Bin Meng

Hi Andrew,

Quoted 54 lines · Andrew Bradford

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 6 lines

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

OK, my test shows that ehci works fine in U-Boot on Bayley Bay.

Hi Simon,

Quoted 8 lines

Quoted 1 line

What do you think regarding to xhci vs. ehci in U-Boot?

The problem is that USB is then broken in U-Boot. I think it is better to limit the speed for the moment until we have that fixed. It is quite useful to be able to use a keyboard or USB stick in U-Boot.

With my testing the bottom (blue) port works fine but the top port does not. This happens regardless of the xhci setting.

Minnowmax has a USB power switch enable which determines if the VBUS2 net is turned on or not, which will supply or not supply power to the USB 2.0 port. The blue USB 3.0 port also has an enable. Both enables and the USB ports themselves are located on page 16 of the schematic that I have.

Quoted 8 lines

Quoted 6 lines

The switches to enable the VBUS for each port are active high and pulled down. So to turn them on, I believe that's the point of the pinmuxing and GPIO settings which are used in the minnowmax.dts. Can you verify if these are correctly turning on VBUS2 (since it sounds like they are turning on VBUS1)? If not, when you turn these GPIO on manually, does the USB 2.0 port work correctly?

I see power on the bottom port but not the top one.

OK, that's odd, but likely can be fixed with changes to the pin mux and pad settings in the dts. I believe that the "pad-offset" for pin_usb_host_en1 at 0 is wrong and that it should be 0x250 instead of 0x258.

arch/x86/dts/minnowmax.dts +1 -1

index d0c0fe6..4988163 100644
@@ -39,7 +39,7 @@
 
                pin_usb_host_en1 at 0 {
                        gpio-offset = <0x80 9>;
-                       pad-offset = <0x258>;
+                       pad-offset = <0x250>;
                        mode-gpio;
                        output-value = <1>;
                        direction = <PIN_OUTPUT>;

Quoted 1 line

Does that fix it?

I dug into this a bit and it all seems quite broken:

- PCI bus configuration does not work in gpio_ich6_pinctrl_init(). I will send a patch for this
- gpio_ich6_get_base() returns a 16-bit word but function is also used to read the memory address which holds a 32-bit word
- Intel's hardware won't let you read the status of an output!

The last point means that _gpio_ich6_pinctrl_cfg_pin cannot work. We need to mirror the lvl register in order to be able to read it.

I confirmed that with the 'correct' value in the lvl registers both USB ports work.

Hi Simon,

Quoted 133 lines · Simon Glass

+Gabriel

Hi Andrew,

Quoted 124 lines · Andrew Bradford

Hi Simon,

Quoted 93 lines · Simon Glass

Hi Andrew,

Quoted 90 lines · Andrew Bradford

Hi Simon,

Quoted 72 lines · Simon Glass

Hi Bin,

Quoted 69 lines · Bin Meng

Hi Andrew,

Quoted 54 lines · Andrew Bradford

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
settings from the Intel FSPv4 Gold release to the respective dts files,
with the condition that the memory-down parameters for MinnowMax are
also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by: Andrew Bradford <[email protected]>
---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 6 lines

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

OK, my test shows that ehci works fine in U-Boot on Bayley Bay.

Hi Simon,

Quoted 8 lines

Quoted 1 line

What do you think regarding to xhci vs. ehci in U-Boot?

The problem is that USB is then broken in U-Boot. I think it is better to limit the speed for the moment until we have that fixed. It is quite useful to be able to use a keyboard or USB stick in U-Boot.

With my testing the bottom (blue) port works fine but the top port does not. This happens regardless of the xhci setting.

Minnowmax has a USB power switch enable which determines if the VBUS2 net is turned on or not, which will supply or not supply power to the USB 2.0 port. The blue USB 3.0 port also has an enable. Both enables and the USB ports themselves are located on page 16 of the schematic that I have.

Quoted 8 lines

Quoted 6 lines

The switches to enable the VBUS for each port are active high and pulled down. So to turn them on, I believe that's the point of the pinmuxing and GPIO settings which are used in the minnowmax.dts. Can you verify if these are correctly turning on VBUS2 (since it sounds like they are turning on VBUS1)? If not, when you turn these GPIO on manually, does the USB 2.0 port work correctly?

I see power on the bottom port but not the top one.

OK, that's odd, but likely can be fixed with changes to the pin mux and pad settings in the dts. I believe that the "pad-offset" for pin_usb_host_en1 at 0 is wrong and that it should be 0x250 instead of 0x258.

arch/x86/dts/minnowmax.dts +1 -1

index d0c0fe6..4988163 100644
@@ -39,7 +39,7 @@
 
                pin_usb_host_en1 at 0 {
                        gpio-offset = <0x80 9>;
-                       pad-offset = <0x258>;
+                       pad-offset = <0x250>;
                        mode-gpio;
                        output-value = <1>;
                        direction = <PIN_OUTPUT>;

Quoted 1 line

Does that fix it?

I dug into this a bit and it all seems quite broken:

Quoted 5 lines

- PCI bus configuration does not work in gpio_ich6_pinctrl_init(). I will send a patch for this
- gpio_ich6_get_base() returns a 16-bit word but function is also used to read the memory address which holds a 32-bit word
- Intel's hardware won't let you read the status of an output!

I thought that if you cleared bit 2 in the "pad value" register (iinenb) for a GPIO that you could read back outputs. Or am I misunderstanding?

Quoted 6 lines

The last point means that _gpio_ich6_pinctrl_cfg_pin cannot work. We need to mirror the lvl register in order to be able to read it.

I confirmed that with the 'correct' value in the lvl registers both USB ports work.

OK, well that's good at least.

Thanks,
Andrew

+Gabriel

Hi Andrew,

Quoted 124 lines · Andrew Bradford

Hi Simon,

Quoted 93 lines · Simon Glass

Hi Andrew,

Quoted 90 lines · Andrew Bradford

Hi Simon,

Quoted 72 lines · Simon Glass

Hi Bin,

Quoted 69 lines · Bin Meng

Hi Andrew,

Quoted 54 lines · Andrew Bradford

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 6 lines

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

OK, my test shows that ehci works fine in U-Boot on Bayley Bay.

Hi Simon,

Quoted 8 lines

Quoted 1 line

What do you think regarding to xhci vs. ehci in U-Boot?

The problem is that USB is then broken in U-Boot. I think it is better to limit the speed for the moment until we have that fixed. It is quite useful to be able to use a keyboard or USB stick in U-Boot.

With my testing the bottom (blue) port works fine but the top port does not. This happens regardless of the xhci setting.

Minnowmax has a USB power switch enable which determines if the VBUS2 net is turned on or not, which will supply or not supply power to the USB 2.0 port. The blue USB 3.0 port also has an enable. Both enables and the USB ports themselves are located on page 16 of the schematic that I have.

Quoted 8 lines

Quoted 6 lines

The switches to enable the VBUS for each port are active high and pulled down. So to turn them on, I believe that's the point of the pinmuxing and GPIO settings which are used in the minnowmax.dts. Can you verify if these are correctly turning on VBUS2 (since it sounds like they are turning on VBUS1)? If not, when you turn these GPIO on manually, does the USB 2.0 port work correctly?

I see power on the bottom port but not the top one.

OK, that's odd, but likely can be fixed with changes to the pin mux and pad settings in the dts. I believe that the "pad-offset" for pin_usb_host_en1 at 0 is wrong and that it should be 0x250 instead of 0x258.

arch/x86/dts/minnowmax.dts +1 -1

index d0c0fe6..4988163 100644
@@ -39,7 +39,7 @@
 
                pin_usb_host_en1 at 0 {
                        gpio-offset = <0x80 9>;
-                       pad-offset = <0x258>;
+                       pad-offset = <0x250>;
                        mode-gpio;
                        output-value = <1>;
                        direction = <PIN_OUTPUT>;

Quoted 1 line

Does that fix it?

I dug into this a bit and it all seems quite broken:

- PCI bus configuration does not work in gpio_ich6_pinctrl_init(). I will send a patch for this

- gpio_ich6_get_base() returns a 16-bit word but function is also used to read the memory address which holds a 32-bit word
- Intel's hardware won't let you read the status of an output!

The last point means that _gpio_ich6_pinctrl_cfg_pin cannot work. We need to mirror the lvl register in order to be able to read it.

I confirmed that with the 'correct' value in the lvl registers both USB ports work.

+Gabriel

Hi Andrew,

Quoted 124 lines · Andrew Bradford

Hi Simon,

Quoted 93 lines · Simon Glass

Hi Andrew,

Quoted 90 lines · Andrew Bradford

Hi Simon,

Quoted 72 lines · Simon Glass

Hi Bin,

Quoted 69 lines · Bin Meng

Hi Andrew,

Quoted 54 lines · Andrew Bradford

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 6 lines

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

OK, my test shows that ehci works fine in U-Boot on Bayley Bay.

Hi Simon,

Quoted 8 lines

Quoted 1 line

What do you think regarding to xhci vs. ehci in U-Boot?

The problem is that USB is then broken in U-Boot. I think it is better to limit the speed for the moment until we have that fixed. It is quite useful to be able to use a keyboard or USB stick in U-Boot.

With my testing the bottom (blue) port works fine but the top port does not. This happens regardless of the xhci setting.

Minnowmax has a USB power switch enable which determines if the VBUS2 net is turned on or not, which will supply or not supply power to the USB 2.0 port. The blue USB 3.0 port also has an enable. Both enables and the USB ports themselves are located on page 16 of the schematic that I have.

Quoted 8 lines

Quoted 6 lines

The switches to enable the VBUS for each port are active high and pulled down. So to turn them on, I believe that's the point of the pinmuxing and GPIO settings which are used in the minnowmax.dts. Can you verify if these are correctly turning on VBUS2 (since it sounds like they are turning on VBUS1)? If not, when you turn these GPIO on manually, does the USB 2.0 port work correctly?

I see power on the bottom port but not the top one.

OK, that's odd, but likely can be fixed with changes to the pin mux and pad settings in the dts. I believe that the "pad-offset" for pin_usb_host_en1 at 0 is wrong and that it should be 0x250 instead of 0x258.

arch/x86/dts/minnowmax.dts +1 -1

index d0c0fe6..4988163 100644
@@ -39,7 +39,7 @@
 
                 pin_usb_host_en1 at 0 {
                         gpio-offset = <0x80 9>;
-                       pad-offset = <0x258>;
+                       pad-offset = <0x250>;
                         mode-gpio;
                         output-value = <1>;
                         direction = <PIN_OUTPUT>;

Quoted 1 line

Does that fix it?

I dug into this a bit and it all seems quite broken:

- PCI bus configuration does not work in gpio_ich6_pinctrl_init(). I will send a patch for this
- gpio_ich6_get_base() returns a 16-bit word but function is also used to read the memory address which holds a 32-bit word
- Intel's hardware won't let you read the status of an output!

The last point means that _gpio_ich6_pinctrl_cfg_pin cannot work. We need to mirror the lvl register in order to be able to read it.

I confirmed that with the 'correct' value in the lvl registers both USB ports work.

Hi Simon, Hi Bin,

Quoted 139 lines · Simon Glass

+Gabriel

Hi Andrew,

Quoted 124 lines · Andrew Bradford

Hi Simon,

Quoted 93 lines · Simon Glass

Hi Andrew,

Quoted 90 lines · Andrew Bradford

Hi Simon,

Quoted 72 lines · Simon Glass

Hi Bin,

Quoted 69 lines · Bin Meng

Hi Andrew,

Quoted 54 lines · Andrew Bradford

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
settings from the Intel FSPv4 Gold release to the respective dts files,
with the condition that the memory-down parameters for MinnowMax are
also used.

Quoted 7 lines

Quoted 3 lines

Signed-off-by: Andrew Bradford <[email protected]>
---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 6 lines

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

OK, my test shows that ehci works fine in U-Boot on Bayley Bay.

Hi Simon,

Quoted 8 lines

Quoted 1 line

What do you think regarding to xhci vs. ehci in U-Boot?

The problem is that USB is then broken in U-Boot. I think it is better to limit the speed for the moment until we have that fixed. It is quite useful to be able to use a keyboard or USB stick in U-Boot.

With my testing the bottom (blue) port works fine but the top port does not. This happens regardless of the xhci setting.

Minnowmax has a USB power switch enable which determines if the VBUS2 net is turned on or not, which will supply or not supply power to the USB 2.0 port. The blue USB 3.0 port also has an enable. Both enables and the USB ports themselves are located on page 16 of the schematic that I have.

Quoted 8 lines

Quoted 6 lines

The switches to enable the VBUS for each port are active high and pulled down. So to turn them on, I believe that's the point of the pinmuxing and GPIO settings which are used in the minnowmax.dts. Can you verify if these are correctly turning on VBUS2 (since it sounds like they are turning on VBUS1)? If not, when you turn these GPIO on manually, does the USB 2.0 port work correctly?

I see power on the bottom port but not the top one.

OK, that's odd, but likely can be fixed with changes to the pin mux and pad settings in the dts. I believe that the "pad-offset" for pin_usb_host_en1 at 0 is wrong and that it should be 0x250 instead of 0x258.

arch/x86/dts/minnowmax.dts +1 -1

index d0c0fe6..4988163 100644
@@ -39,7 +39,7 @@
 
                 pin_usb_host_en1 at 0 {
                         gpio-offset = <0x80 9>;
-                       pad-offset = <0x258>;
+                       pad-offset = <0x250>;
                         mode-gpio;
                         output-value = <1>;
                         direction = <PIN_OUTPUT>;

Quoted 1 line

Does that fix it?

I dug into this a bit and it all seems quite broken:

- PCI bus configuration does not work in gpio_ich6_pinctrl_init(). I will send a patch for this
- gpio_ich6_get_base() returns a 16-bit word but function is also used to read the memory address which holds a 32-bit word
- Intel's hardware won't let you read the status of an output!

Quoted 5 lines

The last point means that _gpio_ich6_pinctrl_cfg_pin cannot work. We need to mirror the lvl register in order to be able to read it.

I confirmed that with the 'correct' value in the lvl registers both USB ports work.

I'm currently struggling with the USB EHCI ports on my custom Bay Trail x86 board. With the current U-Boot, cloned from the MinnowMAX, only some of the USB EHCI ports are enabled / available. Here the "usb tree" output with 3 USB keys installed:

=> usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)
| u-boot EHCI Host Controller
|

  +-2  Hub (480 Mb/s, 0mA)
    |
    +-3  Hub (480 Mb/s, 100mA)
    | |
    | +-4  Hub (12 Mb/s, 100mA)
    |
    +-5  Mass Storage (480 Mb/s, 200mA)
         JetFlash Mass Storage Device 3281440601

When I first start the original (AMI) BIOS on this custom board, and then reboot into U-Boot (without a power-cycle), I see this configuration:

=> usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)
| u-boot EHCI Host Controller
|

  +-2  Hub (480 Mb/s, 0mA)
    |
    +-3  Hub (480 Mb/s, 100mA)
    | |
    | +-4  Hub (12 Mb/s, 100mA)
    |
    +-5  Hub (480 Mb/s, 0mA)
    | |
    | +-6  Mass Storage (480 Mb/s, 200mA)
    | |    Kingston DataTraveler 2.0 50E549C688C4BE7189942766
    | |
    | +-7  Mass Storage (480 Mb/s, 98mA)
    |      USBest Technology USB Mass Storage Device 09092207fbf0c4
    |
    +-8  Mass Storage (480 Mb/s, 200mA)
         JetFlash Mass Storage Device 3281440601

So now all 3 USB sticks are detected.

It doesn't seem to be a problem with missing USB power switch enabling via some GPIOs. I've checked the schematics and all ports should have power enabled.

Do you have any quick ideas, what might be missing to enable all 4 EHCI ports on Bay Trail? There seems to be a per-port disable feature which might be involved. I'm still pretty new to x86, and I'm struggling with finding the correct datasheet for this. So any hints are really appreciated.

Hi Stefan,

Quoted 199 lines · Stefan Roese

Hi Simon, Hi Bin,

Quoted 139 lines · Simon Glass

+Gabriel

Hi Andrew,

Quoted 124 lines · Andrew Bradford

Hi Simon,

Quoted 93 lines · Simon Glass

Hi Andrew,

Quoted 90 lines · Andrew Bradford

Hi Simon,

Quoted 72 lines · Simon Glass

Hi Bin,

Quoted 69 lines · Bin Meng

Hi Andrew,

Quoted 54 lines · Andrew Bradford

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 19 lines · Bin Meng

On Fri, Aug 7, 2015 at 8:36 PM, Andrew Bradford
<[email protected]> wrote:
From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
settings from the Intel FSPv4 Gold release to the respective dts files,
with the condition that the memory-down parameters for MinnowMax are
also used.

Signed-off-by: Andrew Bradford <[email protected]>
---

Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

Quoted 7 lines

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 6 lines

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

OK, my test shows that ehci works fine in U-Boot on Bayley Bay.

Hi Simon,

Quoted 8 lines

Quoted 1 line

What do you think regarding to xhci vs. ehci in U-Boot?

The problem is that USB is then broken in U-Boot. I think it is better to limit the speed for the moment until we have that fixed. It is quite useful to be able to use a keyboard or USB stick in U-Boot.

With my testing the bottom (blue) port works fine but the top port does not. This happens regardless of the xhci setting.

Minnowmax has a USB power switch enable which determines if the VBUS2 net is turned on or not, which will supply or not supply power to the USB 2.0 port. The blue USB 3.0 port also has an enable. Both enables and the USB ports themselves are located on page 16 of the schematic that I have.

Quoted 8 lines

Quoted 6 lines

The switches to enable the VBUS for each port are active high and pulled down. So to turn them on, I believe that's the point of the pinmuxing and GPIO settings which are used in the minnowmax.dts. Can you verify if these are correctly turning on VBUS2 (since it sounds like they are turning on VBUS1)? If not, when you turn these GPIO on manually, does the USB 2.0 port work correctly?

I see power on the bottom port but not the top one.

OK, that's odd, but likely can be fixed with changes to the pin mux and pad settings in the dts. I believe that the "pad-offset" for pin_usb_host_en1 at 0 is wrong and that it should be 0x250 instead of 0x258.

arch/x86/dts/minnowmax.dts +1 -1

index d0c0fe6..4988163 100644
@@ -39,7 +39,7 @@
 
                  pin_usb_host_en1 at 0 {
                          gpio-offset = <0x80 9>;
-                       pad-offset = <0x258>;
+                       pad-offset = <0x250>;
                          mode-gpio;
                          output-value = <1>;
                          direction = <PIN_OUTPUT>;

Quoted 1 line

Does that fix it?

I dug into this a bit and it all seems quite broken:

- PCI bus configuration does not work in gpio_ich6_pinctrl_init(). I will send a patch for this
- gpio_ich6_get_base() returns a 16-bit word but function is also used to read the memory address which holds a 32-bit word
- Intel's hardware won't let you read the status of an output!

Quoted 5 lines

The last point means that _gpio_ich6_pinctrl_cfg_pin cannot work. We need to mirror the lvl register in order to be able to read it.

I confirmed that with the 'correct' value in the lvl registers both USB ports work.

I'm currently struggling with the USB EHCI ports on my custom Bay Trail x86 board. With the current U-Boot, cloned from the MinnowMAX, only some of the USB EHCI ports are enabled / available. Here the "usb tree" output with 3 USB keys installed:

=> usb tree
USB device tree:

   1  Hub (480 Mb/s, 0mA)
   |  u-boot EHCI Host Controller
   |
   +-2  Hub (480 Mb/s, 0mA)
     |
     +-3  Hub (480 Mb/s, 100mA)
     | |
     | +-4  Hub (12 Mb/s, 100mA)
     |
     +-5  Mass Storage (480 Mb/s, 200mA)
          JetFlash Mass Storage Device 3281440601

When I first start the original (AMI) BIOS on this custom board, and then reboot into U-Boot (without a power-cycle), I see this configuration:

=> usb tree
USB device tree:

   1  Hub (480 Mb/s, 0mA)
   |  u-boot EHCI Host Controller
   |
   +-2  Hub (480 Mb/s, 0mA)
     |
     +-3  Hub (480 Mb/s, 100mA)
     | |
     | +-4  Hub (12 Mb/s, 100mA)
     |
     +-5  Hub (480 Mb/s, 0mA)
     | |
     | +-6  Mass Storage (480 Mb/s, 200mA)
     | |    Kingston DataTraveler 2.0 50E549C688C4BE7189942766
     | |
     | +-7  Mass Storage (480 Mb/s, 98mA)
     |      USBest Technology USB Mass Storage Device 09092207fbf0c4
     |
     +-8  Mass Storage (480 Mb/s, 200mA)
          JetFlash Mass Storage Device 3281440601

So now all 3 USB sticks are detected.

It doesn't seem to be a problem with missing USB power switch enabling via some GPIOs. I've checked the schematics and all ports should have power enabled.

Quoted 5 lines

Do you have any quick ideas, what might be missing to enable all 4 EHCI ports on Bay Trail? There seems to be a per-port disable feature which might be involved. I'm still pretty new to x86, and I'm struggling with finding the correct datasheet for this. So any hints are really appreciated.

It might be worth checking the pci bus device list in both cases. Perhaps one of the USB ports is disabled?

Hi Simon,

Quoted 202 lines · Simon Glass

Hi Stefan,

Quoted 199 lines · Stefan Roese

Hi Simon, Hi Bin,

Quoted 139 lines · Simon Glass

+Gabriel

Hi Andrew,

Quoted 124 lines · Andrew Bradford

Hi Simon,

Quoted 93 lines · Simon Glass

Hi Andrew,

Quoted 90 lines · Andrew Bradford

Hi Simon,

Quoted 72 lines · Simon Glass

Hi Bin,

Quoted 69 lines · Bin Meng

Hi Andrew,

Quoted 54 lines · Andrew Bradford

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 36 lines · Simon Glass

Hi,

On 7 August 2015 at 06:44, Bin Meng <[email protected]> wrote:
On Fri, Aug 7, 2015 at 8:36 PM, Andrew Bradford
<[email protected]> wrote:
From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
settings from the Intel FSPv4 Gold release to the respective dts files,
with the condition that the memory-down parameters for MinnowMax are
also used.

Signed-off-by: Andrew Bradford <[email protected]>
---

Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>

Acked-by: Simon Glass <[email protected]>
Tested on minnowmax:
Tested-by: Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

- fsp,enable-xhci needs to be removed as this does not work in U-Boot
at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information
being displayed

I plan to apply this with these changes - please let me know if this
doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

Quoted 6 lines

Quoted 2 lines

Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

OK, my test shows that ehci works fine in U-Boot on Bayley Bay.

Hi Simon,

Quoted 8 lines

Quoted 1 line

What do you think regarding to xhci vs. ehci in U-Boot?

The problem is that USB is then broken in U-Boot. I think it is better to limit the speed for the moment until we have that fixed. It is quite useful to be able to use a keyboard or USB stick in U-Boot.

With my testing the bottom (blue) port works fine but the top port does not. This happens regardless of the xhci setting.

Minnowmax has a USB power switch enable which determines if the VBUS2 net is turned on or not, which will supply or not supply power to the USB 2.0 port. The blue USB 3.0 port also has an enable. Both enables and the USB ports themselves are located on page 16 of the schematic that I have.

Quoted 8 lines

Quoted 6 lines

The switches to enable the VBUS for each port are active high and pulled down. So to turn them on, I believe that's the point of the pinmuxing and GPIO settings which are used in the minnowmax.dts. Can you verify if these are correctly turning on VBUS2 (since it sounds like they are turning on VBUS1)? If not, when you turn these GPIO on manually, does the USB 2.0 port work correctly?

I see power on the bottom port but not the top one.

OK, that's odd, but likely can be fixed with changes to the pin mux and pad settings in the dts. I believe that the "pad-offset" for pin_usb_host_en1 at 0 is wrong and that it should be 0x250 instead of 0x258.

arch/x86/dts/minnowmax.dts +1 -1

index d0c0fe6..4988163 100644
@@ -39,7 +39,7 @@
 
                  pin_usb_host_en1 at 0 {
                          gpio-offset = <0x80 9>;
-                       pad-offset = <0x258>;
+                       pad-offset = <0x250>;
                          mode-gpio;
                          output-value = <1>;
                          direction = <PIN_OUTPUT>;

Quoted 1 line

Does that fix it?

I dug into this a bit and it all seems quite broken:

- PCI bus configuration does not work in gpio_ich6_pinctrl_init(). I will send a patch for this
- gpio_ich6_get_base() returns a 16-bit word but function is also used to read the memory address which holds a 32-bit word
- Intel's hardware won't let you read the status of an output!

Quoted 5 lines

The last point means that _gpio_ich6_pinctrl_cfg_pin cannot work. We need to mirror the lvl register in order to be able to read it.

I confirmed that with the 'correct' value in the lvl registers both USB ports work.

I'm currently struggling with the USB EHCI ports on my custom Bay Trail x86 board. With the current U-Boot, cloned from the MinnowMAX, only some of the USB EHCI ports are enabled / available. Here the "usb tree" output with 3 USB keys installed:

=> usb tree
USB device tree:

   1  Hub (480 Mb/s, 0mA)
   |  u-boot EHCI Host Controller
   |
   +-2  Hub (480 Mb/s, 0mA)
     |
     +-3  Hub (480 Mb/s, 100mA)
     | |
     | +-4  Hub (12 Mb/s, 100mA)
     |
     +-5  Mass Storage (480 Mb/s, 200mA)
          JetFlash Mass Storage Device 3281440601

When I first start the original (AMI) BIOS on this custom board, and then reboot into U-Boot (without a power-cycle), I see this configuration:

=> usb tree
USB device tree:

   1  Hub (480 Mb/s, 0mA)
   |  u-boot EHCI Host Controller
   |
   +-2  Hub (480 Mb/s, 0mA)
     |
     +-3  Hub (480 Mb/s, 100mA)
     | |
     | +-4  Hub (12 Mb/s, 100mA)
     |
     +-5  Hub (480 Mb/s, 0mA)
     | |
     | +-6  Mass Storage (480 Mb/s, 200mA)
     | |    Kingston DataTraveler 2.0 50E549C688C4BE7189942766
     | |
     | +-7  Mass Storage (480 Mb/s, 98mA)
     |      USBest Technology USB Mass Storage Device 09092207fbf0c4
     |
     +-8  Mass Storage (480 Mb/s, 200mA)
          JetFlash Mass Storage Device 3281440601

So now all 3 USB sticks are detected.

It doesn't seem to be a problem with missing USB power switch enabling via some GPIOs. I've checked the schematics and all ports should have power enabled.

Quoted 8 lines

Quoted 5 lines

Do you have any quick ideas, what might be missing to enable all 4 EHCI ports on Bay Trail? There seems to be a per-port disable feature which might be involved. I'm still pretty new to x86, and I'm struggling with finding the correct datasheet for this. So any hints are really appreciated.

It might be worth checking the pci bus device list in both cases. Perhaps one of the USB ports is disabled?

IIUTC, its only one PCI device, that handles all EHCI USB 2.0 ports. In both cases its this output:

=> pci
Scanning PCI devices on bus 0
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________

00.1f.00   0x8086     0x0f1c     Bridge device           0x01
00.00.00   0x8086     0x0f00     Bridge device           0x00
00.02.00   0x8086     0x0f31     Display controller      0x00
00.11.00   0x8086     0x0f15     Base system peripheral  0x05
00.12.00   0x8086     0x0f16     Base system peripheral  0x05
00.13.00   0x8086     0x0f23     Mass storage controller 0x06
00.15.00   0x8086     0x0f28     Multimedia device       0x01
00.18.00   0x8086     0x0f40     Base system peripheral  0x01
00.18.01   0x8086     0x0f41     Serial bus controller   0x80
00.18.02   0x8086     0x0f42     Serial bus controller   0x80
00.18.03   0x8086     0x0f43     Serial bus controller   0x80
00.18.04   0x8086     0x0f44     Serial bus controller   0x80
00.18.05   0x8086     0x0f45     Serial bus controller   0x80
00.18.06   0x8086     0x0f46     Serial bus controller   0x80
00.18.07   0x8086     0x0f47     Serial bus controller   0x80
00.1a.00   0x8086     0x0f18     Cryptographic device    0x80
00.1c.00   0x8086     0x0f48     Bridge device           0x04
00.1c.03   0x8086     0x0f4e     Bridge device           0x04
00.1d.00   0x8086     0x0f34     Serial bus controller   0x03
00.1e.00   0x8086     0x0f06     Base system peripheral  0x01
00.1e.01   0x8086     0x0f08     Serial bus controller   0x80
00.1e.02   0x8086     0x0f09     Serial bus controller   0x80
00.1e.04   0x8086     0x0f0c     Simple comm. controller 0x80
00.1e.05   0x8086     0x0f0e     Serial bus controller   0x80
00.1f.03   0x8086     0x0f12     Serial bus controller   0x05

Here 00.1d.00 is the EHCI controller. The "pci long" output is also identical. So its not that simple I'm afraid.

The Intel Atom Processor Z3600 and Z3700 Series Datasheet Vol 1 mentions in chapter "10.3.1 EHCI USB 2.0 Controller Features" on page 150:

? Per port USB disable

Perhaps this feature is biting me here. I'm wondering how this can be configured.

Any further ideas are welcome.

Thanks,
Stefan

Quoted 96 lines

Quoted 51 lines

Quoted 51 lines

I'm currently struggling with the USB EHCI ports on my custom Bay Trail x86 board. With the current U-Boot, cloned from the MinnowMAX, only some of the USB EHCI ports are enabled / available. Here the "usb tree" output with 3 USB keys installed:

=> usb tree
USB device tree:

    1  Hub (480 Mb/s, 0mA)
    |  u-boot EHCI Host Controller
    |
    +-2  Hub (480 Mb/s, 0mA)
      |
      +-3  Hub (480 Mb/s, 100mA)
      | |
      | +-4  Hub (12 Mb/s, 100mA)
      |
      +-5  Mass Storage (480 Mb/s, 200mA)
           JetFlash Mass Storage Device 3281440601

When I first start the original (AMI) BIOS on this custom board, and then reboot into U-Boot (without a power-cycle), I see this configuration:

=> usb tree
USB device tree:

    1  Hub (480 Mb/s, 0mA)
    |  u-boot EHCI Host Controller
    |
    +-2  Hub (480 Mb/s, 0mA)
      |
      +-3  Hub (480 Mb/s, 100mA)
      | |
      | +-4  Hub (12 Mb/s, 100mA)
      |
      +-5  Hub (480 Mb/s, 0mA)
      | |
      | +-6  Mass Storage (480 Mb/s, 200mA)
      | |    Kingston DataTraveler 2.0 50E549C688C4BE7189942766
      | |
      | +-7  Mass Storage (480 Mb/s, 98mA)
      |      USBest Technology USB Mass Storage Device 09092207fbf0c4
      |
      +-8  Mass Storage (480 Mb/s, 200mA)
           JetFlash Mass Storage Device 3281440601

So now all 3 USB sticks are detected.

It doesn't seem to be a problem with missing USB power switch enabling via some GPIOs. I've checked the schematics and all ports should have power enabled.

Quoted 8 lines

Quoted 5 lines

Do you have any quick ideas, what might be missing to enable all 4 EHCI ports on Bay Trail? There seems to be a per-port disable feature which might be involved. I'm still pretty new to x86, and I'm struggling with finding the correct datasheet for this. So any hints are really appreciated.

It might be worth checking the pci bus device list in both cases. Perhaps one of the USB ports is disabled?

IIUTC, its only one PCI device, that handles all EHCI USB 2.0 ports. In both cases its this output:

=> pci
Scanning PCI devices on bus 0
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________

00.1f.00   0x8086     0x0f1c     Bridge device           0x01
00.00.00   0x8086     0x0f00     Bridge device           0x00
00.02.00   0x8086     0x0f31     Display controller      0x00
00.11.00   0x8086     0x0f15     Base system peripheral  0x05
00.12.00   0x8086     0x0f16     Base system peripheral  0x05
00.13.00   0x8086     0x0f23     Mass storage controller 0x06
00.15.00   0x8086     0x0f28     Multimedia device       0x01
00.18.00   0x8086     0x0f40     Base system peripheral  0x01
00.18.01   0x8086     0x0f41     Serial bus controller   0x80
00.18.02   0x8086     0x0f42     Serial bus controller   0x80
00.18.03   0x8086     0x0f43     Serial bus controller   0x80
00.18.04   0x8086     0x0f44     Serial bus controller   0x80
00.18.05   0x8086     0x0f45     Serial bus controller   0x80
00.18.06   0x8086     0x0f46     Serial bus controller   0x80
00.18.07   0x8086     0x0f47     Serial bus controller   0x80
00.1a.00   0x8086     0x0f18     Cryptographic device    0x80
00.1c.00   0x8086     0x0f48     Bridge device           0x04
00.1c.03   0x8086     0x0f4e     Bridge device           0x04
00.1d.00   0x8086     0x0f34     Serial bus controller   0x03
00.1e.00   0x8086     0x0f06     Base system peripheral  0x01
00.1e.01   0x8086     0x0f08     Serial bus controller   0x80
00.1e.02   0x8086     0x0f09     Serial bus controller   0x80
00.1e.04   0x8086     0x0f0c     Simple comm. controller 0x80
00.1e.05   0x8086     0x0f0e     Serial bus controller   0x80
00.1f.03   0x8086     0x0f12     Serial bus controller   0x05

Here 00.1d.00 is the EHCI controller. The "pci long" output is also identical. So its not that simple I'm afraid.

Quoted 8 lines

The Intel Atom Processor Z3600 and Z3700 Series Datasheet Vol 1 mentions in chapter "10.3.1 EHCI USB 2.0 Controller Features" on page 150:

? Per port USB disable

Perhaps this feature is biting me here. I'm wondering how this can be configured.

That sounds likely.

Also: xHCI and EHCI Port Mapping

suggests that you need to make sure the ports are being driven by EHCI instead of XHCI.

It mentions USB2HCSEL but I cannot find that in the datasheet.

It does appear here though:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/perf_power.c

See IOSF_PORT_0x5a here:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/broadwell_fsp/src/lib/reg_script.c

So it looks like you need to set up this port, and perhaps some others asper that file.

Hi Simon,

On 09.03.2016 00:33, Simon Glass wrote:

<snip>

Quoted 105 lines

Quoted 96 lines

Quoted 51 lines

Quoted 51 lines

I'm currently struggling with the USB EHCI ports on my custom Bay Trail x86 board. With the current U-Boot, cloned from the MinnowMAX, only some of the USB EHCI ports are enabled / available. Here the "usb tree" output with 3 USB keys installed:

=> usb tree
USB device tree:

    1  Hub (480 Mb/s, 0mA)
    |  u-boot EHCI Host Controller
    |
    +-2  Hub (480 Mb/s, 0mA)
      |
      +-3  Hub (480 Mb/s, 100mA)
      | |
      | +-4  Hub (12 Mb/s, 100mA)
      |
      +-5  Mass Storage (480 Mb/s, 200mA)
           JetFlash Mass Storage Device 3281440601

When I first start the original (AMI) BIOS on this custom board, and then reboot into U-Boot (without a power-cycle), I see this configuration:

=> usb tree
USB device tree:

    1  Hub (480 Mb/s, 0mA)
    |  u-boot EHCI Host Controller
    |
    +-2  Hub (480 Mb/s, 0mA)
      |
      +-3  Hub (480 Mb/s, 100mA)
      | |
      | +-4  Hub (12 Mb/s, 100mA)
      |
      +-5  Hub (480 Mb/s, 0mA)
      | |
      | +-6  Mass Storage (480 Mb/s, 200mA)
      | |    Kingston DataTraveler 2.0 50E549C688C4BE7189942766
      | |
      | +-7  Mass Storage (480 Mb/s, 98mA)
      |      USBest Technology USB Mass Storage Device 09092207fbf0c4
      |
      +-8  Mass Storage (480 Mb/s, 200mA)
           JetFlash Mass Storage Device 3281440601

So now all 3 USB sticks are detected.

It doesn't seem to be a problem with missing USB power switch enabling via some GPIOs. I've checked the schematics and all ports should have power enabled.

Quoted 8 lines

Quoted 5 lines

Do you have any quick ideas, what might be missing to enable all 4 EHCI ports on Bay Trail? There seems to be a per-port disable feature which might be involved. I'm still pretty new to x86, and I'm struggling with finding the correct datasheet for this. So any hints are really appreciated.

It might be worth checking the pci bus device list in both cases. Perhaps one of the USB ports is disabled?

IIUTC, its only one PCI device, that handles all EHCI USB 2.0 ports. In both cases its this output:

=> pci
Scanning PCI devices on bus 0
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________

00.1f.00   0x8086     0x0f1c     Bridge device           0x01
00.00.00   0x8086     0x0f00     Bridge device           0x00
00.02.00   0x8086     0x0f31     Display controller      0x00
00.11.00   0x8086     0x0f15     Base system peripheral  0x05
00.12.00   0x8086     0x0f16     Base system peripheral  0x05
00.13.00   0x8086     0x0f23     Mass storage controller 0x06
00.15.00   0x8086     0x0f28     Multimedia device       0x01
00.18.00   0x8086     0x0f40     Base system peripheral  0x01
00.18.01   0x8086     0x0f41     Serial bus controller   0x80
00.18.02   0x8086     0x0f42     Serial bus controller   0x80
00.18.03   0x8086     0x0f43     Serial bus controller   0x80
00.18.04   0x8086     0x0f44     Serial bus controller   0x80
00.18.05   0x8086     0x0f45     Serial bus controller   0x80
00.18.06   0x8086     0x0f46     Serial bus controller   0x80
00.18.07   0x8086     0x0f47     Serial bus controller   0x80
00.1a.00   0x8086     0x0f18     Cryptographic device    0x80
00.1c.00   0x8086     0x0f48     Bridge device           0x04
00.1c.03   0x8086     0x0f4e     Bridge device           0x04
00.1d.00   0x8086     0x0f34     Serial bus controller   0x03
00.1e.00   0x8086     0x0f06     Base system peripheral  0x01
00.1e.01   0x8086     0x0f08     Serial bus controller   0x80
00.1e.02   0x8086     0x0f09     Serial bus controller   0x80
00.1e.04   0x8086     0x0f0c     Simple comm. controller 0x80
00.1e.05   0x8086     0x0f0e     Serial bus controller   0x80
00.1f.03   0x8086     0x0f12     Serial bus controller   0x05

Here 00.1d.00 is the EHCI controller. The "pci long" output is also identical. So its not that simple I'm afraid.

Quoted 8 lines

The Intel Atom Processor Z3600 and Z3700 Series Datasheet Vol 1 mentions in chapter "10.3.1 EHCI USB 2.0 Controller Features" on page 150:

? Per port USB disable

Perhaps this feature is biting me here. I'm wondering how this can be configured.

Quoted 8 lines

That sounds likely.

Also: xHCI and EHCI Port Mapping

suggests that you need to make sure the ports are being driven by EHCI instead of XHCI.

It mentions USB2HCSEL but I cannot find that in the datasheet.

Same here.

Quoted 10 lines

It does appear here though:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/perf_power.c

See IOSF_PORT_0x5a here:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/broadwell_fsp/src/lib/reg_script.c

So it looks like you need to set up this port, and perhaps some others asper that file.

I've looked into these coreboot files today. And ported parts of them to U-Boot to run these configurations there as well. Unfortunately without any (positive) effect. Some things I've tested are:

Configure 0x5a / 0xd0 (USB2HCSEL???) to different values. All without effect.

Unfortunately this value can't be read-out. At least I read always 0 here. So I can't see, if the AMI BIOS version configures here something different.

Then I've started looking into ehci.c:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/ehci.c

EHCI_USB2PDO (per-port disable) looked promising here. And writing 0xff into this reg results in all ports disabled:

=> usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)
| u-boot EHCI Host Controller
|
+-2 Hub (480 Mb/s, 0mA)

So this register at least has some effect. But its initialized with 0 and writing 0 into it does not fix the problem with the missing ports.

I also ported the PHY values from usb2_phy_init() without any changes. The values here are the default values, as I can read them back. Also the AMI BIOS does not change these values, I've double checked this as well.

So I'm nearly out of ideas right now what else to configure / test to get all ports running. One idea is that the xHCI controller also needs some configuration for this port muxing. See:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/xhci.c:

                /* USB3 SuperSpeed Enable */
                REG_PCI_WRITE32(XHCI_USB3PR, BYTM_USB3_PORT_MAP),
                /* USB2 Port Route to XHCI */
                REG_PCI_WRITE32(XHCI_USB2PR, BYTM_USB2_PORT_MAP),

and:

                /* Set USB2 Port Routing Mask */
                REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP),
                /* Set USB3 Port Routing Mask */
                REG_PCI_WRITE32(XHCI_USB3PRM, BYTM_USB3_PORT_MAP),
                /*
                 * Disable ports if requested
                 */
                /* Open per-port disable control override */
                REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN),
                REG_PCI_WRITE32(XHCI_USB2PDO, config->usb2_port_disable_mask),
                REG_PCI_WRITE32(XHCI_USB3PDO, config->usb3_port_disable_mask),
                /* Close per-port disable control override */
                REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0),

But I can only either see the EHCI or the xHCI controller via "pci". If I configure the FSP to enable xHCI (fsp,enable-xhci) the EHCI PCI device is not listed. And without this DT property the xHCI PCI device is missing. So I only have access to one USB controller at the some time.

Any further ideas are really welcome! :)

BTW: Did you (or somebody else?) already start moving xHCI (PCI) to DM yet? If yes, could you perhaps provide this version so that I could continue with it.

Thanks,
Stefan

Quoted 141 lines · Stefan Roese

Hi Simon,

On 09.03.2016 00:33, Simon Glass wrote:

<snip>

Quoted 105 lines

Quoted 96 lines

Quoted 51 lines

Quoted 51 lines

I'm currently struggling with the USB EHCI ports on my custom Bay Trail x86 board. With the current U-Boot, cloned from the MinnowMAX, only some of the USB EHCI ports are enabled / available. Here the "usb tree" output with 3 USB keys installed:

=> usb tree
USB device tree:

     1  Hub (480 Mb/s, 0mA)
     |  u-boot EHCI Host Controller
     |
     +-2  Hub (480 Mb/s, 0mA)
       |
       +-3  Hub (480 Mb/s, 100mA)
       | |
       | +-4  Hub (12 Mb/s, 100mA)
       |
       +-5  Mass Storage (480 Mb/s, 200mA)
            JetFlash Mass Storage Device 3281440601

When I first start the original (AMI) BIOS on this custom board, and then reboot into U-Boot (without a power-cycle), I see this configuration:

=> usb tree
USB device tree:

     1  Hub (480 Mb/s, 0mA)
     |  u-boot EHCI Host Controller
     |
     +-2  Hub (480 Mb/s, 0mA)
       |
       +-3  Hub (480 Mb/s, 100mA)
       | |
       | +-4  Hub (12 Mb/s, 100mA)
       |
       +-5  Hub (480 Mb/s, 0mA)
       | |
       | +-6  Mass Storage (480 Mb/s, 200mA)
       | |    Kingston DataTraveler 2.0 50E549C688C4BE7189942766
       | |
       | +-7  Mass Storage (480 Mb/s, 98mA)
       |      USBest Technology USB Mass Storage Device 09092207fbf0c4
       |
       +-8  Mass Storage (480 Mb/s, 200mA)
            JetFlash Mass Storage Device 3281440601

So now all 3 USB sticks are detected.

It doesn't seem to be a problem with missing USB power switch enabling via some GPIOs. I've checked the schematics and all ports should have power enabled.

Quoted 8 lines

Quoted 5 lines

Do you have any quick ideas, what might be missing to enable all 4 EHCI ports on Bay Trail? There seems to be a per-port disable feature which might be involved. I'm still pretty new to x86, and I'm struggling with finding the correct datasheet for this. So any hints are really appreciated.

It might be worth checking the pci bus device list in both cases. Perhaps one of the USB ports is disabled?

IIUTC, its only one PCI device, that handles all EHCI USB 2.0 ports. In both cases its this output:

=> pci
Scanning PCI devices on bus 0
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________

00.1f.00   0x8086     0x0f1c     Bridge device           0x01
00.00.00   0x8086     0x0f00     Bridge device           0x00
00.02.00   0x8086     0x0f31     Display controller      0x00
00.11.00   0x8086     0x0f15     Base system peripheral  0x05
00.12.00   0x8086     0x0f16     Base system peripheral  0x05
00.13.00   0x8086     0x0f23     Mass storage controller 0x06
00.15.00   0x8086     0x0f28     Multimedia device       0x01
00.18.00   0x8086     0x0f40     Base system peripheral  0x01
00.18.01   0x8086     0x0f41     Serial bus controller   0x80
00.18.02   0x8086     0x0f42     Serial bus controller   0x80
00.18.03   0x8086     0x0f43     Serial bus controller   0x80
00.18.04   0x8086     0x0f44     Serial bus controller   0x80
00.18.05   0x8086     0x0f45     Serial bus controller   0x80
00.18.06   0x8086     0x0f46     Serial bus controller   0x80
00.18.07   0x8086     0x0f47     Serial bus controller   0x80
00.1a.00   0x8086     0x0f18     Cryptographic device    0x80
00.1c.00   0x8086     0x0f48     Bridge device           0x04
00.1c.03   0x8086     0x0f4e     Bridge device           0x04
00.1d.00   0x8086     0x0f34     Serial bus controller   0x03
00.1e.00   0x8086     0x0f06     Base system peripheral  0x01
00.1e.01   0x8086     0x0f08     Serial bus controller   0x80
00.1e.02   0x8086     0x0f09     Serial bus controller   0x80
00.1e.04   0x8086     0x0f0c     Simple comm. controller 0x80
00.1e.05   0x8086     0x0f0e     Serial bus controller   0x80
00.1f.03   0x8086     0x0f12     Serial bus controller   0x05

Here 00.1d.00 is the EHCI controller. The "pci long" output is also identical. So its not that simple I'm afraid.

Quoted 8 lines

The Intel Atom Processor Z3600 and Z3700 Series Datasheet Vol 1 mentions in chapter "10.3.1 EHCI USB 2.0 Controller Features" on page 150:

? Per port USB disable

Perhaps this feature is biting me here. I'm wondering how this can be configured.

Quoted 8 lines

That sounds likely.

Also: xHCI and EHCI Port Mapping

suggests that you need to make sure the ports are being driven by EHCI instead of XHCI.

It mentions USB2HCSEL but I cannot find that in the datasheet.

Same here.

Quoted 10 lines

It does appear here though:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/perf_power.c

See IOSF_PORT_0x5a here:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/broadwell_fsp/src/lib/reg_script.c

So it looks like you need to set up this port, and perhaps some others asper that file.

I've looked into these coreboot files today. And ported parts of them to U-Boot to run these configurations there as well. Unfortunately without any (positive) effect. Some things I've tested are:

Configure 0x5a / 0xd0 (USB2HCSEL???) to different values. All without effect.

Quoted 3 lines

Unfortunately this value can't be read-out. At least I read always 0 here. So I can't see, if the AMI BIOS version configures here something different.

That's really odd, because it looks like this is a read/write interface. Worth digging int I think, and trying to find docs.

Quoted 19 lines

Then I've started looking into ehci.c:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/ehci.c

EHCI_USB2PDO (per-port disable) looked promising here. And writing 0xff into this reg results in all ports disabled:

=> usb tree
USB device tree:

   1  Hub (480 Mb/s, 0mA)
   |  u-boot EHCI Host Controller
   |
   +-2  Hub (480 Mb/s, 0mA)

So this register at least has some effect. But its initialized with 0 and writing 0 into it does not fix the problem with the missing ports.

Quoted 4 lines

I also ported the PHY values from usb2_phy_init() without any changes. The values here are the default values, as I can read them back. Also the AMI BIOS does not change these values, I've double checked this as well.

BTW is the AMI BIOS UEFI?

If so, for now I suppose you could boot into U-Boot from that, and deal with the problem later.

Quoted 34 lines

So I'm nearly out of ideas right now what else to configure / test to get all ports running. One idea is that the xHCI controller also needs some configuration for this port muxing. See:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/xhci.c:

                 /* USB3 SuperSpeed Enable */
                 REG_PCI_WRITE32(XHCI_USB3PR, BYTM_USB3_PORT_MAP),
                 /* USB2 Port Route to XHCI */
                 REG_PCI_WRITE32(XHCI_USB2PR, BYTM_USB2_PORT_MAP),

and:

                 /* Set USB2 Port Routing Mask */
                 REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP),
                 /* Set USB3 Port Routing Mask */
                 REG_PCI_WRITE32(XHCI_USB3PRM, BYTM_USB3_PORT_MAP),
                 /*
                  * Disable ports if requested
                  */
                 /* Open per-port disable control override */
                 REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN),
                 REG_PCI_WRITE32(XHCI_USB2PDO, config->usb2_port_disable_mask),
                 REG_PCI_WRITE32(XHCI_USB3PDO, config->usb3_port_disable_mask),
                 /* Close per-port disable control override */
                 REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0),

But I can only either see the EHCI or the xHCI controller via "pci". If I configure the FSP to enable xHCI (fsp,enable-xhci) the EHCI PCI device is not listed. And without this DT property the xHCI PCI device is missing. So I only have access to one USB controller at the some time.

Quoted 1 line

Any further ideas are really welcome! :)

I'm pretty short on time this month otherwise I would love to look at this.

Can you post a patch that adds all the init code you have found to baytrail?

Quoted 4 lines

BTW: Did you (or somebody else?) already start moving xHCI (PCI) to DM yet? If yes, could you perhaps provide this version so that I could continue with it.

Yes, see u-boot-x86/samus-working.

Hi Simon,

Quoted 152 lines · Simon Glass

Quoted 150 lines · Stefan Roese

Hi Simon,

On 09.03.2016 00:33, Simon Glass wrote:

<snip>

Quoted 109 lines

Quoted 99 lines

Quoted 59 lines

Quoted 52 lines

I'm currently struggling with the USB EHCI ports on my custom Bay Trail x86 board. With the current U-Boot, cloned from the MinnowMAX, only some of the USB EHCI ports are enabled / available. Here the "usb tree" output with 3 USB keys installed:

=> usb tree
USB device tree:

     1  Hub (480 Mb/s, 0mA)
     |  u-boot EHCI Host Controller
     |
     +-2  Hub (480 Mb/s, 0mA)
       |
       +-3  Hub (480 Mb/s, 100mA)
       | |
       | +-4  Hub (12 Mb/s, 100mA)
       |
       +-5  Mass Storage (480 Mb/s, 200mA)
            JetFlash Mass Storage Device 3281440601

When I first start the original (AMI) BIOS on this custom board, and then reboot into U-Boot (without a power-cycle), I see this configuration:

=> usb tree
USB device tree:

     1  Hub (480 Mb/s, 0mA)
     |  u-boot EHCI Host Controller
     |
     +-2  Hub (480 Mb/s, 0mA)
       |
       +-3  Hub (480 Mb/s, 100mA)
       | |
       | +-4  Hub (12 Mb/s, 100mA)
       |
       +-5  Hub (480 Mb/s, 0mA)
       | |
       | +-6  Mass Storage (480 Mb/s, 200mA)
       | |    Kingston DataTraveler 2.0 50E549C688C4BE7189942766
       | |
       | +-7  Mass Storage (480 Mb/s, 98mA)
       |      USBest Technology USB Mass Storage Device
09092207fbf0c4
       |
       +-8  Mass Storage (480 Mb/s, 200mA)
            JetFlash Mass Storage Device 3281440601

So now all 3 USB sticks are detected.

It doesn't seem to be a problem with missing USB power switch enabling via some GPIOs. I've checked the schematics and all ports should have power enabled.

Quoted 5 lines

Do you have any quick ideas, what might be missing to enable all 4 EHCI ports on Bay Trail? There seems to be a per-port disable feature which might be involved. I'm still pretty new to x86, and I'm struggling with finding the correct datasheet for this. So any hints are really appreciated.

Quoted 2 lines

It might be worth checking the pci bus device list in both cases. Perhaps one of the USB ports is disabled?

IIUTC, its only one PCI device, that handles all EHCI USB 2.0 ports. In both cases its this output:

=> pci
Scanning PCI devices on bus 0
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________

00.1f.00   0x8086     0x0f1c     Bridge device           0x01
00.00.00   0x8086     0x0f00     Bridge device           0x00
00.02.00   0x8086     0x0f31     Display controller      0x00
00.11.00   0x8086     0x0f15     Base system peripheral  0x05
00.12.00   0x8086     0x0f16     Base system peripheral  0x05
00.13.00   0x8086     0x0f23     Mass storage controller 0x06
00.15.00   0x8086     0x0f28     Multimedia device       0x01
00.18.00   0x8086     0x0f40     Base system peripheral  0x01
00.18.01   0x8086     0x0f41     Serial bus controller   0x80
00.18.02   0x8086     0x0f42     Serial bus controller   0x80
00.18.03   0x8086     0x0f43     Serial bus controller   0x80
00.18.04   0x8086     0x0f44     Serial bus controller   0x80
00.18.05   0x8086     0x0f45     Serial bus controller   0x80
00.18.06   0x8086     0x0f46     Serial bus controller   0x80
00.18.07   0x8086     0x0f47     Serial bus controller   0x80
00.1a.00   0x8086     0x0f18     Cryptographic device    0x80
00.1c.00   0x8086     0x0f48     Bridge device           0x04
00.1c.03   0x8086     0x0f4e     Bridge device           0x04
00.1d.00   0x8086     0x0f34     Serial bus controller   0x03
00.1e.00   0x8086     0x0f06     Base system peripheral  0x01
00.1e.01   0x8086     0x0f08     Serial bus controller   0x80
00.1e.02   0x8086     0x0f09     Serial bus controller   0x80
00.1e.04   0x8086     0x0f0c     Simple comm. controller 0x80
00.1e.05   0x8086     0x0f0e     Serial bus controller   0x80
00.1f.03   0x8086     0x0f12     Serial bus controller   0x05

Here 00.1d.00 is the EHCI controller. The "pci long" output is also identical. So its not that simple I'm afraid.

Quoted 8 lines

The Intel Atom Processor Z3600 and Z3700 Series Datasheet Vol 1 mentions in chapter "10.3.1 EHCI USB 2.0 Controller Features" on page 150:

? Per port USB disable

Perhaps this feature is biting me here. I'm wondering how this can be configured.

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That sounds likely.

Also: xHCI and EHCI Port Mapping

suggests that you need to make sure the ports are being driven by EHCI instead of XHCI.

It mentions USB2HCSEL but I cannot find that in the datasheet.

Same here.

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It does appear here though:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/perf_power.c

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See IOSF_PORT_0x5a here:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/broadwell_fsp/src/lib/reg_script.c

So it looks like you need to set up this port, and perhaps some others asper that file.

I've looked into these coreboot files today. And ported parts of them to U-Boot to run these configurations there as well. Unfortunately without any (positive) effect. Some things I've tested are:

Configure 0x5a / 0xd0 (USB2HCSEL???) to different values. All without effect.

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Unfortunately this value can't be read-out. At least I read always 0 here. So I can't see, if the AMI BIOS version configures here something different.

That's really odd, because it looks like this is a read/write interface. Worth digging int I think, and trying to find docs.

I've really tried to find some docs here. But all I can find on the net are the links to the coreboot source.

I've also printed all 0x5a registers, well not all but from 0x00 to 0x200. And all of them are read as 0. Yes, this is odd but I can't see that I'm doing something wrong here while reading those values.

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Then I've started looking into ehci.c:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/ehci.c

EHCI_USB2PDO (per-port disable) looked promising here. And writing 0xff into this reg results in all ports disabled:

=> usb tree
USB device tree:

   1  Hub (480 Mb/s, 0mA)
   |  u-boot EHCI Host Controller
   |
   +-2  Hub (480 Mb/s, 0mA)

So this register at least has some effect. But its initialized with 0 and writing 0 into it does not fix the problem with the missing ports.

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I also ported the PHY values from usb2_phy_init() without any changes. The values here are the default values, as I can read them back. Also the AMI BIOS does not change these values, I've double checked this as well.

BTW is the AMI BIOS UEFI?

I think so - I need to check to be 100% sure though.

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If so, for now I suppose you could boot into U-Boot from that, and deal with the problem later.

Interesting idea. Right now I'm booting into the AMI BIOS once, and then only doing reset's into U-Boot (I can toggle the SPI NOR chip via a DIP switch, which is quite handy).

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So I'm nearly out of ideas right now what else to configure / test to get all ports running. One idea is that the xHCI controller also needs some configuration for this port muxing. See:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/xhci.c:

                 /* USB3 SuperSpeed Enable */
                 REG_PCI_WRITE32(XHCI_USB3PR, BYTM_USB3_PORT_MAP),
                 /* USB2 Port Route to XHCI */
                 REG_PCI_WRITE32(XHCI_USB2PR, BYTM_USB2_PORT_MAP),

and:

                 /* Set USB2 Port Routing Mask */
                 REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP),
                 /* Set USB3 Port Routing Mask */
                 REG_PCI_WRITE32(XHCI_USB3PRM, BYTM_USB3_PORT_MAP),
                 /*
                  * Disable ports if requested
                  */
                 /* Open per-port disable control override */
                 REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0,
UPRWC_WR_EN),
                 REG_PCI_WRITE32(XHCI_USB2PDO,
config->usb2_port_disable_mask),
                 REG_PCI_WRITE32(XHCI_USB3PDO,

config->usb3_port_disable_mask),
/* Close per-port disable control override */ REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN,
0),

But I can only either see the EHCI or the xHCI controller via "pci". If I configure the FSP to enable xHCI (fsp,enable-xhci) the EHCI PCI device is not listed. And without this DT property the xHCI PCI device is missing. So I only have access to one USB controller at the some time.

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Any further ideas are really welcome! :)

I'm pretty short on time this month otherwise I would love to look at this.

That would be great, thanks!

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Can you post a patch that adds all the init code you have found to baytrail?

I need to clean this mess up a bit before I can post something of this. And I've used the last few days to implement the USB scanning enhancements, as you will have noticed in your inbox. :)

I'll definitely come back to your offer beginning of next week and will post this coreboot register access stuff I've added to my platform code for testing.

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BTW: Did you (or somebody else?) already start moving xHCI (PCI) to DM yet? If yes, could you perhaps provide this version so that I could continue with it.

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Yes, see u-boot-x86/samus-working.

Thanks. I'll probably look into this next week.

Thanks,
Stefan

Hi Bin,

Quoted 51 lines · Bin Meng

Hi Andrew,

Quoted 46 lines · Andrew Bradford

Hi Simon,

Quoted 29 lines · Simon Glass

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

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Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

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- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working
- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.

I'm OK with disabling xhci and the MRC debug output in the FSP.

But if xhci is disabled then I believe when Linux boots that the USB 3.0 port on Minnow Max will only act as a USB 2.0 port. That u-boot doesn't yet have working XHCI on E3800 means there is a tradeoff and I wasn't sure which was a better choice.

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Does these xHCI ports on MinnowMax work fully on Linux kernel? If it works, I'd rather we keep fsp,enable-xhci in the U-Boot.

I believe that the xhci port does work on Minnow Max in Linux but I do not have a board so I'm unable to test, sorry.

Hi,

Quoted 12 lines · Bin Meng

Quoted 10 lines · Andrew Bradford

From: Andrew Bradford <[email protected]>

Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used.

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Signed-off-by Andrew Bradford <[email protected]>

---

Reviewed-by Bin Meng <[email protected]>

Tested-by Bin Meng <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested on minnowmax:

Tested-by Simon Glass <[email protected]>

I found that I need to remove two properties from the minnowmax.dts:

- fsp,enable-xhci needs to be removed as this does not work in U-Boot at present and stops EHCI from working

- fsp,mrc-debug-msg needs to be removed to prevent debug information being displayed

I plan to apply this with these changes - please let me know if this doesn't suit.