ARM: sunxi: Switch to clock indices

The A23 and A33 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

arch/arm/boot/dts/sun8i-a23-a33.dtsi +0 -0

index 7abd0ae3143d..c318c770b6c1 100644

arch/arm/boot/dts/sun8i-a23-a33.dtsi +6 -1

                        clock-output-names = "ahb1_mipidsi", "ahb1_dma",
                                        "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
                                        "ahb1_nand", "ahb1_sdram",

@@ -196,6 +205,8 @@
                        compatible = "allwinner,sun8i-a23-apb1-gates-clk";
                        reg = <0x01c20068 0x4>;
                        clocks = <&apb1>;
+                       clock-indices = <0>, <5>,
+                                       <12>, <13>;
                        clock-output-names = "apb1_codec", "apb1_pio",
                                        "apb1_daudio0", "apb1_daudio1";
                };

@@ -213,6 +224,10 @@
                        compatible = "allwinner,sun8i-a23-apb2-gates-clk";
                        reg = <0x01c2006c 0x4>;
                        clocks = <&apb2>;
+                       clock-indices = <0>, <1>,
+                                       <2>, <16>,
+                                       <17>, <18>,
+                                       <19>, <20>;
                        clock-output-names = "apb2_i2c0", "apb2_i2c1",
                                        "apb2_i2c2", "apb2_uart0",
                                        "apb2_uart1", "apb2_uart2",
--

2.4.6

Quoted 8 lines · Maxime Ripard

The A23 and A33 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

arch/arm/boot/dts/sun8i-a23-a33.dtsi line 183

Quoted 9 lines

arch/arm/boot/dts/sun8i-a23-a33.dtsi +1 -0

index 7abd0ae3143d..c318c770b6c1 100644
@@ -180,6 +180,15 @@
                        compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
                        reg = <0x01c20060 0x8>;
                        clocks = <&ahb1>;
+                       clock-indices = <1>, <6>,

Turns out the A33 (and I assume the same with the A23) has an ahb1 clock gate for the Security System at clock-index <5>.

This is found in the updated A33 user manual.

arch/arm/boot/dts/sun8i-a23-a33.dtsi line 190

Quoted 7 lines

arch/arm/boot/dts/sun8i-a23-a33.dtsi +7 -0

+                                       <8>, <9>, <10>,
+                                       <13>, <14>,
+                                       <19>, <20>,
+                                       <21>, <24>, <26>,
+                                       <29>, <32>, <36>,
+                                       <40>, <44>, <46>,
+                                       <52>, <54>,

<53> is ahb1 clock gate for msgbox, again found in A33 manual.

arch/arm/boot/dts/sun8i-a23-a33.dtsi line 191

Quoted 1 line

arch/arm/boot/dts/sun8i-a23-a33.dtsi +1 -0

+                                       <57>;

<58> is ahb1 clock gate for SAT, which seems to be part of the display pipeline.

Quoted 24 lines

arch/arm/boot/dts/sun8i-a23-a33.dtsi +6 -1

                        clock-output-names = "ahb1_mipidsi", "ahb1_dma",
                                        "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
                                        "ahb1_nand", "ahb1_sdram",

@@ -196,6 +205,8 @@
                        compatible = "allwinner,sun8i-a23-apb1-gates-clk";
                        reg = <0x01c20068 0x4>;
                        clocks = <&apb1>;
+                       clock-indices = <0>, <5>,
+                                       <12>, <13>;
                        clock-output-names = "apb1_codec", "apb1_pio",
                                        "apb1_daudio0", "apb1_daudio1";
                };

@@ -213,6 +224,10 @@
                        compatible = "allwinner,sun8i-a23-apb2-gates-clk";
                        reg = <0x01c2006c 0x4>;
                        clocks = <&apb2>;
+                       clock-indices = <0>, <1>,
+                                       <2>, <16>,
+                                       <17>, <18>,
+                                       <19>, <20>;
                        clock-output-names = "apb2_i2c0", "apb2_i2c1",
                                        "apb2_i2c2", "apb2_uart0",
                                        "apb2_uart1", "apb2_uart2",
--

Quoted 2 lines

2.4.6

Not sure if you want to add the clocks I mentioned together in this patch, or do a separate patch.

The rest look good.

ChenYu

Quoted 10 lines

Quoted 8 lines · Maxime Ripard

The A23 and A33 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

Quoted 12 lines

arch/arm/boot/dts/sun8i-a23-a33.dtsi line 183

Quoted 9 lines

arch/arm/boot/dts/sun8i-a23-a33.dtsi +1 -0

index 7abd0ae3143d..c318c770b6c1 100644
@@ -180,6 +180,15 @@
                        compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
                        reg = <0x01c20060 0x8>;
                        clocks = <&ahb1>;
+                       clock-indices = <1>, <6>,

Turns out the A33 (and I assume the same with the A23) has an ahb1 clock gate for the Security System at clock-index <5>.

Looks like the A23 does not have this one, nor the SS mod clock.

Quoted 11 lines

This is found in the updated A33 user manual.

arch/arm/boot/dts/sun8i-a23-a33.dtsi line 190

Quoted 7 lines

arch/arm/boot/dts/sun8i-a23-a33.dtsi +7 -0

+                                       <8>, <9>, <10>,
+                                       <13>, <14>,
+                                       <19>, <20>,
+                                       <21>, <24>, <26>,
+                                       <29>, <32>, <36>,
+                                       <40>, <44>, <46>,
+                                       <52>, <54>,

<53> is ahb1 clock gate for msgbox, again found in A33 manual.

A23 has this one. Found in Allwinner kernel sources.

Quoted 4 lines

arch/arm/boot/dts/sun8i-a23-a33.dtsi line 191

Quoted 1 line

arch/arm/boot/dts/sun8i-a23-a33.dtsi +1 -0

+                                       <57>;

<58> is ahb1 clock gate for SAT, which seems to be part of the display pipeline.

This one is A33 only.

I guess we should do a separate compatible for A33 AHB1 clock gates.

ChenYu

Quoted 30 lines

Quoted 24 lines

arch/arm/boot/dts/sun8i-a23-a33.dtsi +6 -1

                        clock-output-names = "ahb1_mipidsi", "ahb1_dma",
                                        "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
                                        "ahb1_nand", "ahb1_sdram",

@@ -196,6 +205,8 @@
                        compatible = "allwinner,sun8i-a23-apb1-gates-clk";
                        reg = <0x01c20068 0x4>;
                        clocks = <&apb1>;
+                       clock-indices = <0>, <5>,
+                                       <12>, <13>;
                        clock-output-names = "apb1_codec", "apb1_pio",
                                        "apb1_daudio0", "apb1_daudio1";
                };

@@ -213,6 +224,10 @@
                        compatible = "allwinner,sun8i-a23-apb2-gates-clk";
                        reg = <0x01c2006c 0x4>;
                        clocks = <&apb2>;
+                       clock-indices = <0>, <1>,
+                                       <2>, <16>,
+                                       <17>, <18>,
+                                       <19>, <20>;
                        clock-output-names = "apb2_i2c0", "apb2_i2c1",
                                        "apb2_i2c2", "apb2_uart0",
                                        "apb2_uart1", "apb2_uart2",
--

Quoted 2 lines

2.4.6

Not sure if you want to add the clocks I mentioned together in this patch, or do a separate patch.

Quoted 3 lines

The rest look good.

ChenYu

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Quoting Chen-Yu Tsai (2015-08-10 21:49:54)

Quoted 47 lines · Chen-Yu Tsai

Quoted 10 lines

Quoted 8 lines · Maxime Ripard

The A23 and A33 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

Quoted 12 lines

arch/arm/boot/dts/sun8i-a23-a33.dtsi line 183

Quoted 9 lines

arch/arm/boot/dts/sun8i-a23-a33.dtsi +1 -0

index 7abd0ae3143d..c318c770b6c1 100644
@@ -180,6 +180,15 @@
                        compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
                        reg = <0x01c20060 0x8>;
                        clocks = <&ahb1>;
+                       clock-indices = <1>, <6>,

Turns out the A33 (and I assume the same with the A23) has an ahb1 clock gate for the Security System at clock-index <5>.

Looks like the A23 does not have this one, nor the SS mod clock.

Quoted 11 lines

This is found in the updated A33 user manual.

arch/arm/boot/dts/sun8i-a23-a33.dtsi line 190

Quoted 7 lines

arch/arm/boot/dts/sun8i-a23-a33.dtsi +7 -0

+                                       <8>, <9>, <10>,
+                                       <13>, <14>,
+                                       <19>, <20>,
+                                       <21>, <24>, <26>,
+                                       <29>, <32>, <36>,
+                                       <40>, <44>, <46>,
+                                       <52>, <54>,

<53> is ahb1 clock gate for msgbox, again found in A33 manual.

A23 has this one. Found in Allwinner kernel sources.

Quoted 4 lines

arch/arm/boot/dts/sun8i-a23-a33.dtsi line 191

Quoted 1 line

arch/arm/boot/dts/sun8i-a23-a33.dtsi +1 -0

+                                       <57>;

<58> is ahb1 clock gate for SAT, which seems to be part of the display pipeline.

This one is A33 only.

Quoted 1 line

I guess we should do a separate compatible for A33 AHB1 clock gates.

ChenYu,

I believe Maxime is on vacation. I told him that I would pick these patches directly. It looks like your comments can be fixed up in follow-up patches at a later date, correct?

If so then I will apply them to clk-next.

Regards,
Mike

Quoted 41 lines

ChenYu

Quoted 30 lines

Quoted 24 lines

arch/arm/boot/dts/sun8i-a23-a33.dtsi +6 -1

                        clock-output-names = "ahb1_mipidsi", "ahb1_dma",
                                        "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
                                        "ahb1_nand", "ahb1_sdram",

@@ -196,6 +205,8 @@
                        compatible = "allwinner,sun8i-a23-apb1-gates-clk";
                        reg = <0x01c20068 0x4>;
                        clocks = <&apb1>;
+                       clock-indices = <0>, <5>,
+                                       <12>, <13>;
                        clock-output-names = "apb1_codec", "apb1_pio",
                                        "apb1_daudio0", "apb1_daudio1";
                };

@@ -213,6 +224,10 @@
                        compatible = "allwinner,sun8i-a23-apb2-gates-clk";
                        reg = <0x01c2006c 0x4>;
                        clocks = <&apb2>;
+                       clock-indices = <0>, <1>,
+                                       <2>, <16>,
+                                       <17>, <18>,
+                                       <19>, <20>;
                        clock-output-names = "apb2_i2c0", "apb2_i2c1",
                                        "apb2_i2c2", "apb2_uart0",
                                        "apb2_uart1", "apb2_uart2",
--

Quoted 2 lines

2.4.6

Not sure if you want to add the clocks I mentioned together in this patch, or do a separate patch.

Quoted 3 lines

The rest look good.

ChenYu

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Quoted 13 lines · Maxime Ripard

The A23 and A33 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

arch/arm/boot/dts/sun8i-a23-a33.dtsi +0 -0

index 7abd0ae3143d..c318c770b6c1 100644

arch/arm/boot/dts/sun8i-a23-a33.dtsi line 183

Quoted 4 lines

arch/arm/boot/dts/sun8i-a23-a33.dtsi +1 -0

@@ -180,6 +180,15 @@
                        compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
                        reg = <0x01c20060 0x8>;
                        clocks = <&ahb1>;
+                       clock-indices = <1>, <6>,

Turns out the A33 (and I assume the same with the A23) has an ahb1 clock gate for the Security System at clock-index <5>.

This is found in the updated A33 user manual.

arch/arm/boot/dts/sun8i-a23-a33.dtsi line 190

Quoted 7 lines

arch/arm/boot/dts/sun8i-a23-a33.dtsi +7 -0

+                                       <8>, <9>, <10>,
+                                       <13>, <14>,
+                                       <19>, <20>,
+                                       <21>, <24>, <26>,
+                                       <29>, <32>, <36>,
+                                       <40>, <44>, <46>,
+                                       <52>, <54>,

<53> is ahb1 clock gate for msgbox, again found in A33 manual.

arch/arm/boot/dts/sun8i-a23-a33.dtsi line 191

Quoted 1 line

arch/arm/boot/dts/sun8i-a23-a33.dtsi +1 -0

+                                       <57>;

<58> is ahb1 clock gate for SAT, which seems to be part of the display pipeline.

Quoted 24 lines

arch/arm/boot/dts/sun8i-a23-a33.dtsi +6 -1

                        clock-output-names = "ahb1_mipidsi", "ahb1_dma",
                                        "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
                                        "ahb1_nand", "ahb1_sdram",

@@ -196,6 +205,8 @@
                        compatible = "allwinner,sun8i-a23-apb1-gates-clk";
                        reg = <0x01c20068 0x4>;
                        clocks = <&apb1>;
+                       clock-indices = <0>, <5>,
+                                       <12>, <13>;
                        clock-output-names = "apb1_codec", "apb1_pio",
                                        "apb1_daudio0", "apb1_daudio1";
                };

@@ -213,6 +224,10 @@
                        compatible = "allwinner,sun8i-a23-apb2-gates-clk";
                        reg = <0x01c2006c 0x4>;
                        clocks = <&apb2>;
+                       clock-indices = <0>, <1>,
+                                       <2>, <16>,
+                                       <17>, <18>,
+                                       <19>, <20>;
                        clock-output-names = "apb2_i2c0", "apb2_i2c1",
                                        "apb2_i2c2", "apb2_uart0",
                                        "apb2_uart1", "apb2_uart2",
--

Quoted 2 lines

2.4.6

Not sure if you want to add the clocks I mentioned together in this patch, or do a separate patch.

The rest look good.

The gates were handled with a common piece of framework that was registering all gates array, that was not using the CLK_OF_DECLARE logic, and was not using clock-indices but some private masks that were pretty much equivalent.

Move this code in a new driver that handles all the gates array and solves both these issues.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/clk/sunxi/Makefile           |   1 +
 drivers/clk/sunxi/clk-simple-gates.c | 157 +++++++++++++++++++++++++++++++
 drivers/clk/sunxi/clk-sunxi.c        | 177 -----------------------------------
 3 files changed, 158 insertions(+), 177 deletions(-)
 create mode 100644 drivers/clk/sunxi/clk-simple-gates.c

drivers/clk/sunxi/Makefile +1 -0

index 058f273d6154..f5a35b82cc1a 100644
@@ -6,6 +6,7 @@ obj-y += clk-sunxi.o clk-factors.o
 obj-y += clk-a10-hosc.o
 obj-y += clk-a20-gmac.o
 obj-y += clk-mod0.o
+obj-y += clk-simple-gates.o
 obj-y += clk-sun8i-mbus.o
 obj-y += clk-sun9i-core.o
 obj-y += clk-sun9i-mmc.o

drivers/clk/sunxi/clk-simple-gates.c new file +157 -0

new file mode 100644
index 000000000000..39e57e3d745c
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+static DEFINE_SPINLOCK(gates_lock);
+
+static void __init sunxi_simple_gates_setup(struct device_node *node,
+                                           const int protected[],
+                                           int nprotected)
+{
+       struct clk_onecell_data *clk_data;
+       const char *clk_parent, *clk_name;
+       struct property *prop;
+       struct resource res;
+       void __iomem *clk_reg;
+       void __iomem *reg;
+       const __be32 *p;
+       int number, i = 0, j;
+       u8 clk_bit;
+       u32 index;
+
+       reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+       if (IS_ERR(reg))
+               return;
+
+       clk_parent = of_clk_get_parent_name(node, 0);
+
+       clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
+       if (!clk_data)
+               goto err_unmap;
+
+       number = of_property_count_u32_elems(node, "clock-indices");
+       of_property_read_u32_index(node, "clock-indices", number - 1, &number);
+
+       clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
+       if (!clk_data->clks)
+               goto err_free_data;
+
+       of_property_for_each_u32(node, "clock-indices", prop, p, index) {
+               of_property_read_string_index(node, "clock-output-names",
+                                             i, &clk_name);
+
+               clk_reg = reg + 4 * (index / 32);
+               clk_bit = index % 32;
+
+               clk_data->clks[index] = clk_register_gate(NULL, clk_name,
+                                                         clk_parent, 0,
+                                                         clk_reg,
+                                                         clk_bit,
+                                                         0, &gates_lock);
+               i++;
+
+               if (IS_ERR(clk_data->clks[index])) {
+                       WARN_ON(true);
+                       continue;
+               }
+
+               for (j = 0; j < nprotected; j++)
+                       if (protected[j] == index)
+                               clk_prepare_enable(clk_data->clks[index]);
+
+       }
+
+       clk_data->clk_num = number + 1;
+       of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+       return;
+
+err_free_data:
+       kfree(clk_data);
+err_unmap:
+       iounmap(reg);
+       of_address_to_resource(node, 0, &res);
+       release_mem_region(res.start, resource_size(&res));
+}
+
+static void __init sunxi_simple_gates_init(struct device_node *node)
+{
+       sunxi_simple_gates_setup(node, NULL, 0);
+}
+
+CLK_OF_DECLARE(sun4i_a10_apb0, "allwinner,sun4i-a10-apb0-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun4i_a10_apb1, "allwinner,sun4i-a10-apb1-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun4i_a10_axi, "allwinner,sun4i-a10-axi-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a10s_apb0, "allwinner,sun5i-a10s-apb0-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a10s_apb1, "allwinner,sun5i-a10s-apb1-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a13_apb0, "allwinner,sun5i-a13-apb0-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a13_apb1, "allwinner,sun5i-a13-apb1-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun6i_a31_apb1, "allwinner,sun6i-a31-apb1-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun6i_a31_apb2, "allwinner,sun6i-a31-apb2-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun7i_a20_apb0, "allwinner,sun7i-a20-apb0-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun7i_a20_apb1, "allwinner,sun7i-a20-apb1-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_a23_ahb1, "allwinner,sun8i-a23-ahb1-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_a23_apb1, "allwinner,sun8i-a23-apb1-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_ahb2, "allwinner,sun9i-a80-ahb2-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-gates-clk",
+              sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-gates-clk",
+              sunxi_simple_gates_init);
+
+static const int sun4i_a10_ahb_critical_clocks[] __initconst = {
+       14,     /* ahb_sdram */
+};
+
+static void __init sun4i_a10_ahb_init(struct device_node *node)
+{
+       sunxi_simple_gates_setup(node, sun4i_a10_ahb_critical_clocks,
+                                ARRAY_SIZE(sun4i_a10_ahb_critical_clocks));
+}
+CLK_OF_DECLARE(sun4i_a10_ahb, "allwinner,sun4i-a10-ahb-gates-clk",
+              sun4i_a10_ahb_init);
+CLK_OF_DECLARE(sun5i_a10s_ahb, "allwinner,sun5i-a10s-ahb-gates-clk",
+              sun4i_a10_ahb_init);
+CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk",
+              sun4i_a10_ahb_init);
+CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",
+              sun4i_a10_ahb_init);

drivers/clk/sunxi/clk-sunxi.c +0 -178

index abf7b37faf73..1fec91093fcd 100644
@@ -900,150 +900,6 @@ struct gates_data {
        DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
 };
 
-static const struct gates_data sun4i_axi_gates_data __initconst = {
-       .mask = {1},
-};
-
-static const struct gates_data sun4i_ahb_gates_data __initconst = {
-       .mask = {0x7F77FFF, 0x14FB3F},
-};
-
-static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
-       .mask = {0x147667e7, 0x185915},
-};
-
-static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
-       .mask = {0x107067e7, 0x185111},
-};
-
-static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
-       .mask = {0xEDFE7F62, 0x794F931},
-};
-
-static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
-       .mask = { 0x12f77fff, 0x16ff3f },
-};
-
-static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
-       .mask = {0x25386742, 0x2505111},
-};
-
-static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
-       .mask = {0xF5F12B},
-};
-
-static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
-       .mask = {0x1E20003},
-};
-
-static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
-       .mask = {0x9B7},
-};
-
-static const struct gates_data sun4i_apb0_gates_data __initconst = {
-       .mask = {0x4EF},
-};
-
-static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
-       .mask = {0x469},
-};
-
-static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
-       .mask = {0x61},
-};
-
-static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
-       .mask = { 0x4ff },
-};
-
-static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
-       .mask = {0xEB822},
-};
-
-static const struct gates_data sun4i_apb1_gates_data __initconst = {
-       .mask = {0xFF00F7},
-};
-
-static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
-       .mask = {0xf0007},
-};
-
-static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
-       .mask = {0xa0007},
-};
-
-static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
-       .mask = {0x3031},
-};
-
-static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
-       .mask = {0x3021},
-};
-
-static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
-       .mask = {0x3F000F},
-};
-
-static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
-       .mask = { 0xff80ff },
-};
-
-static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
-       .mask = {0x3F001F},
-};
-
-static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
-       .mask = {0x1F0007},
-};
-
-static void __init sunxi_gates_clk_setup(struct device_node *node,
-                                        struct gates_data *data)
-{
-       struct clk_onecell_data *clk_data;
-       const char *clk_parent;
-       const char *clk_name;
-       void __iomem *reg;
-       int qty;
-       int i = 0;
-       int j = 0;
-
-       reg = of_iomap(node, 0);
-
-       clk_parent = of_clk_get_parent_name(node, 0);
-
-       /* Worst-case size approximation and memory allocation */
-       qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
-       clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
-       if (!clk_data)
-               return;
-       clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
-       if (!clk_data->clks) {
-               kfree(clk_data);
-               return;
-       }
-
-       for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
-               of_property_read_string_index(node, "clock-output-names",
-                                             j, &clk_name);
-
-               clk_data->clks[i] = clk_register_gate(NULL, clk_name,
-                                                     clk_parent, 0,
-                                                     reg + 4 * (i/32), i % 32,
-                                                     0, &clk_lock);
-               WARN_ON(IS_ERR(clk_data->clks[i]));
-               clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
-
-               j++;
-       }
-
-       /* Adjust to the real max */
-       clk_data->clk_num = i;
-
-       of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-}
-
-
-
 /**
  * sunxi_divs_clk_setup() helper data
  */

@@ -1281,34 +1137,6 @@ static const struct of_device_id clk_mux_match[] __initconst = {
        {}
 };
 
-/* Matches for gate clocks */
-static const struct of_device_id clk_gates_match[] __initconst = {
-       {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
-       {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
-       {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
-       {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
-       {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
-       {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
-       {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
-       {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
-       {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
-       {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
-       {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
-       {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
-       {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
-       {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
-       {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
-       {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
-       {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
-       {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
-       {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
-       {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
-       {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
-       {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
-       {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
-       {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
-       {}
-};
 
 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
                                              void *function)

@@ -1340,9 +1168,6 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
        /* Register mux clocks */
        of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
 
-       /* Register gate clocks */
-       of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
-
        /* Protect the clocks that needs to stay on */
        for (i = 0; i < nclocks; i++) {
                struct clk *clk = clk_get(NULL, clocks[i]);

@@ -1354,7 +1179,6 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
 
 static const char *sun4i_a10_critical_clocks[] __initdata = {
        "pll5_ddr",
-       "ahb_sdram",
 };
 
 static void __init sun4i_a10_init_clocks(struct device_node *node)

@@ -1367,7 +1191,6 @@ CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks)
 static const char *sun5i_critical_clocks[] __initdata = {
        "cpu",
        "pll5_ddr",
-       "ahb_sdram",
 };
 
 static void __init sun5i_init_clocks(struct device_node *node)
--

2.4.6