clk: rockchip: Fix SPIF special clock definition
Subsystems (2)
PATCH 1/1 clk: rockchip: Fix SPIF special clock definition
Neither spdif_src nor spdif_pll exists, judging by the vendor kernel in both cases spdif_pre was meant. This brings the naming in line and hierachy in line with that of sclk_i2s0.
Also allow sclk_spdif and spdif_frac to change their parents rate as that the upstream dividers are purely there to feed sclk_spdif
--- drivers/clk/rockchip/clk-rk3188.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/clk/rockchip/clk-rk3188.c +3 -3
@@ -202,7 +202,7 @@ PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };PNAME (mux_aclk_cpu_p) = {"apll" ,"gpll" };PNAME (mux_sclk_cif0_p) = {"cif0_pre" ,"xin24m" };PNAME (mux_sclk_i2s0_p) = {"i2s0_pre" ,"i2s0_frac" ,"xin12m" }; -PNAME (mux_sclk_spdif_p) = {"spdif_src" ,"spdif_frac" ,"xin12m" }; +PNAME (mux_sclk_spdif_p) = {"spdif_pre" ,"spdif_frac" ,"xin12m" };PNAME (mux_sclk_uart0_p) = {"uart0_pre" ,"uart0_frac" ,"xin24m" };PNAME (mux_sclk_uart1_p) = {"uart1_pre" ,"uart1_frac" ,"xin24m" };PNAME (mux_sclk_uart2_p) = {"uart2_pre" ,"uart2_frac" ,"xin24m" };
@@ -350,10 +350,10 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {COMPOSITE_NOMUX (0 ,"spdif_pre" ,"i2s_src" ,0 ,RK2928_CLKSEL_CON (5 ),0 ,7 ,DFLAGS ,RK2928_CLKGATE_CON (0 ),13 ,GFLAGS ), -COMPOSITE_FRAC (0 ,"spdif_frac" ,"spdif_pll" ,0 , +COMPOSITE_FRAC (0 ,"spdif_frac" ,"spdif_pre" ,CLK_SET_RATE_PARENT ,RK2928_CLKSEL_CON (9 ),0 ,RK2928_CLKGATE_CON (0 ),14 ,GFLAGS ), -MUX (SCLK_SPDIF ,"sclk_spdif" , mux_sclk_spdif_p,0 , +MUX (SCLK_SPDIF ,"sclk_spdif" , mux_sclk_spdif_p,CLK_SET_RATE_PARENT , RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),/*
Signature · 1 line
2.4.6
Heiko Stübner
maintainerPATCH 1/1 clk: rockchip: Fix SPIF special clock definition
Am Dienstag, 28. Juli 2015, 11:52:42 schrieb Sjoerd Simons:
Quoted 8 lines
Neither
spdif_srcnorspdif_pllexists, judging by the vendor kernel in both casesspdif_prewas meant. This brings the naming in line and hierachy in line with that ofsclk_i2s0.Also allow
sclk_spdifandspdif_fracto change their parents rate as that the upstream dividers are purely there to feedsclk_spdifSigned-off-by Sjoerd Simons <[email protected]>
I guess there was one rename to many back in the time :-) . Verified this with the CRU documentation, so
Quoted 31 lines
--- drivers/clk/rockchip/clk-rk3188.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)(quoted diff) +0
-0
b/drivers/clk/rockchip/clk-rk3188.cindex 0abf22d..ed02bbc 100644drivers/clk/rockchip/clk-rk3188.c +3
-3@@ -202,7 +202,7 @@ PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };PNAME (mux_aclk_cpu_p) = {"apll" ,"gpll" };PNAME (mux_sclk_cif0_p) = {"cif0_pre" ,"xin24m" };PNAME (mux_sclk_i2s0_p) = {"i2s0_pre" ,"i2s0_frac" ,"xin12m" }; -PNAME (mux_sclk_spdif_p) = {"spdif_src" ,"spdif_frac" ,"xin12m" }; +PNAME (mux_sclk_spdif_p) = {"spdif_pre" ,"spdif_frac" ,"xin12m" };PNAME (mux_sclk_uart0_p) = {"uart0_pre" ,"uart0_frac" ,"xin24m" };PNAME (mux_sclk_uart1_p) = {"uart1_pre" ,"uart1_frac" ,"xin24m" };PNAME (mux_sclk_uart2_p) = {"uart2_pre" ,"uart2_frac" ,"xin24m" };@@ -350,10 +350,10 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0, RK2928_CLKSEL_CON(5), 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 13, GFLAGS), - COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0, + COMPOSITE_FRAC(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(9), 0, RK2928_CLKGATE_CON(0), 14, GFLAGS), -MUX (SCLK_SPDIF ,"sclk_spdif" , mux_sclk_spdif_p,0 , +MUX (SCLK_SPDIF ,"sclk_spdif" , mux_sclk_spdif_p,CLK_SET_RATE_PARENT , RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),/*
Michael Turquette
AppliedPATCH 1/1 clk: rockchip: Fix SPIF special clock definition
Quoting Heiko St?bner (2015-07-28 03:08:54)
Quoted 8 lines
Am Dienstag, 28. Juli 2015, 11:52:42 schrieb Sjoerd Simons:
Quoted 7 lines
Neither
spdif_srcnorspdif_pllexists, judging by the vendor kernel in both casesspdif_prewas meant. This brings the naming in line and hierachy in line with that ofsclk_i2s0.Also allow
sclk_spdifandspdif_fracto change their parents rate as that the upstream dividers are purely there to feedsclk_spdif
Quoted 6 lines
Quoted 1 line
Signed-off-by Sjoerd Simons <[email protected]>I guess there was one rename to many back in the time :-) . Verified this with the CRU documentation, so
Reviewed-by Heiko Stuebner <[email protected]>
Applied to clk-next.
Regards,
Mike
Quoted 38 lines
Quoted 31 lines
--- drivers/clk/rockchip/clk-rk3188.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)(quoted diff) +0
-0
b/drivers/clk/rockchip/clk-rk3188.cindex 0abf22d..ed02bbc 100644drivers/clk/rockchip/clk-rk3188.c +3
-3@@ -202,7 +202,7 @@ PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };PNAME (mux_aclk_cpu_p) = {"apll" ,"gpll" };PNAME (mux_sclk_cif0_p) = {"cif0_pre" ,"xin24m" };PNAME (mux_sclk_i2s0_p) = {"i2s0_pre" ,"i2s0_frac" ,"xin12m" }; -PNAME (mux_sclk_spdif_p) = {"spdif_src" ,"spdif_frac" ,"xin12m" }; +PNAME (mux_sclk_spdif_p) = {"spdif_pre" ,"spdif_frac" ,"xin12m" };PNAME (mux_sclk_uart0_p) = {"uart0_pre" ,"uart0_frac" ,"xin24m" };PNAME (mux_sclk_uart1_p) = {"uart1_pre" ,"uart1_frac" ,"xin24m" };PNAME (mux_sclk_uart2_p) = {"uart2_pre" ,"uart2_frac" ,"xin24m" };@@ -350,10 +350,10 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0, RK2928_CLKSEL_CON(5), 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 13, GFLAGS), - COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0, + COMPOSITE_FRAC(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(9), 0, RK2928_CLKGATE_CON(0), 14, GFLAGS), -MUX (SCLK_SPDIF ,"sclk_spdif" , mux_sclk_spdif_p,0 , +MUX (SCLK_SPDIF ,"sclk_spdif" , mux_sclk_spdif_p,CLK_SET_RATE_PARENT , RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),Quoted 1 line
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