clk: atlas7: a bind of fixes

PATCH New Barry Song 2 participants 14 messages Aug 4, 2015 – Aug 12, 2015 Common clk

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Barry Song

author

2015-08-04 14:45 UTC #0 lore raw

v2 cover clk: atlas7: a bind of fixes

-v2: refine commit title according to the feedback of Stephen Boyd

Guo Zeng (5):
clk: atlas7: add lost pwm unit clks
clk: atlas7: export mux clks so that consumers can get them
clk: atlas7: fix the clock tree for bluetooth stuff
clk: atlas7: fix bit field and its root clk for coresight_tpiu
clk: atlas7: fix pll missed divide NR in fraction mode

Yibo Cai (2):
clk: atlas7: fix integer overflow in dto rate calculation
clk: atlas7: replace dto resolution magic number by macro

 drivers/clk/sirf/clk-atlas7.c | 33 +++++++++++++++++++++------------
 1 file changed, 21 insertions(+), 12 deletions(-)

Signature · 1 line

1.9.1

Barry Song

author

2015-08-04 14:45 UTC #1 lore raw

PATCH v2 1/7 clk: atlas7: add lost pwm unit clks

From: Guo Zeng <[email protected]>

Signed-off-by Guo Zeng <[email protected]>

Signed-off-by Barry Song <[email protected]>

---
 drivers/clk/sirf/clk-atlas7.c | 4 ++++
 1 file changed, 4 insertions(+)

drivers/clk/sirf/clk-atlas7.c +4 -0

index db8ab69..a92e7ea 100644
@@ -1174,6 +1174,10 @@ static struct atlas7_unit_init_data unit_list[] __initdata = {
 	{ 135, "thbtm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 7, &leaf8_gate_lock },
 	{ 136, "btslow", "xinw_fixdiv_btslow", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 25, &root1_gate_lock },
 	{ 137, "a7ca_btslow", "btslow", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 0, &leaf8_gate_lock },
+	{ 138 , "pwm_io", "io_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 0, &leaf0_gate_lock },
+	{ 139 , "pwm_xin", "xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 1, &leaf0_gate_lock },
+	{ 140 , "pwm_xinw", "xinw", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 2, &leaf0_gate_lock },
+	{ 141 , "thcgum_sys", "sys_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 3, &leaf0_gate_lock },
 };
 
 static struct clk *atlas7_clks[ARRAY_SIZE(unit_list)];

Signature · 1 line

1.9.1

Stephen Boyd

2015-08-12 00:27 UTC #2 lore raw

PATCH v2 1/7 clk: atlas7: add lost pwm unit clks

drivers/clk/sirf/clk-atlas7.c static struct atlas7_unit_init_data unit_list[] __initdata = { · line 1180

Quoted 12 lines · Barry Song

drivers/clk/sirf/clk-atlas7.c +4 -0

index db8ab69..a92e7ea 100644
@@ -1174,6 +1174,10 @@ static struct atlas7_unit_init_data unit_list[] __initdata = {
 	{ 135, "thbtm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 7, &leaf8_gate_lock },
 	{ 136, "btslow", "xinw_fixdiv_btslow", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 25, &root1_gate_lock },
 	{ 137, "a7ca_btslow", "btslow", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 0, &leaf8_gate_lock },
+	{ 138 , "pwm_io", "io_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 0, &leaf0_gate_lock },
+	{ 139 , "pwm_xin", "xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 1, &leaf0_gate_lock },
+	{ 140 , "pwm_xinw", "xinw", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 2, &leaf0_gate_lock },
+	{ 141 , "thcgum_sys", "sys_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 3, &leaf0_gate_lock },

The extra space made checkpatch complain. I silenced it and applied to clk-next.

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Barry Song

author

2015-08-04 14:45 UTC #3 lore raw

PATCH v2 2/7 clk: atlas7: export mux clks so that consumers can get them

In reply to Barry Song

From: Guo Zeng <[email protected]>

this patch makes mux clks can be referenced by device drivers.

Signed-off-by Guo Zeng <[email protected]>

Signed-off-by Barry Song <[email protected]>

---
 drivers/clk/sirf/clk-atlas7.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

drivers/clk/sirf/clk-atlas7.c +3 -2

index a92e7ea..d01dce3 100644
@@ -1180,7 +1180,7 @@ static struct atlas7_unit_init_data unit_list[] __initdata = {
 	{ 141 , "thcgum_sys", "sys_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 3, &leaf0_gate_lock },
 };
 
-static struct clk *atlas7_clks[ARRAY_SIZE(unit_list)];
+static struct clk *atlas7_clks[ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list)];
 
 static int unit_clk_is_enabled(struct clk_hw *hw)
 {

@@ -1613,6 +1613,7 @@ static void __init atlas7_clk_init(struct device_node *np)
 			       sirfsoc_clk_vbase + mux->mux_offset,
 			       mux->shift, mux->width,
 			       mux->mux_flags, NULL);
+		atlas7_clks[ARRAY_SIZE(unit_list) + i] = clk;
 		BUG_ON(!clk);
 	}

@@ -1624,7 +1625,7 @@ static void __init atlas7_clk_init(struct device_node *np)
 	}
 
 	clk_data.clks = atlas7_clks;
-	clk_data.clk_num = ARRAY_SIZE(unit_list);
+	clk_data.clk_num = ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list);
 
 	ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 	BUG_ON(ret);

Signature · 1 line

1.9.1

Stephen Boyd

Applied

2015-08-12 00:27 UTC #4 lore raw

PATCH v2 2/7 clk: atlas7: export mux clks so that consumers can get them

Quoted 7 lines · Barry Song

From: Guo Zeng <[email protected]>
this patch makes mux clks can be referenced by device drivers.
Signed-off-by Guo Zeng <[email protected]>
Signed-off-by Barry Song <[email protected]>
---

Applied to clk-next

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Barry Song

author

2015-08-04 14:45 UTC #5 lore raw

PATCH v2 3/7 clk: atlas7: fix integer overflow in dto rate calculation

In reply to Barry Song

From: Yibo Cai <[email protected]>

I cannot believe that I spend quite a lot time in finding this bug. It seems a pitfall people tend to fall in.

In "int64 = int32 * int32", conversion from 32-bits to 64-bits comes after the multiplication. So this statement may not work as expected.

Signed-off-by Yibo Cai <[email protected]>

Signed-off-by Barry Song <[email protected]>

---
 drivers/clk/sirf/clk-atlas7.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/clk/sirf/clk-atlas7.c +2 -2

index d01dce3..cf489a5 100644
@@ -519,7 +519,7 @@ static unsigned long dto_clk_recalc_rate(struct clk_hw *hw,
 static long dto_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 	unsigned long *parent_rate)
 {
-	u64 dividend = rate * (1 << 29);
+	u64 dividend = (u64)rate * (1 << 29);
 
 	do_div(dividend, *parent_rate);
 	dividend *= *parent_rate;

@@ -531,7 +531,7 @@ static long dto_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 static int dto_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 	unsigned long parent_rate)
 {
-	u64 dividend = rate * (1 << 29);
+	u64 dividend = (u64)rate * (1 << 29);
 	struct clk_dto *clk = to_dtoclk(hw);
 
 	do_div(dividend, parent_rate);

Signature · 1 line

1.9.1

Stephen Boyd

Applied

2015-08-12 00:27 UTC #6 lore raw

PATCH v2 3/7 clk: atlas7: fix integer overflow in dto rate calculation

Quoted 11 lines · Barry Song

From: Yibo Cai <[email protected]>
I cannot believe that I spend quite a lot time in finding this bug. It seems a pitfall people tend to fall in.
In "int64 = int32 * int32", conversion from 32-bits to 64-bits comes after the multiplication. So this statement may not work as expected.
Signed-off-by Yibo Cai <[email protected]>
Signed-off-by Barry Song <[email protected]>
---

Applied to clk-next

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Barry Song

author

2015-08-04 14:45 UTC #7 lore raw

PATCH v2 4/7 clk: atlas7: replace dto resolution magic number by macro

In reply to Barry Song

From: Yibo Cai <[email protected]>

Signed-off-by Yibo Cai <[email protected]>

Signed-off-by Barry Song <[email protected]>

---
 drivers/clk/sirf/clk-atlas7.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

drivers/clk/sirf/clk-atlas7.c +8 -5

index cf489a5..1000421 100644
@@ -465,6 +465,9 @@ static struct clk_pll clk_sys3pll = {
  *  double resolution mode:fout = fin * finc / 2^29
  *  normal mode:fout = fin * finc / 2^28
  */
+#define DTO_RESL_DOUBLE	(1ULL << 29)
+#define DTO_RESL_NORMAL	(1ULL << 28)
+
 static int dto_clk_is_enabled(struct clk_hw *hw)
 {
 	struct clk_dto *clk = to_dtoclk(hw);

@@ -509,9 +512,9 @@ static unsigned long dto_clk_recalc_rate(struct clk_hw *hw,
 	rate *= finc;
 	if (droff & BIT(0))
 		/* Double resolution off */
-		do_div(rate, 1 << 28);
+		do_div(rate, DTO_RESL_NORMAL);
 	else
-		do_div(rate, 1 << 29);
+		do_div(rate, DTO_RESL_DOUBLE);
 
 	return rate;
 }

@@ -519,11 +522,11 @@ static unsigned long dto_clk_recalc_rate(struct clk_hw *hw,
 static long dto_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 	unsigned long *parent_rate)
 {
-	u64 dividend = (u64)rate * (1 << 29);
+	u64 dividend = rate * DTO_RESL_DOUBLE;
 
 	do_div(dividend, *parent_rate);
 	dividend *= *parent_rate;
-	do_div(dividend, 1 << 29);
+	do_div(dividend, DTO_RESL_DOUBLE);
 
 	return dividend;
 }

@@ -531,7 +534,7 @@ static long dto_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 static int dto_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 	unsigned long parent_rate)
 {
-	u64 dividend = (u64)rate * (1 << 29);
+	u64 dividend = rate * DTO_RESL_DOUBLE;
 	struct clk_dto *clk = to_dtoclk(hw);
 
 	do_div(dividend, parent_rate);

Signature · 1 line

1.9.1

Stephen Boyd

Applied

2015-08-12 00:27 UTC #8 lore raw

PATCH v2 4/7 clk: atlas7: replace dto resolution magic number by macro

Quoted 5 lines · Barry Song

From: Yibo Cai <[email protected]>
Signed-off-by Yibo Cai <[email protected]>
Signed-off-by Barry Song <[email protected]>
---

Applied to clk-next

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Barry Song

author

2015-08-04 14:45 UTC #9 lore raw

PATCH v2 5/7 clk: atlas7: fix the clock tree for bluetooth stuff

In reply to Barry Song

From: Guo Zeng <[email protected]>

normally dmac should depends on only one clock, to operate dmac internal register, but dmac4 is very special case, it normally dmac should depends on only one clock, to operate dmac internal register, but dmac4 is very special case, it depends on two additional clock, the reason is that dmac4 is wrapped in hw into bt a7ca module, and accessing dmac4 internal register would also require that the a7ca_io and related bt macro io clk also enabled.
here workaround this by setting depend clk into parent of dmac4, and also related clks, to reflect dependency. noc_io

    -btm_noc_clk
            -a7ca_io
                    -dmac4_io
                                    -uart6_io
                                    -usp3_io

Signed-off-by Guo Zeng <[email protected]>

Signed-off-by Barry Song <[email protected]>

---
 drivers/clk/sirf/clk-atlas7.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

drivers/clk/sirf/clk-atlas7.c +4 -4

index 1000421..c1788df 100644
@@ -1169,10 +1169,10 @@ static struct atlas7_unit_init_data unit_list[] __initdata = {
 	{ 127, "vss_sdr", "gpum_sdr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 1, &leaf7_gate_lock },
 	{ 128, "thgpum_nocr", "gpum_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 2, &leaf7_gate_lock },
 	{ 129, "a7ca_btss", "btm_btss", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 1, &leaf8_gate_lock },
-	{ 130, "dmac4_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 2, &leaf8_gate_lock },
-	{ 131, "uart6_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 3, &leaf8_gate_lock },
-	{ 132, "usp3_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 4, &leaf8_gate_lock },
-	{ 133, "a7ca_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 5, &leaf8_gate_lock },
+	{ 130 , "dmac4_io", "a7ca_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 2, &leaf8_gate_lock },
+	{ 131 , "uart6_io", "dmac4_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 3, &leaf8_gate_lock },
+	{ 132 , "usp3_io", "dmac4_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 4, &leaf8_gate_lock },
+	{ 133 , "a7ca_io", "noc_btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 5, &leaf8_gate_lock },
 	{ 134, "noc_btm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 6, &leaf8_gate_lock },
 	{ 135, "thbtm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 7, &leaf8_gate_lock },
 	{ 136, "btslow", "xinw_fixdiv_btslow", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 25, &root1_gate_lock },

Signature · 1 line

1.9.1

Barry Song

author

2015-08-04 14:45 UTC #10 lore raw

PATCH v2 6/7 clk: atlas7: fix bit field and its root clk for coresight_tpiu

In reply to Barry Song

From: Guo Zeng <[email protected]>

bit4 thcpum_cpudiv4_clken r/w
thcpum_cpudiv4_clk clock enable (default: 1)
Root clock CPU_CLK must be enabled for this clock to be enabled

bit3 coresight_tpiu_clken r/w
coresight_tpiu_clk clock enable (default: 0)
Root clock TPIU_CLK must be enabled for this clock to be enabled

Signed-off-by Guo Zeng <[email protected]>

Signed-off-by Barry Song <[email protected]>

---
 drivers/clk/sirf/clk-atlas7.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/clk/sirf/clk-atlas7.c +1 -1

index c1788df..4fc33da 100644
@@ -1164,7 +1164,7 @@ static struct atlas7_unit_init_data unit_list[] __initdata = {
 	{ 122, "spram1_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 0, &leaf6_gate_lock },
 	{ 123, "spram2_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 1, &leaf6_gate_lock },
 	{ 124, "coresight_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 2, &leaf6_gate_lock },
-	{ 125, "thcpum_cpudiv4", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 3, &leaf6_gate_lock },
+	{ 125 , "coresight_tpiu", "cpum_tpiu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 3, &leaf6_gate_lock },
 	{ 126, "graphic_gpu", "gpum_gpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 0, &leaf7_gate_lock },
 	{ 127, "vss_sdr", "gpum_sdr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 1, &leaf7_gate_lock },
 	{ 128, "thgpum_nocr", "gpum_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 2, &leaf7_gate_lock },

Signature · 1 line

1.9.1

Stephen Boyd

2015-08-12 00:27 UTC #11 lore raw

PATCH v2 6/7 clk: atlas7: fix bit field and its root clk for coresight_tpiu

drivers/clk/sirf/clk-atlas7.c static struct atlas7_unit_init_data unit_list[] __initdata = { · line 1167

Quoted 10 lines · Barry Song

drivers/clk/sirf/clk-atlas7.c +1 -1

index c1788df..4fc33da 100644
@@ -1164,7 +1164,7 @@ static struct atlas7_unit_init_data unit_list[] __initdata = {
 	{ 122, "spram1_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 0, &leaf6_gate_lock },
 	{ 123, "spram2_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 1, &leaf6_gate_lock },
 	{ 124, "coresight_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 2, &leaf6_gate_lock },
-	{ 125, "thcpum_cpudiv4", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 3, &leaf6_gate_lock },
+	{ 125 , "coresight_tpiu", "cpum_tpiu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 3, &leaf6_gate_lock },

This one too. Silenced checkpatch error by removing space after
125. Applied to clk-next.

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Barry Song

author

2015-08-04 14:45 UTC #12 lore raw

PATCH v2 7/7 clk: atlas7: fix pll missed divide NR in fraction mode

In reply to Barry Song

From: Guo Zeng <[email protected]>

PLL VCO frequency is given by Fvco = Fref * 2 * NF / NR in integer-N mode, or by Fvco = Fref * SSN / NR in Spread Spectrum (fractional-N) mode. Thus fix the missing part of NR

Signed-off-by Guo Zeng <[email protected]>

Signed-off-by Barry Song <[email protected]>

---
 drivers/clk/sirf/clk-atlas7.c | 1 +
 1 file changed, 1 insertion(+)

drivers/clk/sirf/clk-atlas7.c +1 -0

index 4fc33da..19f417c 100644
@@ -358,6 +358,7 @@ static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
 	if (regctrl0 & SIRFSOC_ABPLL_CTRL0_SSEN) {
 		rate = fin;
 		rate *= 1 << 24;
+		do_div(rate, nr);
 		do_div(rate, (256 * ((ssdiv >> ssdepth) << ssdepth)
 			+ (ssmod << ssdepth)));
 	} else {

Signature · 1 line

1.9.1

Stephen Boyd

Applied

2015-08-12 00:30 UTC #13 lore raw

PATCH 7/7 clk: atlas7: fix pll missed divide NR in fraction mode

Quoted 10 lines · Barry Song

From: Guo Zeng <[email protected]>
PLL VCO frequency is given by Fvco = Fref * 2 * NF / NR in integer-N mode, or by Fvco = Fref * SSN / NR in Spread Spectrum (fractional-N) mode. Thus fix the missing part of NR
Signed-off-by Guo Zeng <[email protected]>
Signed-off-by Barry Song <[email protected]>
---

Applied to clk-next

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project