dcache support for Raspberry Pi 1

index a7aed4b..5d4b3c2 100644
@@ -32,16 +32,6 @@ int cleanup_before_linux (void)
 
 	disable_interrupts ();
 
-#ifdef CONFIG_LCD
-	{
-		extern void lcd_disable(void);
-		extern void lcd_panel_disable(void);
-
-		lcd_disable(); /* proper disable of lcd & panel */
-		lcd_panel_disable();
-	}
-#endif
-
 	/* turn off I/D-cache */
 	icache_disable();
 	dcache_disable();

similarity index 100%
rename from arch/arm/cpu/arm1136/cpu.c
rename to arch/arm/cpu/arm11/cpu.c

51 lines not on this page · raw message

index ab2f4db..86422e3 100644
@@ -7,6 +7,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_SYS_CACHELINE_SIZE		32
+
 #include "rpi-common.h"
 
 #endif

index 2e7e74f..13dc8de 100644
@@ -9,6 +9,7 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BCM2836
+#define CONFIG_SYS_CACHELINE_SIZE		64
 
 #include "rpi-common.h"
 

index 96fe870..d21750e 100644
@@ -182,7 +182,7 @@ u32 rpi_board_rev = 0;
 
 int dram_init(void)
 {
-	ALLOC_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1, 16);
+	ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1);
 	int ret;
 
 	BCM2835_MBOX_INIT_HDR(msg);

@@ -212,7 +212,7 @@ static void set_fdtfile(void)
 
 static void set_usbethaddr(void)
 {
-	ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 16);
+	ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1);
 	int ret;
 
 	if (!models[rpi_board_rev].has_onboard_eth)

@@ -245,7 +245,7 @@ int misc_init_r(void)
 
 static int power_on_module(u32 module)
 {
-	ALLOC_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1, 16);
+	ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1);
 	int ret;
 
 	BCM2835_MBOX_INIT_HDR(msg_pwr);

@@ -269,7 +269,7 @@ static int power_on_module(u32 module)
 
 static void get_board_rev(void)
 {
-	ALLOC_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1, 16);
+	ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1);
 	int ret;
 	const char *name;
 

@@ -324,7 +324,7 @@ int board_init(void)
 
 int board_mmc_init(bd_t *bis)
 {
-	ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16);
+	ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1);
 	int ret;
 
 	power_on_module(BCM2835_MBOX_POWER_DEVID_SDHCI);

index 1f18231..61d054d 100644
@@ -38,8 +38,8 @@ struct msg_setup {
 
 void lcd_ctrl_init(void *lcdbase)
 {
-	ALLOC_ALIGN_BUFFER(struct msg_query, msg_query, 1, 16);
-	ALLOC_ALIGN_BUFFER(struct msg_setup, msg_setup, 1, 16);
+	ALLOC_CACHE_ALIGN_BUFFER(struct msg_query, msg_query, 1);
+	ALLOC_CACHE_ALIGN_BUFFER(struct msg_setup, msg_setup, 1);
 	int ret;
 	u32 w, h;
 

index 54d369c..ff959c8 100644
@@ -522,6 +522,9 @@ int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv);
  * a termination value are expected to immediately follow the header in
  * memory, as required by the property protocol.
  *
+ * Each struct bcm2835_mbox_hdr passed must be allocated with
+ * ALLOC_CACHE_ALIGN_BUFFER(x, y, z) to ensure proper cache flush/invalidate.
+ *
  * Returns 0 for success, any other value for error.
  */
 int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer);

index 1af9be7..311bd8f 100644
@@ -111,9 +111,18 @@ int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer)
 	dump_buf(buffer);
 #endif
 
+	flush_dcache_range((unsigned long)buffer,
+			   (unsigned long)((void *)buffer +
+			   roundup(buffer->buf_size, ARCH_DMA_MINALIGN)));
+
 	ret = bcm2835_mbox_call_raw(chan, phys_to_bus((u32)buffer), &rbuffer);
 	if (ret)
 		return ret;
+
+	invalidate_dcache_range((unsigned long)buffer,
+				(unsigned long)((void *)buffer +
+				roundup(buffer->buf_size, ARCH_DMA_MINALIGN)));
+
 	if (rbuffer != phys_to_bus((u32)buffer)) {
 		printf("mbox: Response buffer mismatch\n");
 		return -1;

index eee60a2..b7fb4f8 100644
@@ -21,9 +21,9 @@
 #define DWC2_STATUS_BUF_SIZE		64
 #define DWC2_DATA_BUF_SIZE		(64 * 1024)
 
-/* We need doubleword-aligned buffers for DMA transfers */
-DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer, DWC2_DATA_BUF_SIZE, 8);
-DEFINE_ALIGN_BUFFER(uint8_t, status_buffer, DWC2_STATUS_BUF_SIZE, 8);
+/* We need cacheline-aligned buffers for DMA transfers and dcache support */
+DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer, DWC2_DATA_BUF_SIZE, ARCH_DMA_MINALIGN);
+DEFINE_ALIGN_BUFFER(uint8_t, status_buffer, DWC2_STATUS_BUF_SIZE, ARCH_DMA_MINALIGN);
 
 #define MAX_DEVICE			16
 #define MAX_ENDPOINT			16

@@ -802,9 +802,14 @@ int chunk_msg(struct usb_device *dev, unsigned long pipe, int *pid, int in,
 		       (*pid << DWC2_HCTSIZ_PID_OFFSET),
 		       &hc_regs->hctsiz);
 
-		if (!in)
+		if (!in) {
 			memcpy(aligned_buffer, (char *)buffer + done, len);
 
+			flush_dcache_range((unsigned long)aligned_buffer,
+				(unsigned long)((void *)aligned_buffer +
+				roundup(len, ARCH_DMA_MINALIGN)));
+		}
+
 		writel(phys_to_bus((unsigned long)aligned_buffer),
 		       &hc_regs->hcdma);
 

@@ -820,6 +825,11 @@ int chunk_msg(struct usb_device *dev, unsigned long pipe, int *pid, int in,
 
 		if (in) {
 			xfer_len -= sub;
+
+			invalidate_dcache_range((unsigned long)aligned_buffer,
+				(unsigned long)((void *)aligned_buffer +
+				roundup(xfer_len, ARCH_DMA_MINALIGN)));
+
 			memcpy(buffer + done, aligned_buffer, xfer_len);
 			if (sub)
 				stop_transfer = 1;

index 1012cdd..dd638c4 100644
@@ -14,7 +14,6 @@
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_BCM2835
 #define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_DCACHE_OFF
 
 #define CONFIG_SYS_TIMER_RATE		1000000
 #define CONFIG_SYS_TIMER_COUNTER	\

index 13dc8de..bea4ebd 100644
@@ -10,6 +10,7 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BCM2836
 #define CONFIG_SYS_CACHELINE_SIZE		64
+#define CONFIG_SYS_DCACHE_OFF
 
 #include "rpi-common.h"