Enable edma support for ti-qspi
Subsystems (4)
Vignesh R
maintainerv2 cover Enable edma support for ti-qspi
This patch series enables DMA for QSPI on dra7xx and am43xx. Patch 1 and 2 make sure the buffers are mem aligned for dma operation. Patch 3-6 add support for enabling and disabling of edma3 clocks on am43xx and dra7xx. Patch 7-9 add dma functionality to ti_qspi driver. Patch 10 enable edma3 support in dra7xx config files.
Tested on DRA74 EVM: http://pastebin.ubuntu.com/11813977/
changes in v2:
* Move edma related code to edma driver instead of handling it in ti-qspi driver.
v1: https://www.mail-archive.com/u-boot at lists.denx.de/msg176479.html
Kishon Vijay Abraham I (2):
ARM: AM43xx: Add support for disabling clocks in uboot
ARM: OMAP5: Add support for disabling clocks in uboot
Ravi Babu (2):
sf: allocate cache aligned buffers to copy from flash
env: use cache line aligned memory for flash read
Tom Rini (1):
sf: ops: Add spi_flash_copy_mmap function
Vignesh R (5):
ARM: OMAP5: Add functions to enable and disable EDMA3 clocks
ARM: AM43XX: Add functions to enable and disable EDMA3 clocks
dma: ti-edma3: Add helper function to support edma3 transfer
spi: ti_qspi: Use DMA to read from qspi flash
ARM: dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspi
arch/arm/cpu/armv7/am33xx/clock.c | 52 +++++++++++++++++ arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 36 ++++++++++++ arch/arm/cpu/armv7/omap-common/clocks-common.c | 53 +++++++++++++++++ arch/arm/cpu/armv7/omap5/hw_data.c | 41 ++++++++++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 4 ++ arch/arm/include/asm/arch-am33xx/clock.h | 1 + arch/arm/include/asm/arch-omap5/hardware.h | 5 ++ arch/arm/include/asm/omap_common.h | 13 +++++ arch/arm/include/asm/ti-common/ti-edma3.h | 2 + common/cmd_sf.c | 6 +- common/env_sf.c | 11 ++-- drivers/dma/ti-edma3.c | 78 ++++++++++++++++++++++++++ drivers/mtd/spi/sf_ops.c | 8 ++- drivers/spi/ti_qspi.c | 23 ++++++++ include/configs/dra7xx_evm.h | 2 + include/spi.h | 3 + 16 files changed, 329 insertions(+), 9 deletions(-)
Signature · 1 line
2.5.0
Vignesh R
maintainerPATCH v2 1/10 sf: allocate cache aligned buffers to copy from flash
From: Ravi Babu <[email protected]>
Use memalign() with ARCH_DMA_MINALIGN to allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read.
--- common/cmd_sf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
common/cmd_sf.c +3 -3
@@ -223,7 +223,7 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset,if (end - buf >=200 ) scale = (end - buf) /100 ; - cmp_buf =malloc (flash->sector_size); + cmp_buf =memalign (ARCH_DMA_MINALIGN , flash->sector_size);if (cmp_buf) {ulong last_update =get_timer (0 );
@@ -484,12 +484,12 @@ static int do_spi_flash_test(int argc, char * const argv[])if (*argv[2 ] ==0 || *endp !=0 )return -1 ; - vbuf =malloc (len); + vbuf =memalign (ARCH_DMA_MINALIGN , len);if (!vbuf) {printf ("Cannot allocate memory (%lu bytes)\n" , len);return 1 ; } - buf =malloc (len); + buf =memalign (ARCH_DMA_MINALIGN , len);if (!buf) {free (vbuf);printf ("Cannot allocate memory (%lu bytes)\n" , len);
Signature · 1 line
2.5.0
PATCH v2 1/10 sf: allocate cache aligned buffers to copy from flash
Hi Simon,
Quoted 17 lines · Vignesh R
From: Ravi Babu <[email protected]>
Use
memalign()withARCH_DMA_MINALIGNto allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read.Signed-off-by Ravi Babu <[email protected]>Signed-off-by Vignesh R <[email protected]>--- common/cmd_sf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)common/cmd_sf.c +0
-0
common/cmd_sf.c static int spi_flash_update(struct spi_flash *flash, u32 offset, · line 226
Quoted 5 lines
common/cmd_sf.c +1
-1@@ -223,7 +223,7 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset,if (end - buf >=200 ) scale = (end - buf) /100 ; - cmp_buf =malloc (flash->sector_size); + cmp_buf =memalign (ARCH_DMA_MINALIGN , flash->sector_size);
I always have a confusion like align macro is never used on code memalign_simple()
Was it a typo missing or some thing?
Quoted 21 lines
common/cmd_sf.c +2
-3if (cmp_buf) {ulong last_update =get_timer (0 );@@ -484,12 +484,12 @@ static int do_spi_flash_test(int argc, char * const argv[])if (*argv[2 ] ==0 || *endp !=0 )return -1 ; - vbuf =malloc (len); + vbuf =memalign (ARCH_DMA_MINALIGN , len);if (!vbuf) {printf ("Cannot allocate memory (%lu bytes)\n" , len);return 1 ; } - buf =malloc (len); + buf =memalign (ARCH_DMA_MINALIGN , len);if (!buf) {free (vbuf);printf ("Cannot allocate memory (%lu bytes)\n" , len); --2.5.0
Quoted 4 lines
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
thanks!
Signature · 5 lines
Jagan | openedev. Sent with MailTrack
PATCH v2 1/10 sf: allocate cache aligned buffers to copy from flash
HI Jagan,
Quoted 22 lines · Jagan Teki
Hi Simon,
Quoted 18 lines · Vignesh R
From: Ravi Babu <[email protected]>
Use
memalign()withARCH_DMA_MINALIGNto allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read.Signed-off-by Ravi Babu <[email protected]>Signed-off-by Vignesh R <[email protected]>--- common/cmd_sf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)common/cmd_sf.c +0
-0@@ -223,7 +223,7 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset,
Quoted 8 lines
common/cmd_sf.c static int spi_flash_update(struct spi_flash *flash, u32 offset, · line 226
Quoted 4 lines
common/cmd_sf.c +1
-1if (end - buf >=200 ) scale = (end - buf) /100 ; - cmp_buf =malloc (flash->sector_size); + cmp_buf =memalign (ARCH_DMA_MINALIGN , flash->sector_size);I always have a confusion like align macro is never used on code
memalign_simple()
Was it a typo missing or some thing?
I don't understand what you are saying, sorry.
Quoted 23 lines
Quoted 23 lines
common/cmd_sf.c +2
-3if (cmp_buf) {ulong last_update =get_timer (0 );@@ -484,12 +484,12 @@ static int do_spi_flash_test(int argc, char * const argv[])if (*argv[2 ] ==0 || *endp !=0 )return -1 ; - vbuf =malloc (len); + vbuf =memalign (ARCH_DMA_MINALIGN , len);if (!vbuf) {printf ("Cannot allocate memory (%lu bytes)\n" , len);return 1 ; } - buf =malloc (len); + buf =memalign (ARCH_DMA_MINALIGN , len);if (!buf) {free (vbuf);printf ("Cannot allocate memory (%lu bytes)\n" , len); --2.5.0
Quoted 9 lines
Quoted 4 lines
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-bootthanks!
--
Jagan | openedev.
Regards,
Simon
PATCH v2 1/10 sf: allocate cache aligned buffers to copy from flash
Quoted 25 lines · Simon Glass
HI Jagan,
Quoted 22 lines · Jagan Teki
Hi Simon,
Quoted 18 lines · Vignesh R
From: Ravi Babu <[email protected]>
Use
memalign()withARCH_DMA_MINALIGNto allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read.Signed-off-by Ravi Babu <[email protected]>Signed-off-by Vignesh R <[email protected]>--- common/cmd_sf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)common/cmd_sf.c +0
-0@@ -223,7 +223,7 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset,
Quoted 4 lines
Quoted 4 lines
common/cmd_sf.c static int spi_flash_update(struct spi_flash *flash, u32 offset, · line 226
Quoted 4 lines
common/cmd_sf.c +1
-1if (end - buf >=200 ) scale = (end - buf) /100 ; - cmp_buf =malloc (flash->sector_size); + cmp_buf =memalign (ARCH_DMA_MINALIGN , flash->sector_size);
memalign is calling memalign_simple(size_t align, size_t bytes) in common/malloc_simple.c
except __libc_memalign
So, the align argument is never used on code, why?
Quoted 30 lines
Quoted 4 lines
I always have a confusion like align macro is never used on code
memalign_simple()
Was it a typo missing or some thing?I don't understand what you are saying, sorry.
Quoted 23 lines
Quoted 23 lines
common/cmd_sf.c +2
-3if (cmp_buf) {ulong last_update =get_timer (0 );@@ -484,12 +484,12 @@ static int do_spi_flash_test(int argc, char * const argv[])if (*argv[2 ] ==0 || *endp !=0 )return -1 ; - vbuf =malloc (len); + vbuf =memalign (ARCH_DMA_MINALIGN , len);if (!vbuf) {printf ("Cannot allocate memory (%lu bytes)\n" , len);return 1 ; } - buf =malloc (len); + buf =memalign (ARCH_DMA_MINALIGN , len);if (!buf) {free (vbuf);printf ("Cannot allocate memory (%lu bytes)\n" , len); --2.5.0
Quoted 4 lines
Quoted 4 lines
Quoted 4 lines
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
thanks!
Signature · 1 line
Jagan | openedev.
PATCH v2 1/10 sf: allocate cache aligned buffers to copy from flash
In reply to Jagan TekiQuoted 21 lines · Jagan Teki
Hi Simon,
Quoted 18 lines · Vignesh R
From: Ravi Babu <[email protected]>
Use
memalign()withARCH_DMA_MINALIGNto allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read.Signed-off-by Ravi Babu <[email protected]>Signed-off-by Vignesh R <[email protected]>--- common/cmd_sf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)common/cmd_sf.c +0
-0@@ -223,7 +223,7 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset,
Quoted 8 lines
common/cmd_sf.c static int spi_flash_update(struct spi_flash *flash, u32 offset, · line 226
Quoted 4 lines
common/cmd_sf.c +1
-1if (end - buf >=200 ) scale = (end - buf) /100 ; - cmp_buf =malloc (flash->sector_size); + cmp_buf =memalign (ARCH_DMA_MINALIGN , flash->sector_size);I always have a confusion like align macro is never used on code
memalign_simple()
Was it a typo missing or some thing?
Sorry? We always call memalign() rather than memalign_simple().
Signature · 8 lines
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PATCH v2 1/10 sf: allocate cache aligned buffers to copy from flash
Quoted 31 lines · Tom Rini
Quoted 21 lines · Jagan Teki
Hi Simon,
Quoted 18 lines · Vignesh R
From: Ravi Babu <[email protected]>
Use
memalign()withARCH_DMA_MINALIGNto allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read.Signed-off-by Ravi Babu <[email protected]>Signed-off-by Vignesh R <[email protected]>--- common/cmd_sf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)common/cmd_sf.c +0
-0@@ -223,7 +223,7 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset,Quoted 8 lines
common/cmd_sf.c static int spi_flash_update(struct spi_flash *flash, u32 offset, · line 226
Quoted 4 lines
common/cmd_sf.c +1
-1if (end - buf >=200 ) scale = (end - buf) /100 ; - cmp_buf =malloc (flash->sector_size); + cmp_buf =memalign (ARCH_DMA_MINALIGN , flash->sector_size);I always have a confusion like align macro is never used on code
memalign_simple()
Was it a typo missing or some thing?
Quoted 1 line
Sorry? We always call
memalign()rather thanmemalign_simple().
memalign() is calling memalign_simple() except __libc_memalign
Am I missing something here, because ARCH_DMA_MINALIGN is never used on memalign_simple()
thanks!
--
Jagan.
PATCH v2 1/10 sf: allocate cache aligned buffers to copy from flash
Quoted 32 lines · Jagan Teki
Quoted 31 lines · Tom Rini
Quoted 29 lines · Jagan Teki
Hi Simon,
Quoted 17 lines · Vignesh R
From: Ravi Babu <[email protected]>
Use
memalign()withARCH_DMA_MINALIGNto allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read.Signed-off-by Ravi Babu <[email protected]>Signed-off-by Vignesh R <[email protected]>--- common/cmd_sf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)common/cmd_sf.c +0
-0common/cmd_sf.c static int spi_flash_update(struct spi_flash *flash, u32 offset, · line 226
Quoted 5 lines
common/cmd_sf.c +1
-1@@ -223,7 +223,7 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset,if (end - buf >=200 ) scale = (end - buf) /100 ; - cmp_buf =malloc (flash->sector_size); + cmp_buf =memalign (ARCH_DMA_MINALIGN , flash->sector_size);I always have a confusion like align macro is never used on code
memalign_simple()
Was it a typo missing or some thing?
Quoted 6 lines
Quoted 1 line
Sorry? We always call
memalign()rather thanmemalign_simple().
memalign()is callingmemalign_simple()except__libc_memalignAm I missing something here, because
ARCH_DMA_MINALIGNis never used onmemalign_simple()
Yes, unless I'm missing something now, memalign_simple() is only used on CONFIG_SYS_MALLOC_SIMPLE which has some very specific use cases. We otherwise use memalign from common/dlmalloc.c..
Signature · 8 lines
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PATCH v2 1/10 sf: allocate cache aligned buffers to copy from flash
Hi,
Quoted 35 lines · Tom Rini
Quoted 34 lines · Jagan Teki
Quoted 32 lines · Tom Rini
Quoted 21 lines · Jagan Teki
Hi Simon,
Quoted 18 lines · Vignesh R
From: Ravi Babu <[email protected]>
Use
memalign()withARCH_DMA_MINALIGNto allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read.Signed-off-by Ravi Babu <[email protected]>Signed-off-by Vignesh R <[email protected]>--- common/cmd_sf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)common/cmd_sf.c +0
-0@@ -223,7 +223,7 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset,Quoted 8 lines
common/cmd_sf.c static int spi_flash_update(struct spi_flash *flash, u32 offset, · line 226
Quoted 4 lines
common/cmd_sf.c +1
-1if (end - buf >=200 ) scale = (end - buf) /100 ; - cmp_buf =malloc (flash->sector_size); + cmp_buf =memalign (ARCH_DMA_MINALIGN , flash->sector_size);I always have a confusion like align macro is never used on code
memalign_simple()
Was it a typo missing or some thing?Sorry? We always call
memalign()rather thanmemalign_simple().
Quoted 8 lines
Quoted 4 lines
memalign()is callingmemalign_simple()except__libc_memalignAm I missing something here, because
ARCH_DMA_MINALIGNis never used onmemalign_simple()Yes, unless I'm missing something now,
memalign_simple()is only used onCONFIG_SYS_MALLOC_SIMPLEwhich has some very specific use cases. We otherwise use memalign fromcommon/dlmalloc.c..
It looks like memalign_simple() should use
addr = ALIGN(gd->malloc_base + gd->malloc_ptr, align);
instead of:
addr = ALIGN(gd->malloc_base + gd->malloc_ptr, bytes);
Regards,
Simon
PATCH v2 1/10 sf: allocate cache aligned buffers to copy from flash
Quoted 47 lines · Simon Glass
Hi,
Quoted 35 lines · Tom Rini
Quoted 34 lines · Jagan Teki
Quoted 32 lines · Tom Rini
Quoted 21 lines · Jagan Teki
Hi Simon,
Quoted 18 lines · Vignesh R
From: Ravi Babu <[email protected]>
Use
memalign()withARCH_DMA_MINALIGNto allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read.Signed-off-by Ravi Babu <[email protected]>Signed-off-by Vignesh R <[email protected]>--- common/cmd_sf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)common/cmd_sf.c +0
-0@@ -223,7 +223,7 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset,Quoted 8 lines
common/cmd_sf.c static int spi_flash_update(struct spi_flash *flash, u32 offset, · line 226
Quoted 4 lines
common/cmd_sf.c +1
-1if (end - buf >=200 ) scale = (end - buf) /100 ; - cmp_buf =malloc (flash->sector_size); + cmp_buf =memalign (ARCH_DMA_MINALIGN , flash->sector_size);I always have a confusion like align macro is never used on code
memalign_simple()
Was it a typo missing or some thing?Sorry? We always call
memalign()rather thanmemalign_simple().Quoted 8 lines
Quoted 4 lines
memalign()is callingmemalign_simple()except__libc_memalignAm I missing something here, because
ARCH_DMA_MINALIGNis never used onmemalign_simple()Yes, unless I'm missing something now,
memalign_simple()is only used onCONFIG_SYS_MALLOC_SIMPLEwhich has some very specific use cases. We otherwise use memalign fromcommon/dlmalloc.c..
Quoted 7 lines
It looks like
memalign_simple()should useaddr = ALIGN(gd->malloc_base + gd->malloc_ptr, align);instead of:
addr = ALIGN(gd->malloc_base + gd->malloc_ptr, bytes);
I think we can do the requested bytes as well like
new_ptr = ALIGN(addr + bytes, align);
thanks!
Signature · 1 line
Jagan | openedev.
PATCH v2 1/10 sf: allocate cache aligned buffers to copy from flash
In reply to Simon GlassQuoted 47 lines · Simon Glass
Hi,
Quoted 35 lines · Tom Rini
Quoted 34 lines · Jagan Teki
Quoted 32 lines · Tom Rini
Quoted 21 lines · Jagan Teki
Hi Simon,
Quoted 18 lines · Vignesh R
From: Ravi Babu <[email protected]>
Use
memalign()withARCH_DMA_MINALIGNto allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read.Signed-off-by Ravi Babu <[email protected]>Signed-off-by Vignesh R <[email protected]>--- common/cmd_sf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)common/cmd_sf.c +0
-0@@ -223,7 +223,7 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset,Quoted 8 lines
common/cmd_sf.c static int spi_flash_update(struct spi_flash *flash, u32 offset, · line 226
Quoted 4 lines
common/cmd_sf.c +1
-1if (end - buf >=200 ) scale = (end - buf) /100 ; - cmp_buf =malloc (flash->sector_size); + cmp_buf =memalign (ARCH_DMA_MINALIGN , flash->sector_size);I always have a confusion like align macro is never used on code
memalign_simple()
Was it a typo missing or some thing?Sorry? We always call
memalign()rather thanmemalign_simple().Quoted 8 lines
Quoted 4 lines
memalign()is callingmemalign_simple()except__libc_memalignAm I missing something here, because
ARCH_DMA_MINALIGNis never used onmemalign_simple()Yes, unless I'm missing something now,
memalign_simple()is only used onCONFIG_SYS_MALLOC_SIMPLEwhich has some very specific use cases. We otherwise use memalign fromcommon/dlmalloc.c..
Quoted 7 lines
It looks like
memalign_simple()should useaddr = ALIGN(gd->malloc_base + gd->malloc_ptr, align);instead of:
addr = ALIGN(gd->malloc_base + gd->malloc_ptr, bytes);
Now we're getting somewhere, good spotting Jagan!
Signature · 8 lines
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PATCH v2 1/10 sf: allocate cache aligned buffers to copy from flash
Hi,
Quoted 52 lines · Tom Rini
Quoted 51 lines · Simon Glass
Hi,
Quoted 35 lines · Tom Rini
Quoted 34 lines · Jagan Teki
Quoted 32 lines · Tom Rini
Quoted 21 lines · Jagan Teki
Hi Simon,
Quoted 18 lines · Vignesh R
From: Ravi Babu <[email protected]>
Use
memalign()withARCH_DMA_MINALIGNto allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read.Signed-off-by Ravi Babu <[email protected]>Signed-off-by Vignesh R <[email protected]>--- common/cmd_sf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)common/cmd_sf.c +0
-0@@ -223,7 +223,7 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset,Quoted 8 lines
common/cmd_sf.c static int spi_flash_update(struct spi_flash *flash, u32 offset, · line 226
Quoted 4 lines
common/cmd_sf.c +1
-1if (end - buf >=200 ) scale = (end - buf) /100 ; - cmp_buf =malloc (flash->sector_size); + cmp_buf =memalign (ARCH_DMA_MINALIGN , flash->sector_size);I always have a confusion like align macro is never used on code
memalign_simple()
Was it a typo missing or some thing?Sorry? We always call
memalign()rather thanmemalign_simple().Quoted 8 lines
Quoted 4 lines
memalign()is callingmemalign_simple()except__libc_memalignAm I missing something here, because
ARCH_DMA_MINALIGNis never used onmemalign_simple()Yes, unless I'm missing something now,
memalign_simple()is only used onCONFIG_SYS_MALLOC_SIMPLEwhich has some very specific use cases. We otherwise use memalign fromcommon/dlmalloc.c..It looks like
memalign_simple()should useaddr = ALIGN(gd->malloc_base + gd->malloc_ptr, align);
Quoted 8 lines
Quoted 3 lines
instead of:
addr = ALIGN(gd->malloc_base + gd->malloc_ptr, bytes);Now we're getting somewhere, good spotting Jagan!
--
Tom
Is that to catch the case where bytes is not a multiple of align? Why would that be and is it correct to 'waste' those bytes?
I'll send a patch and perhaps we can continue the discussion there.
Regards,
Simon
Vignesh R
maintainerPATCH v2 2/10 env: use cache line aligned memory for flash read
In reply to Vignesh RFrom: Ravi Babu <[email protected]>
Use memalign() with ARCH_DMA_MINALIGN to allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read.
--- common/env_sf.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
common/env_sf.c +6 -5
@@ -79,7 +79,7 @@ int saveenv(void)if (CONFIG_ENV_SECT_SIZE >CONFIG_ENV_SIZE ) { saved_size =CONFIG_ENV_SECT_SIZE -CONFIG_ENV_SIZE ; saved_offset = env_new_offset +CONFIG_ENV_SIZE ; - saved_buffer =malloc (saved_size); + saved_buffer =memalign (ARCH_DMA_MINALIGN , saved_size);if (!saved_buffer) { ret =1 ; goto done;
@@ -142,9 +142,10 @@ void env_relocate_spec(void)env_t *tmp_env2 =NULL ;env_t *ep =NULL ; - tmp_env1 = (env_t *)malloc (CONFIG_ENV_SIZE ); - tmp_env2 = (env_t *)malloc (CONFIG_ENV_SIZE ); - + tmp_env1 = (env_t *)memalign (ARCH_DMA_MINALIGN , +CONFIG_ENV_SIZE ); + tmp_env2 = (env_t *)memalign (ARCH_DMA_MINALIGN , +CONFIG_ENV_SIZE );if (!tmp_env1 || !tmp_env2) {set_default_env ("!malloc() failed" ); goto out;
@@ -295,7 +296,7 @@ void env_relocate_spec(void)int ret;char *buf =NULL ; - buf = (char *)malloc (CONFIG_ENV_SIZE ); + buf = (char *)memalign (ARCH_DMA_MINALIGN ,CONFIG_ENV_SIZE ); env_flash =spi_flash_probe (CONFIG_ENV_SPI_BUS ,CONFIG_ENV_SPI_CS ,CONFIG_ENV_SPI_MAX_HZ ,CONFIG_ENV_SPI_MODE );if (!env_flash) {
Signature · 1 line
2.5.0
PATCH v2 2/10 env: use cache line aligned memory for flash read
Quoted 8 lines · Vignesh R
From: Ravi Babu <[email protected]>
Use
memalign()withARCH_DMA_MINALIGNto allocate read buffers. This is required because, flash drivers may use DMA for read operations and may have to invalidate the buffer before read.Signed-off-by Ravi Babu <[email protected]>Signed-off-by Vignesh R <[email protected]>
Signature · 8 lines
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Vignesh R
maintainerPATCH v2 3/10 ARM: AM43xx: Add support for disabling clocks in uboot
In reply to Vignesh RFrom: Kishon Vijay Abraham I <[email protected]>
Add do_disable_clocks() to disable clock domains and module clocks. These clocks are enabled using do_enable_clocks().
--- arch/arm/cpu/armv7/am33xx/clock.c | 52 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-am33xx/clock.h | 1 + 2 files changed, 53 insertions(+)
arch/arm/cpu/armv7/am33xx/clock.c +52 -0
@@ -144,6 +144,33 @@ static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,wait_for_clk_enable (clkctrl_addr); } +static inline void wait_for_clk_disable (u32 *clkctrl_addr) +{ +u32 clkctrl, idlest =MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL ; +u32 bound =LDELAY ; + +while ((idlest !=MODULE_CLKCTRL_IDLEST_DISABLED )) { + clkctrl =readl (clkctrl_addr); + idlest = (clkctrl &MODULE_CLKCTRL_IDLEST_MASK ) >> +MODULE_CLKCTRL_IDLEST_SHIFT ; +if (--bound ==0 ) { +printf ("Clock disable failed for 0x%p idlest 0x%x\n" , + clkctrl_addr, clkctrl); +return ; + } + } +} +static inline void disable_clock_module (u32 *const clkctrl_addr, +u32 wait_for_disable) +{ +clrsetbits_le32 (clkctrl_addr,MODULE_CLKCTRL_MODULEMODE_MASK , +MODULE_CLKCTRL_MODULEMODE_SW_DISABLE << +MODULE_CLKCTRL_MODULEMODE_SHIFT ); +debug ("Disable clock module - %p\n" , clkctrl_addr); +if (wait_for_disable) +wait_for_clk_disable (clkctrl_addr); +} +static inline void enable_clock_domain (u32 *const clkctrl_reg,u32 enable_mode) { clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
@@ -151,6 +178,14 @@ static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)debug ("Enable clock domain - %p\n" , clkctrl_reg); } +static inline void disable_clock_domain (u32 *const clkctrl_reg) +{ +clrsetbits_le32 (clkctrl_reg,CD_CLKCTRL_CLKTRCTRL_MASK , +CD_CLKCTRL_CLKTRCTRL_SW_SLEEP << +CD_CLKCTRL_CLKTRCTRL_SHIFT ); +debug ("Disable clock domain - %p\n" , clkctrl_reg); +} +void do_enable_clocks (u32 *const *clk_domains,u32 *const *clk_modules_explicit_en,u8 wait_for_enable) {
@@ -170,6 +205,23 @@ void do_enable_clocks(u32 *const *clk_domains, }; } +void do_disable_clocks (u32 *const *clk_domains, +u32 *const *clk_modules_disable, +u8 wait_for_disable) +{ +u32 i, max =100 ; + + +/* Clock modules that need to be put in SW_DISABLE */ +for (i =0 ; (i < max) && clk_modules_disable[i]; i++) +disable_clock_module (clk_modules_disable[i], + wait_for_disable); + +/* Put the clock domains in SW_SLEEP mode */ +for (i =0 ; (i < max) && clk_domains[i]; i++) +disable_clock_domain (clk_domains[i]); +} +/* * Before scaling up the clocks we need to have the PMIC scale up the * voltages first. This will be dependent on which PMIC is in use
arch/arm/include/asm/arch-am33xx/clock.h +1 -0
@@ -112,5 +112,6 @@ void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);void prcm_init (void );void enable_basic_clocks (void );void do_enable_clocks (u32 *const *,u32 *const *,u8 ); +void do_disable_clocks (u32 *const *,u32 *const *,u8 );#endif
Signature · 1 line
2.5.0
PATCH v2 3/10 ARM: AM43xx: Add support for disabling clocks in uboot
Quoted 8 lines · Vignesh R
From: Kishon Vijay Abraham I <[email protected]>
Add
do_disable_clocks()to disable clock domains and module clocks. These clocks are enabled usingdo_enable_clocks().Signed-off-by Kishon Vijay Abraham I <[email protected]>Signed-off-by Vignesh R <[email protected]>---
Quoted 99 lines
arch/arm/cpu/armv7/am33xx/clock.c | 52 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-am33xx/clock.h | 1 + 2 files changed, 53 insertions(+)arch/arm/cpu/armv7/am33xx/clock.c +52
-0@@ -144,6 +144,33 @@ static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,wait_for_clk_enable (clkctrl_addr); } +static inline void wait_for_clk_disable (u32 *clkctrl_addr) +{ +u32 clkctrl, idlest =MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL ; +u32 bound =LDELAY ; + +while ((idlest !=MODULE_CLKCTRL_IDLEST_DISABLED )) { + clkctrl =readl (clkctrl_addr); + idlest = (clkctrl &MODULE_CLKCTRL_IDLEST_MASK ) >> +MODULE_CLKCTRL_IDLEST_SHIFT ; +if (--bound ==0 ) { +printf ("Clock disable failed for 0x%p idlest 0x%x\n" , + clkctrl_addr, clkctrl); +return ; + } + } +} +static inline void disable_clock_module (u32 *const clkctrl_addr, +u32 wait_for_disable) +{ +clrsetbits_le32 (clkctrl_addr,MODULE_CLKCTRL_MODULEMODE_MASK , +MODULE_CLKCTRL_MODULEMODE_SW_DISABLE << +MODULE_CLKCTRL_MODULEMODE_SHIFT ); +debug ("Disable clock module - %p\n" , clkctrl_addr); +if (wait_for_disable) +wait_for_clk_disable (clkctrl_addr); +} +static inline void enable_clock_domain (u32 *const clkctrl_reg,u32 enable_mode) { clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,@@ -151,6 +178,14 @@ static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)debug ("Enable clock domain - %p\n" , clkctrl_reg); } +static inline void disable_clock_domain (u32 *const clkctrl_reg) +{ +clrsetbits_le32 (clkctrl_reg,CD_CLKCTRL_CLKTRCTRL_MASK , +CD_CLKCTRL_CLKTRCTRL_SW_SLEEP << +CD_CLKCTRL_CLKTRCTRL_SHIFT ); +debug ("Disable clock domain - %p\n" , clkctrl_reg); +} +void do_enable_clocks (u32 *const *clk_domains,u32 *const *clk_modules_explicit_en,u8 wait_for_enable) {@@ -170,6 +205,23 @@ void do_enable_clocks(u32 *const *clk_domains, }; } +void do_disable_clocks (u32 *const *clk_domains, +u32 *const *clk_modules_disable, +u8 wait_for_disable) +{ +u32 i, max =100 ; + + +/* Clock modules that need to be put in SW_DISABLE */ +for (i =0 ; (i < max) && clk_modules_disable[i]; i++) +disable_clock_module (clk_modules_disable[i], + wait_for_disable); + +/* Put the clock domains in SW_SLEEP mode */ +for (i =0 ; (i < max) && clk_domains[i]; i++) +disable_clock_domain (clk_domains[i]); +} +/* * Before scaling up the clocks we need to have the PMIC scale up the * voltages first. This will be dependent on which PMIC is in use arch/arm/include/asm/arch-am33xx/clock.h +1
-1@@ -112,5 +112,6 @@ void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);void prcm_init (void );void enable_basic_clocks (void );void do_enable_clocks (u32 *const *,u32 *const *,u8 ); +void do_disable_clocks (u32 *const *,u32 *const *,u8 );#endif --2.5.0
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Signature · 1 line
Jagan | openedev.
Vignesh R
maintainerPATCH v2 4/10 ARM: OMAP5: Add support for disabling clocks in uboot
In reply to Vignesh RFrom: Kishon Vijay Abraham I <[email protected]>
Add do_disable_clocks() to disable clock domains and module clocks. These clocks are enabled using do_enable_clocks().
--- arch/arm/cpu/armv7/omap-common/clocks-common.c | 53 ++++++++++++++++++++++++++ arch/arm/include/asm/omap_common.h | 4 ++ 2 files changed, 57 insertions(+)
arch/arm/cpu/armv7/omap-common/clocks-common.c +53 -0
@@ -648,6 +648,14 @@ static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)debug ("Enable clock domain - %x\n" , clkctrl_reg); } +static inline void disable_clock_domain (u32 const clkctrl_reg) +{ +clrsetbits_le32 (clkctrl_reg,CD_CLKCTRL_CLKTRCTRL_MASK , +CD_CLKCTRL_CLKTRCTRL_SW_SLEEP << +CD_CLKCTRL_CLKTRCTRL_SHIFT ); +debug ("Disable clock domain - %x\n" , clkctrl_reg); +} +static inline void wait_for_clk_enable (u32 clkctrl_addr) {u32 clkctrl, idlest =MODULE_CLKCTRL_IDLEST_DISABLED ;
@@ -677,6 +685,34 @@ static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,wait_for_clk_enable (clkctrl_addr); } +static inline void wait_for_clk_disable (u32 clkctrl_addr) +{ +u32 clkctrl, idlest =MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL ; +u32 bound =LDELAY ; + +while ((idlest !=MODULE_CLKCTRL_IDLEST_DISABLED )) { + clkctrl =readl (clkctrl_addr); + idlest = (clkctrl &MODULE_CLKCTRL_IDLEST_MASK ) >> +MODULE_CLKCTRL_IDLEST_SHIFT ; +if (--bound ==0 ) { +printf ("Clock disable failed for 0x%x idlest 0x%x\n" , + clkctrl_addr, clkctrl); +return ; + } + } +} + +static inline void disable_clock_module (u32 const clkctrl_addr, +u32 wait_for_disable) +{ +clrsetbits_le32 (clkctrl_addr,MODULE_CLKCTRL_MODULEMODE_MASK , +MODULE_CLKCTRL_MODULEMODE_SW_DISABLE << +MODULE_CLKCTRL_MODULEMODE_SHIFT ); +debug ("Disable clock module - %x\n" , clkctrl_addr); +if (wait_for_disable) +wait_for_clk_disable (clkctrl_addr); +} +void freq_update_core (void ) {u32 freq_config1 =0 ;
@@ -800,6 +836,23 @@ void do_enable_clocks(u32 const *clk_domains, } } +void do_disable_clocks (u32 const *clk_domains, +u32 const *clk_modules_disable, +u8 wait_for_disable) +{ +u32 i, max =100 ; + + +/* Clock modules that need to be put in SW_DISABLE */ +for (i =0 ; (i < max) && clk_modules_disable[i]; i++) +disable_clock_module (clk_modules_disable[i], + wait_for_disable); + +/* Put the clock domains in SW_SLEEP mode */ +for (i =0 ; (i < max) && clk_domains[i]; i++) +disable_clock_domain (clk_domains[i]); +} +void prcm_init (void ) {switch (omap_hw_init_context ()) {
arch/arm/include/asm/omap_common.h +4 -0
@@ -575,6 +575,10 @@ void do_enable_clocks(u32 const *clk_domains,u32 const *clk_modules_explicit_en, u8 wait_for_enable); +void do_disable_clocks (u32 const *clk_domains, +u32 const *clk_modules_disable, +u8 wait_for_disable); +void setup_post_dividers (u32 const base,const struct dpll_params *params);u32 omap_ddr_clk (void );
Signature · 1 line
2.5.0
PATCH v2 4/10 ARM: OMAP5: Add support for disabling clocks in uboot
Quoted 8 lines · Vignesh R
From: Kishon Vijay Abraham I <[email protected]>
Add
do_disable_clocks()to disable clock domains and module clocks. These clocks are enabled usingdo_enable_clocks().Signed-off-by Kishon Vijay Abraham I <[email protected]>Signed-off-by Vignesh R <[email protected]>---
Quoted 59 lines
arch/arm/cpu/armv7/omap-common/clocks-common.c | 53 ++++++++++++++++++++++++++ arch/arm/include/asm/omap_common.h | 4 ++ 2 files changed, 57 insertions(+)arch/arm/cpu/armv7/omap-common/clocks-common.c +36
-0@@ -648,6 +648,14 @@ static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)debug ("Enable clock domain - %x\n" , clkctrl_reg); } +static inline void disable_clock_domain (u32 const clkctrl_reg) +{ +clrsetbits_le32 (clkctrl_reg,CD_CLKCTRL_CLKTRCTRL_MASK , +CD_CLKCTRL_CLKTRCTRL_SW_SLEEP << +CD_CLKCTRL_CLKTRCTRL_SHIFT ); +debug ("Disable clock domain - %x\n" , clkctrl_reg); +} +static inline void wait_for_clk_enable (u32 clkctrl_addr) {u32 clkctrl, idlest =MODULE_CLKCTRL_IDLEST_DISABLED ;@@ -677,6 +685,34 @@ static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,wait_for_clk_enable (clkctrl_addr); } +static inline void wait_for_clk_disable (u32 clkctrl_addr) +{ +u32 clkctrl, idlest =MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL ; +u32 bound =LDELAY ; + +while ((idlest !=MODULE_CLKCTRL_IDLEST_DISABLED )) { + clkctrl =readl (clkctrl_addr); + idlest = (clkctrl &MODULE_CLKCTRL_IDLEST_MASK ) >> +MODULE_CLKCTRL_IDLEST_SHIFT ; +if (--bound ==0 ) { +printf ("Clock disable failed for 0x%x idlest 0x%x\n" , + clkctrl_addr, clkctrl); +return ; + } + } +} + +static inline void disable_clock_module (u32 const clkctrl_addr, +u32 wait_for_disable) +{ +clrsetbits_le32 (clkctrl_addr,MODULE_CLKCTRL_MODULEMODE_MASK , +MODULE_CLKCTRL_MODULEMODE_SW_DISABLE << +MODULE_CLKCTRL_MODULEMODE_SHIFT ); +debug ("Disable clock module - %x\n" , clkctrl_addr); +if (wait_for_disable) +wait_for_clk_disable (clkctrl_addr); +} +void freq_update_core (void ) {u32 freq_config1 =0 ;
arch/arm/cpu/armv7/omap-common/clocks-common.c void do_enable_clocks(u32 const *clk_domains, · line 843
Quoted 8 lines
arch/arm/cpu/armv7/omap-common/clocks-common.c +5
-0@@ -800,6 +836,23 @@ void do_enable_clocks(u32 const *clk_domains, } } +void do_disable_clocks (u32 const *clk_domains, +u32 const *clk_modules_disable, +u8 wait_for_disable) +{ +u32 i, max =100 ;
Why is this 100 max value?
Quoted 33 lines
arch/arm/cpu/armv7/omap-common/clocks-common.c +12
-0+ + +/* Clock modules that need to be put in SW_DISABLE */ +for (i =0 ; (i < max) && clk_modules_disable[i]; i++) +disable_clock_module (clk_modules_disable[i], + wait_for_disable); + +/* Put the clock domains in SW_SLEEP mode */ +for (i =0 ; (i < max) && clk_domains[i]; i++) +disable_clock_domain (clk_domains[i]); +} +void prcm_init (void ) {switch (omap_hw_init_context ()) {arch/arm/include/asm/omap_common.h +4
-1@@ -575,6 +575,10 @@ void do_enable_clocks(u32 const *clk_domains,u32 const *clk_modules_explicit_en, u8 wait_for_enable); +void do_disable_clocks (u32 const *clk_domains, +u32 const *clk_modules_disable, +u8 wait_for_disable); +void setup_post_dividers (u32 const base,const struct dpll_params *params);u32 omap_ddr_clk (void ); --2.5.0
Quoted 4 lines
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Signature · 1 line
Jagan | openedev.
Vignesh R
maintainerPATCH v2 5/10 ARM: OMAP5: Add functions to enable and disable EDMA3 clocks
In reply to Vignesh RAdds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks.
--- arch/arm/cpu/armv7/omap5/hw_data.c | 41 ++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 4 ++++ arch/arm/include/asm/omap_common.h | 9 ++++++++ 3 files changed, 54 insertions(+)
arch/arm/cpu/armv7/omap5/hw_data.c +41 -0
@@ -565,6 +565,47 @@ void enable_basic_uboot_clocks(void) 1); } +#ifdef CONFIG_TI_EDMA3 +void enable_edma3_clocks (void ) +{ +u32 const clk_domains_edma3[] = { +0 + }; + +u32 const clk_modules_hw_auto_edma3[] = { + (*prcm)->cm_l3main1_tptc1_clkctrl, + (*prcm)->cm_l3main1_tptc2_clkctrl, +0 + }; + +u32 const clk_modules_explicit_en_edma3[] = { +0 + }; + +do_enable_clocks (clk_domains_edma3, + clk_modules_hw_auto_edma3, + clk_modules_explicit_en_edma3, +1 ); +} + +void disable_edma3_clocks (void ) +{ +u32 const clk_domains_edma3[] = { +0 + }; + +u32 const clk_modules_disable_edma3[] = { + (*prcm)->cm_l3main1_tptc1_clkctrl, + (*prcm)->cm_l3main1_tptc2_clkctrl, +0 + }; + +do_disable_clocks (clk_domains_edma3, + clk_modules_disable_edma3, +1 ); +} +#endif +const struct ctrl_ioregs ioregs_omap5430 = { .ctrl_ddrch =DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN , .ctrl_lpddr2ch =DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN ,
arch/arm/cpu/armv7/omap5/prcm-regs.c +4 -0
@@ -989,4 +989,8 @@ struct prcm_regs const dra7xx_prcm = { .prm_abbldo_mpu_setup = 0x4AE07DDC, .prm_abbldo_mpu_ctrl = 0x4AE07DE0, + +/*l3main1 edma*/ + .cm_l3main1_tptc1_clkctrl = 0x4a008778, + .cm_l3main1_tptc2_clkctrl = 0x4a008780, };
arch/arm/include/asm/omap_common.h +9 -0
@@ -349,6 +349,10 @@ struct prcm_regs {/* IPU */ u32 cm_ipu_clkstctrl;u32 cm_ipu_i2c5_clkctrl; + +/*l3main1 edma*/ +u32 cm_l3main1_tptc1_clkctrl; +u32 cm_l3main1_tptc2_clkctrl; };struct omap_sys_ctrl_regs {
@@ -598,6 +602,11 @@ void recalibrate_iodelay(void);void omap_smc1 (u32 service,u32 val); +#ifdef CONFIG_TI_EDMA3 +void enable_edma3_clocks (void ); +void disable_edma3_clocks (void ); +#endif +/* ABB */ #define OMAP_ABB_NOMINAL_OPP 0#define OMAP_ABB_FAST_OPP 1
Signature · 1 line
2.5.0
PATCH v2 5/10 ARM: OMAP5: Add functions to enable and disable EDMA3 clocks
Quoted 4 lines · Vignesh R
Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks.
Signed-off-by Vignesh R <[email protected]>
[snip]
Quoted 16 lines
arch/arm/include/asm/omap_common.h +4
-0@@ -349,6 +349,10 @@ struct prcm_regs {/* IPU */ u32 cm_ipu_clkstctrl;u32 cm_ipu_i2c5_clkctrl; + +/*l3main1 edma*/ +u32 cm_l3main1_tptc1_clkctrl; +u32 cm_l3main1_tptc2_clkctrl; };struct omap_sys_ctrl_regs {
arch/arm/include/asm/omap_common.h void recalibrate_iodelay(void); · line 608
Quoted 7 lines
arch/arm/include/asm/omap_common.h +4
-0@@ -598,6 +602,11 @@ void recalibrate_iodelay(void);void omap_smc1 (u32 service,u32 val); +#ifdef CONFIG_TI_EDMA3 +void enable_edma3_clocks (void ); +void disable_edma3_clocks (void ); +#endif
No #ifdef/#endif in headers please.
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Vignesh R
maintainerPATCH v2 6/10 ARM: AM43XX: Add functions to enable and disable EDMA3 clocks
In reply to Vignesh RAdds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks.
--- arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 36 ++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)
arch/arm/cpu/armv7/am33xx/clock_am43xx.c +36 -0
@@ -134,3 +134,39 @@ void enable_basic_clocks(void)/* For OPP100 the mac clock should be /5. */ writel (0x4 , &cmdpll->clkselmacclk); } + +#ifdef CONFIG_TI_EDMA3 +void enable_edma3_clocks (void ) +{ +u32 *const clk_domains_edma3[] = { +0 + }; + +u32 *const clk_modules_explicit_en_edma3[] = { + &cmper->tpccclkctrl, + &cmper->tptc0clkctrl, +0 + }; + +do_enable_clocks (clk_domains_edma3, + clk_modules_explicit_en_edma3, +1 ); +} + +void disable_edma3_clocks (void ) +{ +u32 *const clk_domains_edma3[] = { +0 + }; + +u32 *const clk_modules_disable_edma3[] = { + &cmper->tpccclkctrl, + &cmper->tptc0clkctrl, +0 + }; + +do_disable_clocks (clk_domains_edma3, + clk_modules_disable_edma3, +1 ); +} +#endif
Signature · 1 line
2.5.0
PATCH v2 6/10 ARM: AM43XX: Add functions to enable and disable EDMA3 clocks
Quoted 4 lines · Vignesh R
Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks.
Signed-off-by Vignesh R <[email protected]>
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PATCH v2 6/10 ARM: AM43XX: Add functions to enable and disable EDMA3 clocks
Quoted 8 lines · Tom Rini
Quoted 4 lines · Vignesh R
Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks.
Signed-off-by Vignesh R <[email protected]>Reviewed-by Tom Rini <[email protected]>
thanks!
Signature · 1 line
Jagan | openedev.
Vignesh R
maintainerPATCH v2 7/10 sf: ops: Add spi_flash_copy_mmap function
In reply to Vignesh RFrom: Tom Rini <[email protected]>
When doing a memory mapped copy we may have DMA available and thus need to have this copy abstracted so that the driver can do it, rather than a simple memcpy.
--- drivers/mtd/spi/sf_ops.c | 8 +++++++- include/spi.h | 3 +++ 2 files changed, 10 insertions(+), 1 deletion(-)
drivers/mtd/spi/sf_ops.c +7 -1
@@ -14,6 +14,7 @@#include <spi.h> #include <spi_flash.h> #include <watchdog.h> +#include <linux/compiler.h> #include "sf_internal.h"
@@ -378,6 +379,11 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,return ret; } +void __weak spi_flash_copy_mmap (void *data,void *offset,size_t len) +{ +memcpy (data, offset, len); +} +int spi_flash_cmd_read_ops (struct spi_flash *flash,u32 offset,size_t len,void *data) {
@@ -394,7 +400,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,return ret; }spi_xfer (flash->spi,0 ,NULL ,NULL ,SPI_XFER_MMAP ); -memcpy (data, flash->memory_map + offset, len); +spi_flash_copy_mmap (data, flash->memory_map + offset, len);spi_xfer (flash->spi,0 ,NULL ,NULL ,SPI_XFER_MMAP_END );spi_release_bus (flash->spi);return 0 ;
include/spi.h +3 -0
@@ -272,6 +272,9 @@ int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen);int spi_xfer (struct spi_slave *slave,unsigned int bitlen,const void *dout,void *din,unsigned long flags); +/* Copy memory mapped data */ +void spi_flash_copy_mmap (void *data,void *offset,size_t len); +/** * Determine if a SPI chipselect is valid. * This function is provided by the board if the low-level SPI driver
Signature · 1 line
2.5.0
PATCH v2 7/10 sf: ops: Add spi_flash_copy_mmap function
Quoted 9 lines · Vignesh R
From: Tom Rini <[email protected]>
When doing a memory mapped copy we may have DMA available and thus need to have this copy abstracted so that the driver can do it, rather than a simple memcpy.
Signed-off-by Tom Rini <[email protected]>Signed-off-by Vignesh R <[email protected]>---
Quoted 54 lines
drivers/mtd/spi/sf_ops.c | 8 +++++++- include/spi.h | 3 +++ 2 files changed, 10 insertions(+), 1 deletion(-)drivers/mtd/spi/sf_ops.c +7
-1@@ -14,6 +14,7 @@#include <spi.h> #include <spi_flash.h> #include <watchdog.h> +#include <linux/compiler.h> #include "sf_internal.h" @@ -378,6 +379,11 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,return ret; } +void __weak spi_flash_copy_mmap (void *data,void *offset,size_t len) +{ +memcpy (data, offset, len); +} +int spi_flash_cmd_read_ops (struct spi_flash *flash,u32 offset,size_t len,void *data) {@@ -394,7 +400,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,return ret; }spi_xfer (flash->spi,0 ,NULL ,NULL ,SPI_XFER_MMAP ); -memcpy (data, flash->memory_map + offset, len); +spi_flash_copy_mmap (data, flash->memory_map + offset, len);spi_xfer (flash->spi,0 ,NULL ,NULL ,SPI_XFER_MMAP_END );spi_release_bus (flash->spi);return 0 ;include/spi.h +3
-1@@ -272,6 +272,9 @@ int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen);int spi_xfer (struct spi_slave *slave,unsigned int bitlen,const void *dout,void *din,unsigned long flags); +/* Copy memory mapped data */ +void spi_flash_copy_mmap (void *data,void *offset,size_t len); +/** * Determine if a SPI chipselect is valid. * This function is provided by the board if the low-level SPI driver -- 2.5.0
Quoted 4 lines
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Signature · 1 line
Jagan | openedev.
Vignesh R
maintainerPATCH v2 8/10 dma: ti-edma3: Add helper function to support edma3 transfer
In reply to Vignesh R--- arch/arm/include/asm/ti-common/ti-edma3.h | 2 + drivers/dma/ti-edma3.c | 78 +++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+)
arch/arm/include/asm/ti-common/ti-edma3.h +2 -0
@@ -117,5 +117,7 @@ void edma3_set_src_addr(u32 base, int slot, u32 src);void edma3_set_transfer_params (u32 base,int slot,int acnt,int bcnt,int ccnt,u16 bcnt_rld,enum edma3_sync_dimension sync_mode); +void edma3_transfer (unsigned long edma3_base_addr,unsigned int + edma_slot_num,void *dst,void *src,size_t len);#endif
drivers/dma/ti-edma3.c +78 -0
81 lines not on this page · raw message
Signature · 1 line
2.5.0
PATCH v2 8/10 dma: ti-edma3: Add helper function to support edma3 transfer
Quoted 1 line · Vignesh R
Signed-off-by Vignesh R <[email protected]>
Quoted 60 lines
--- arch/arm/include/asm/ti-common/ti-edma3.h | 2 + drivers/dma/ti-edma3.c | 78 +++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+)arch/arm/include/asm/ti-common/ti-edma3.h +2
-0@@ -117,5 +117,7 @@ void edma3_set_src_addr(u32 base, int slot, u32 src);void edma3_set_transfer_params (u32 base,int slot,int acnt,int bcnt,int ccnt,u16 bcnt_rld,enum edma3_sync_dimension sync_mode); +void edma3_transfer (unsigned long edma3_base_addr,unsigned int + edma_slot_num,void *dst,void *src,size_t len);#endif drivers/dma/ti-edma3.c +35
-0@@ -382,3 +382,81 @@ void qedma3_stop(u32 base, struct edma3_channel_config *cfg)/* Clear the channel map */ __raw_writel (0 , base +EDMA3_QCHMAP (cfg->chnum)); } + +void edma3_transfer (unsigned long edma3_base_addr,unsigned int + edma_slot_num,void *dst,void *src,size_t len) +{ +struct edma3_slot_config slot; +struct edma3_channel_config edma_channel; +int b_cnt_value =1 ; +int rem_bytes =0 ; +int a_cnt_value = len; +unsigned int addr = (unsigned int ) (dst); +unsigned int max_acnt =0x7FFFU ; + +if (len > max_acnt) { + b_cnt_value = (len / max_acnt); + rem_bytes = (len % max_acnt); + a_cnt_value = max_acnt; + } + + slot.opt =0 ; + slot.src = ((unsigned int ) src); + slot.acnt = a_cnt_value; + slot.bcnt = b_cnt_value; + slot.ccnt =1 ; + slot.src_bidx = a_cnt_value; + slot.dst_bidx = a_cnt_value; + slot.src_cidx =0 ; + slot.dst_cidx =0 ; + slot.link =EDMA3_PARSET_NULL_LINK ; + slot.bcntrld =0 ; + slot.opt =EDMA3_SLOPT_TRANS_COMP_INT_ENB | +EDMA3_SLOPT_COMP_CODE (0 ) | +EDMA3_SLOPT_STATIC |EDMA3_SLOPT_AB_SYNC ; + +edma3_slot_configure (edma3_base_addr, edma_slot_num, &slot); + edma_channel.slot = edma_slot_num;
drivers/dma/ti-edma3.c void qedma3_stop(u32 base, struct edma3_channel_config *cfg) · line 429
Quoted 10 lines
drivers/dma/ti-edma3.c +10
-0+ edma_channel.chnum =0 ; + edma_channel.complete_code =0 ; +/* set event trigger to dst update */ + edma_channel.trigger_slot_word =EDMA3_TWORD (dst); + +qedma3_start (edma3_base_addr, &edma_channel); +edma3_set_dest_addr (edma3_base_addr, edma_channel.slot, addr); + +while (edma3_check_for_transfer (edma3_base_addr, &edma_channel)) + ;
Can't we do with proper timeout, status from reg or some thing.
Quoted 34 lines
drivers/dma/ti-edma3.c +33
-1+qedma3_stop (edma3_base_addr, &edma_channel); + +if (rem_bytes !=0 ) { + slot.opt =0 ; + slot.src = + (b_cnt_value * max_acnt) + ((unsigned int ) src); + slot.acnt = rem_bytes; + slot.bcnt =1 ; + slot.ccnt =1 ; + slot.src_bidx = rem_bytes; + slot.dst_bidx = rem_bytes; + slot.src_cidx =0 ; + slot.dst_cidx =0 ; + slot.link =EDMA3_PARSET_NULL_LINK ; + slot.bcntrld =0 ; + slot.opt =EDMA3_SLOPT_TRANS_COMP_INT_ENB | +EDMA3_SLOPT_COMP_CODE (0 ) | +EDMA3_SLOPT_STATIC |EDMA3_SLOPT_AB_SYNC ; +edma3_slot_configure (edma3_base_addr, edma_slot_num, &slot); + edma_channel.slot = edma_slot_num; + edma_channel.chnum =0 ; + edma_channel.complete_code =0 ; +/* set event trigger to dst update */ + edma_channel.trigger_slot_word =EDMA3_TWORD (dst); + +qedma3_start (edma3_base_addr, &edma_channel); +edma3_set_dest_addr (edma3_base_addr, edma_channel.slot, addr + + (max_acnt * b_cnt_value)); +while (edma3_check_for_transfer (edma3_base_addr, &edma_channel)) + ; +qedma3_stop (edma3_base_addr, &edma_channel); + } +} --
Quoted 2 lines
2.5.0
thanks!
Signature · 1 line
Jagan | openedev.
Vignesh R
maintainerPATCH v2 9/10 spi: ti_qspi: Use DMA to read from qspi flash
In reply to Vignesh Rti_qspi uses memory map mode for faster read. Enabling DMA will increase read speed by 3x @48MHz on DRA74 EVM.
--- drivers/spi/ti_qspi.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)
drivers/spi/ti_qspi.c +23 -0
@@ -13,6 +13,8 @@#include <spi.h> #include <asm/gpio.h> #include <asm/omap_gpio.h> +#include <asm/omap_common.h> +#include <asm/ti-common/ti-edma3.h> /* ti qpsi register bit masks */ #define QSPI_TIMEOUT 2000000
@@ -347,3 +349,24 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,return 0 ; } +#ifdef CONFIG_TI_EDMA3 +void spi_flash_copy_mmap (void *data,void *offset,size_t len) +{ +unsigned int addr = (unsigned int ) (data); +unsigned int edma_slot_num =1 ; + +/* Invalidate the area, so no writeback into the RAM races with DMA */ +invalidate_dcache_range (addr, addr +roundup (len,ARCH_DMA_MINALIGN )); + +/* enable edma3 clocks */ +enable_edma3_clocks (); + +/* Call edma3 api to do actual DMA transfer */ +edma3_transfer (EDMA3_BASE , edma_slot_num, data, offset, len); + +/* disable edma3 clocks */ +disable_edma3_clocks (); + + *((unsigned int *)offset) += len; +} +#endif
Signature · 1 line
2.5.0
PATCH v2 9/10 spi: ti_qspi: Use DMA to read from qspi flash
Quoted 4 lines · Vignesh R
ti_qspiuses memory map mode for faster read. Enabling DMA will increase read speed by 3x @48MHz on DRA74 EVM.Signed-off-by Vignesh R <[email protected]>
Quoted 18 lines
--- drivers/spi/ti_qspi.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)drivers/spi/ti_qspi.c +2
-0@@ -13,6 +13,8 @@#include <spi.h> #include <asm/gpio.h> #include <asm/omap_gpio.h> +#include <asm/omap_common.h> +#include <asm/ti-common/ti-edma3.h> /* ti qpsi register bit masks */ #define QSPI_TIMEOUT 2000000
drivers/spi/ti_qspi.c int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, · line 352
Quoted 4 lines
drivers/spi/ti_qspi.c +1
-0@@ -347,3 +349,24 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,return 0 ; } +#ifdef CONFIG_TI_EDMA3
Add below comment
/* TODO: control from sf layer to here through dm-spi */
Quoted 23 lines
drivers/spi/ti_qspi.c +20
-1+void spi_flash_copy_mmap (void *data,void *offset,size_t len) +{ +unsigned int addr = (unsigned int ) (data); +unsigned int edma_slot_num =1 ; + +/* Invalidate the area, so no writeback into the RAM races with DMA */ +invalidate_dcache_range (addr, addr +roundup (len,ARCH_DMA_MINALIGN )); + +/* enable edma3 clocks */ +enable_edma3_clocks (); + +/* Call edma3 api to do actual DMA transfer */ +edma3_transfer (EDMA3_BASE , edma_slot_num, data, offset, len); + +/* disable edma3 clocks */ +disable_edma3_clocks (); + + *((unsigned int *)offset) += len; +} +#endif --2.5.0
Quoted 4 lines
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thanks!
Signature · 1 line
Jagan | openedev.
Vignesh R
maintainerPATCH v2 10/10 ARM: dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspi
In reply to Vignesh REnable TI_EDMA3 and SPL_DMA support, so as to reduce boot time. With DMA enabled there is almost 3x improvement in read performance. This helps in reducing boot time in qspiboot mode
Also add EDMA3 base address for DRA7XX and AM57XX.
--- arch/arm/include/asm/arch-omap5/hardware.h | 5 +++++ include/configs/dra7xx_evm.h | 2 ++ 2 files changed, 7 insertions(+)
arch/arm/include/asm/arch-omap5/hardware.h +5 -0
@@ -23,4 +23,9 @@/* GPMC Base address */ #define GPMC_BASE 0x50000000 +/* EDMA3 Base address for DRA7XX and AM57XX */ +#if defined(CONFIG_DRA7XX ) || defined(CONFIG_AM57XX ) +#define EDMA3_BASE 0x43300000 +#endif +#endif
include/configs/dra7xx_evm.h +2 -0
@@ -166,6 +166,8 @@/* SPI SPL */ #define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_DMA_SUPPORT +#define CONFIG_TI_EDMA3 #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
Signature · 1 line
2.5.0
PATCH v2 10/10 ARM: dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspi
Quoted 7 lines · Vignesh R
Enable
TI_EDMA3andSPL_DMAsupport, so as to reduce boot time. With DMA enabled there is almost 3x improvement in read performance. This helps in reducing boot time in qspiboot modeAlso add EDMA3 base address for DRA7XX and AM57XX.
Signed-off-by Vignesh R <[email protected]>
Quoted 35 lines
--- arch/arm/include/asm/arch-omap5/hardware.h | 5 +++++ include/configs/dra7xx_evm.h | 2 ++ 2 files changed, 7 insertions(+)arch/arm/include/asm/arch-omap5/hardware.h +5
-0@@ -23,4 +23,9 @@/* GPMC Base address */ #define GPMC_BASE 0x50000000 +/* EDMA3 Base address for DRA7XX and AM57XX */ +#if defined(CONFIG_DRA7XX ) || defined(CONFIG_AM57XX ) +#define EDMA3_BASE 0x43300000 +#endif +#endif include/configs/dra7xx_evm.h +2
-1@@ -166,6 +166,8 @@/* SPI SPL */ #define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_DMA_SUPPORT +#define CONFIG_TI_EDMA3 #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 --2.5.0
Quoted 4 lines
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thanks!
Signature · 1 line
Jagan | openedev.
Vignesh R
maintainerv2 cover Enable edma support for ti-qspi
In reply to Vignesh RQuoted 27 lines · Vignesh R
This patch series enables DMA for QSPI on dra7xx and am43xx. Patch 1 and 2 make sure the buffers are mem aligned for dma operation. Patch 3-6 add support for enabling and disabling of edma3 clocks on am43xx and dra7xx. Patch 7-9 add dma functionality to
ti_qspidriver. Patch 10 enable edma3 support in dra7xx config files.Tested on DRA74 EVM: http://pastebin.ubuntu.com/11813977/
changes in v2:
* Move edma related code to edma driver instead of handling it in ti-qspi driver.v1: https://www.mail-archive.com/u-boot at lists.denx.de/msg176479.html
Kishon Vijay Abraham I (2):
ARM: AM43xx: Add support for disabling clocks in uboot
ARM: OMAP5: Add support for disabling clocks in ubootRavi Babu (2):
sf: allocate cache aligned buffers to copy from flash
env: use cache line aligned memory for flash readTom Rini (1):
sf: ops: Addspi_flash_copy_mmapfunction
Quoted 6 lines
Vignesh R (5):
ARM: OMAP5: Add functions to enable and disable EDMA3 clocks
ARM: AM43XX: Add functions to enable and disable EDMA3 clocks
dma: ti-edma3: Add helper function to support edma3 transfer
spi:ti_qspi: Use DMA to read from qspi flash
ARM:dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspi
Gentle ping...
I haven't received any comments on this series.. Can these patches be picked up, if there are no further comments?
Quoted 19 lines
arch/arm/cpu/armv7/am33xx/clock.c | 52 +++++++++++++++++ arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 36 ++++++++++++ arch/arm/cpu/armv7/omap-common/clocks-common.c | 53 +++++++++++++++++ arch/arm/cpu/armv7/omap5/hw_data.c | 41 ++++++++++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 4 ++ arch/arm/include/asm/arch-am33xx/clock.h | 1 + arch/arm/include/asm/arch-omap5/hardware.h | 5 ++ arch/arm/include/asm/omap_common.h | 13 +++++ arch/arm/include/asm/ti-common/ti-edma3.h | 2 + common/cmd_sf.c | 6 +- common/env_sf.c | 11 ++-- drivers/dma/ti-edma3.c | 78 ++++++++++++++++++++++++++ drivers/mtd/spi/sf_ops.c | 8 ++- drivers/spi/ti_qspi.c | 23 ++++++++ include/configs/dra7xx_evm.h | 2 + include/spi.h | 3 + 16 files changed, 329 insertions(+), 9 deletions(-)
Signature · 2 lines
Regards Vignesh
v2 cover Enable edma support for ti-qspi
Quoted 37 lines · Vignesh R
Quoted 27 lines · Vignesh R
This patch series enables DMA for QSPI on dra7xx and am43xx. Patch 1 and 2 make sure the buffers are mem aligned for dma operation. Patch 3-6 add support for enabling and disabling of edma3 clocks on am43xx and dra7xx. Patch 7-9 add dma functionality to
ti_qspidriver. Patch 10 enable edma3 support in dra7xx config files.Tested on DRA74 EVM: http://pastebin.ubuntu.com/11813977/
changes in v2:
* Move edma related code to edma driver instead of handling it in ti-qspi driver.v1: https://www.mail-archive.com/u-boot at lists.denx.de/msg176479.html
Kishon Vijay Abraham I (2):
ARM: AM43xx: Add support for disabling clocks in uboot
ARM: OMAP5: Add support for disabling clocks in ubootRavi Babu (2):
sf: allocate cache aligned buffers to copy from flash
env: use cache line aligned memory for flash readTom Rini (1):
sf: ops: Addspi_flash_copy_mmapfunctionQuoted 6 lines
Vignesh R (5):
ARM: OMAP5: Add functions to enable and disable EDMA3 clocks
ARM: AM43XX: Add functions to enable and disable EDMA3 clocks
dma: ti-edma3: Add helper function to support edma3 transfer
spi:ti_qspi: Use DMA to read from qspi flash
ARM:dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspi
Quoted 3 lines
Gentle ping...
I haven't received any comments on this series.. Can these patches be picked up, if there are no further comments?
Yes, let me give sometime will back my comments.
Quoted 28 lines
Quoted 11 lines
arch/arm/cpu/armv7/am33xx/clock.c | 52 +++++++++++++++++ arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 36 ++++++++++++ arch/arm/cpu/armv7/omap-common/clocks-common.c | 53 +++++++++++++++++ arch/arm/cpu/armv7/omap5/hw_data.c | 41 ++++++++++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 4 ++ arch/arm/include/asm/arch-am33xx/clock.h | 1 + arch/arm/include/asm/arch-omap5/hardware.h | 5 ++ arch/arm/include/asm/omap_common.h | 13 +++++ arch/arm/include/asm/ti-common/ti-edma3.h | 2 +Quoted 9 lines
common/cmd_sf.c | 6 +- common/env_sf.c | 11 ++-- drivers/dma/ti-edma3.c | 78 ++++++++++++++++++++++++++ drivers/mtd/spi/sf_ops.c | 8 ++- drivers/spi/ti_qspi.c | 23 ++++++++ include/configs/dra7xx_evm.h | 2 + include/spi.h | 3 + 16 files changed, 329 insertions(+), 9 deletions(-)--
Regards
Vignesh
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Signature · 1 line
Jagan | openedev.