PM / devfreq: exynos-ppmu: fix load_count calculation
Subsystems (4)
PATCH 1/1 PM / devfreq: exynos-ppmu: fix load_count calculation
"pmcnt_high & 0xff" is a u32 so we shifting it 32 spaces is zero. GCC catches this bug:
drivers/devfreq/event/exynos-ppmu.c: In function ‘exynos_ppmu_v2_get_event’:drivers/devfreq/event/exynos-ppmu.c:322:3: warning: left shift count >= width of type
load_count = (u64)((pmcnt_high & 0xff) << 32) + (u64)pmcnt_low;
drivers/devfreq/event/exynos-ppmu.c +1 -1
@@ -319,7 +319,7 @@ static int exynos_ppmu_v2_get_event(struct devfreq_event_dev *edev,case PPMU_PMNCNT3 : pmcnt_high =__raw_readl (info->ppmu.base +PPMU_V2_PMCNT3_HIGH ); pmcnt_low =__raw_readl (info->ppmu.base +PPMU_V2_PMCNT3_LOW ); - load_count = (u64)((pmcnt_high &0xff ) <<32 ) + (u64 )pmcnt_low; + load_count = (((u64 )pmcnt_high &0xff ) <<32 ) + pmcnt_low;break ; } edata->load_count = load_count;
MyungJoo Ham
maintainerPiAicG1jbnRfaGlnaCAmIDB4ZmYiIGlzIGEgdTMyIHNvIHdlIHNoaWZ0aW5nIGl0IDMyIHNwYWNl cyBpcyB6ZXJvLiAgR0NDDQo+IGNhdGNoZXMgdGhpcyBidWc6DQo+IA0KPiBkcml2ZXJzL2RldmZy ZXEvZXZlbnQvZXh5bm9zLXBwbXUuYzogSW4gZnVuY3Rpb24g4oCYZXh5bm9zX3BwbXVfdjJfZ2V0 X2V2ZW504oCZOg0KPiBkcml2ZXJzL2RldmZyZXEvZXZlbnQvZXh5bm9zLXBwbXUuYzozMjI6Mzog d2FybmluZzogbGVmdCBzaGlmdCBjb3VudCA+PSB3aWR0aCBvZiB0eXBlDQo+ICAgIGxvYWRfY291 bnQgPSAodTY0KSgocG1jbnRfaGlnaCAmIDB4ZmYpIDw8IDMyKSArICh1NjQpcG1jbnRfbG93Ow0K PiANCj4gRml4ZXM6IDNkODdiMDIyODFhMiAoJ1BNIC8gZGV2ZnJlcTogZXh5bm9zLXBwbXU6IEFk ZCB0aGUgc3VwcG9ydCBvZiBQUE1VdjIgZm9yIEV4eW5vczU0MzMnKQ0KPiBTaWduZWQtb2ZmLWJ5 OiBEYW4gQ2FycGVudGVyIDxkYW4uY2FycGVudGVyQG9yYWNsZS5jb20+DQoNClRoaXMgcGF0Y2gg aGFzIGJlZW4gd2FpdGluZyBpbiBkZXZmcmVxIHRyZWUgZm9yIHNvbWUgZGF5cy4NCkl0IHdpbGwg YmUgc2VudCB3aXRoIHRoZSBuZXh0IHB1bGwgcmVxdWVzdC4NCg0KaHR0cHM6Ly9naXQua2VybmVs Lm9yZy9jZ2l0L2xpbnV4L2tlcm5lbC9naXQvbXp4L2RldmZyZXEuZ2l0L2NvbW1pdC8/aD1mb3It cmFmYWVsJmlkPThlMjlhYmViYmRiMzJhMzBkODdhNTgyMDFhYzliNzdmOGE4N2ZkODQNCg0KPiAN Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZGV2ZnJlcS9ldmVudC9leHlub3MtcHBtdS5jIGIvZHJp dmVycy9kZXZmcmVxL2V2ZW50L2V4eW5vcy1wcG11LmMNCj4gaW5kZXggZjk5MDFmNS4uZGFmMmNk YiAxMDA2NDQNCj4gLS0tIGEvZHJpdmVycy9kZXZmcmVxL2V2ZW50L2V4eW5vcy1wcG11LmMNCj4g KysrIGIvZHJpdmVycy9kZXZmcmVxL2V2ZW50L2V4eW5vcy1wcG11LmMNCj4gQEAgLTMxOSw3ICsz MTksNyBAQCBzdGF0aWMgaW50IGV4eW5vc19wcG11X3YyX2dldF9ldmVudChzdHJ1Y3QgZGV2ZnJl cV9ldmVudF9kZXYgKmVkZXYsDQo+ICAJY2FzZSBQUE1VX1BNTkNOVDM6DQo+ICAJCXBtY250X2hp Z2ggPSBfX3Jhd19yZWFkbChpbmZvLT5wcG11LmJhc2UgKyBQUE1VX1YyX1BNQ05UM19ISUdIKTsN Cj4gIAkJcG1jbnRfbG93ID0gX19yYXdfcmVhZGwoaW5mby0+cHBtdS5iYXNlICsgUFBNVV9WMl9Q TUNOVDNfTE9XKTsNCj4gLQkJbG9hZF9jb3VudCA9ICh1NjQpKChwbWNudF9oaWdoICYgMHhmZikg PDwgMzIpICsgKHU2NClwbWNudF9sb3c7DQo+ICsJCWxvYWRfY291bnQgPSAoKCh1NjQpcG1jbnRf aGlnaCAmIDB4ZmYpIDw8IDMyKSArIHBtY250X2xvdzsNCj4gIAkJYnJlYWs7DQo+ICAJfQ0KPiAg CWVkYXRhLT5sb2FkX2NvdW50ID0gbG9hZF9jb3VudDsNCj4gDQo