dmaengine: mv_xor fixes and improvements

Commit 6f166312c6ea2 ("dmaengine: mv_xor: add support for a38x command in descriptor mode") introduced the support for a feature that appeared in Armada 38x: specifying the operation to be performed in a per-descriptor basis rather than globally per channel.

However, when doing so, it changed the function mv_chan_set_mode() to use:

if (IS_ENABLED(__BIG_ENDIAN))

instead of:

  #if defined(__BIG_ENDIAN)

While IS_ENABLED() is perfectly fine for CONFIG_* symbols, it is not for other symbols such as __BIG_ENDIAN that is provided directly by the compiler. Consequently, the commit broke support for big-endian, as the XOR_DESCRIPTOR_SWAP flag was not set in the XOR channel configuration register.

The primarily visible effect was some nasty warnings and failures appearing during the self-test of the XOR unit:

[    1.197368] mv_xor d0060900.xor: error on chan 0. intr cause 0x00000082
[    1.197393] mv_xor d0060900.xor: config       0x00008440
[    1.197410] mv_xor d0060900.xor: activation   0x00000000
[    1.197427] mv_xor d0060900.xor: intr cause   0x00000082
[    1.197443] mv_xor d0060900.xor: intr mask    0x000003f7
[    1.197460] mv_xor d0060900.xor: error cause  0x00000000
[    1.197477] mv_xor d0060900.xor: error addr   0x00000000
[    1.197491] ------------[ cut here ]------------
[    1.197513] WARNING: CPU: 0 PID: 1 at ../drivers/dma/mv_xor.c:664 mv_xor_interrupt_handler+0x14c/0x170()

See also:

http://storage.kernelci.org/next/next-20150617/arm-mvebu_v7_defconfig+CONFIG_CPU_BIG_ENDIAN=y/lab-khilman/boot-armada-xp-openblocks-ax3-4.txt

This commit adds suspend/resume support to the mv_xor driver. The config and interrupt mask registers must be saved and restored, and upon resume, the MBus windows configuration must also be done again.

Tested on Armada 388 GP, with a RAID 5 array, accessed before and after a suspend to RAM cycle.

Based on work from Ofer Heifetz and Lior Amsalem.

Signed-off-by Thomas Petazzoni <[email protected]>

---
 drivers/dma/mv_xor.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/dma/mv_xor.h |  1 +
 2 files changed, 48 insertions(+)

drivers/dma/mv_xor.c +5 -0

index f1325f6..0a3ddc2 100644
@@ -1121,6 +1121,51 @@ mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
 	writel(0, base + WINDOW_OVERRIDE_CTRL(1));
 }
 
+static int mv_xor_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct mv_xor_device *xordev = platform_get_drvdata(pdev);
+	int i;
+

drivers/dma/mv_xor.c +32 -0

+	}
+
+	return 0;
+}
+
+static int mv_xor_resume(struct platform_device *dev)
+{
+	struct mv_xor_device *xordev = platform_get_drvdata(dev);
+	const struct mbus_dram_target_info *dram;
+	int i;
+
+	for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
+		struct mv_xor_chan *mv_chan = xordev->channels[i];
+
+		if (!mv_chan)
+			continue;
+
+		writel_relaxed(mv_chan->saved_config_reg,
+			       XOR_CONFIG(mv_chan));
+		writel_relaxed(mv_chan->saved_int_mask_reg,
+			       XOR_INTR_MASK(mv_chan));
+	}
+
+	dram = mv_mbus_dram_info();
+	if (dram)
+		mv_xor_conf_mbus_windows(xordev, dram);
+
+	return 0;
+}
+
 static const struct of_device_id mv_xor_dt_ids[] = {
 	{ .compatible = "marvell,orion-xor", .data = (void *)XOR_MODE_IN_REG },
 	{ .compatible = "marvell,armada-380-xor", .data = (void *)XOR_MODE_IN_DESC },

@@ -1284,6 +1329,8 @@ static int mv_xor_remove(struct platform_device *pdev)
 static struct platform_driver mv_xor_driver = {
 	.probe		= mv_xor_probe,
 	.remove		= mv_xor_remove,
+	.suspend        = mv_xor_suspend,
+	.resume         = mv_xor_resume,
 	.driver		= {
 		.name	        = MV_XOR_NAME,
 		.of_match_table = of_match_ptr(mv_xor_dt_ids),

drivers/dma/mv_xor.h +1 -0

index b7455b4..41a2e8d 100644
@@ -126,6 +126,7 @@ struct mv_xor_chan {
 	char			dummy_src[MV_XOR_MIN_BYTE_COUNT];
 	char			dummy_dst[MV_XOR_MIN_BYTE_COUNT];
 	dma_addr_t		dummy_src_addr, dummy_dst_addr;
+	u32                     saved_config_reg, saved_int_mask_reg;
 };
 
 /**

Signature · 1 line

2.4.5

Quoted 9 lines

drivers/dma/mv_xor.c +9 -0

+static int mv_xor_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct mv_xor_device *xordev = platform_get_drvdata(pdev);
+	int i;
+
+	for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
+		struct mv_xor_chan *mv_chan = xordev->channels[i];
+
+		if (!mv_chan)

drivers/dma/mv_xor.c mv_xor_conf_mbus_windows(struct mv_xor_device *xordev, · line 1138

Quoted 6 lines

drivers/dma/mv_xor.c +6 -0

+			continue;
+
+		mv_chan->saved_config_reg =
+			readl_relaxed(XOR_CONFIG(mv_chan));
+		mv_chan->saved_int_mask_reg =
+			readl_relaxed(XOR_INTR_MASK(mv_chan));

this sound fine, but I am missing the suspension of the channel. If a transfer was active while suspend was invoked then how would this work?

Vinod,

Quoted 9 lines · Vinod Koul

Quoted 9 lines

drivers/dma/mv_xor.c +9 -0

+static int mv_xor_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct mv_xor_device *xordev = platform_get_drvdata(pdev);
+	int i;
+
+	for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
+		struct mv_xor_chan *mv_chan = xordev->channels[i];
+
+		if (!mv_chan)

Quoted 8 lines

drivers/dma/mv_xor.c mv_xor_conf_mbus_windows(struct mv_xor_device *xordev, · line 1138

Quoted 6 lines

drivers/dma/mv_xor.c +6 -0

+			continue;
+
+		mv_chan->saved_config_reg =
+			readl_relaxed(XOR_CONFIG(mv_chan));
+		mv_chan->saved_int_mask_reg =
+			readl_relaxed(XOR_INTR_MASK(mv_chan));

this sound fine, but I am missing the suspension of the channel. If a transfer was active while suspend was invoked then how would this work?

There are indeed no provisions to handle this problem. Does the dmaengine framework provide any helpers to ease with this? I have quickly looked at other dmaengine drivers, and I haven't seen any of them taking care of this problem. Do you have a pointer to a driver handling this problem?

The only reason why we had dmacap,* properties is because back when DMA_MEMSET was supported, only one out of the two channels per engine could do a memset operation. But this is something that the driver already knows anyway, and since then, the DMA_MEMSET support has been removed.

The driver is already well aware of what each channel supports and the one to one mapping between Linux specific implementation details (such as dmacap,interrupt enabling DMA_INTERRUPT) and DT properties is a good indication that these DT properties are wrong.

Therefore, this commit simply gets rid of these dmacap,* properties, they are now ignored, and the driver is responsible for knowing the capabilities of the hardware with regard to the dmaengine subsystem expectations.

Signed-off-by Thomas Petazzoni <[email protected]>

Reviewed-by Maxime Ripard <[email protected]>

---
 Documentation/devicetree/bindings/dma/mv-xor.txt | 10 ++++------
 drivers/dma/mv_xor.c                             |  9 +++------
 2 files changed, 7 insertions(+), 12 deletions(-)

Documentation/devicetree/bindings/dma/mv-xor.txt +4 -1

index cc29c35..276ef81 100644
@@ -12,10 +12,13 @@ XOR engine has. Those sub-nodes have the following required
 properties:
 - interrupts: interrupt of the XOR channel
 
-And the following optional properties:
+The sub-nodes used to contain one or several of the following
+properties, but they are now deprecated:
 - dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations
 - dmacap,memset to indicate that the XOR channel is capable of memset operations
 - dmacap,xor to indicate that the XOR channel is capable of xor operations
+- dmacap,interrupt to indicate that the XOR channel is capable of
+  generating interrupts
 
 Example:
 

@@ -28,13 +31,8 @@ xor at d0060900 {
 

Documentation/devicetree/bindings/dma/mv-xor.txt +0 -0

 	};
 };

drivers/dma/mv_xor.c +3 -6

index 0a3ddc2..6aedc36 100644
@@ -1236,12 +1236,9 @@ static int mv_xor_probe(struct platform_device *pdev)
 			op_in_desc = (int)of_id->data;
 
 			dma_cap_zero(cap_mask);
-			if (of_property_read_bool(np, "dmacap,memcpy"))
-				dma_cap_set(DMA_MEMCPY, cap_mask);
-			if (of_property_read_bool(np, "dmacap,xor"))
-				dma_cap_set(DMA_XOR, cap_mask);
-			if (of_property_read_bool(np, "dmacap,interrupt"))
-				dma_cap_set(DMA_INTERRUPT, cap_mask);
+			dma_cap_set(DMA_MEMCPY, cap_mask);
+			dma_cap_set(DMA_XOR, cap_mask);
+			dma_cap_set(DMA_INTERRUPT, cap_mask);
 
 			irq = irq_of_parse_and_map(np, 0);
 			if (!irq) {

Signature · 1 line

2.4.5

Documentation/devicetree/bindings/dma/mv-xor.txt xor at d0060900 { · line 38

Quoted 12 lines · Thomas Petazzoni

Documentation/devicetree/bindings/dma/mv-xor.txt +0 -5

@@ -28,13 +31,8 @@ xor at d0060900 {
 
 	xor00 {
 	      interrupts = <51>;
-	      dmacap,memcpy;
-	      dmacap,xor;
 	};
 	xor01 {
 	      interrupts = <52>;
-	      dmacap,memcpy;
-	      dmacap,xor;
-	      dmacap,memset;

I maybe wrong but there was an assumption that DT properties, even if bad are always there as they need to be treated as kernel ABI.

How will it work if someone has older DT implementation or older driver?

Arnd, what are the rules here and are they documented anywhere?

Documentation/devicetree/bindings/dma/mv-xor.txt xor at d0060900 { · line 38

Quoted 5 lines

Documentation/devicetree/bindings/dma/mv-xor.txt +0 -3

 	xor01 {
 	      interrupts = <52>;
-	      dmacap,memcpy;
-	      dmacap,xor;
-	      dmacap,memset;

I maybe wrong but there was an assumption that DT properties, even if bad are always there as they need to be treated as kernel ABI.

How will it work if someone has older DT implementation or older driver?

Vinod,

Quoted 9 lines · Vinod Koul

Documentation/devicetree/bindings/dma/mv-xor.txt xor at d0060900 { · line 38

Quoted 5 lines

Documentation/devicetree/bindings/dma/mv-xor.txt +0 -3

 	xor01 {
 	      interrupts = <52>;
-	      dmacap,memcpy;
-	      dmacap,xor;
-	      dmacap,memset;

I maybe wrong but there was an assumption that DT properties, even if bad are always there as they need to be treated as kernel ABI.

How will it work if someone has older DT implementation or older driver?

Supporting a new DT with an old kernel has never been part of the requirements of the DT ABI stability.

Supporting an old DT with a new kernel is the actual requirement. And the patch I'm proposing does not break this at all: a new kernel will simply ignore those dmacap,* properties from an old DT, and the driver automatically knows by itself what are the capabilities of the different XOR engines.

Therefore, there is no backward compatibility issue introduced by this patch.

The only reason why we had dmacap,* properties is because back when DMA_MEMSET was supported, only one out of the two channels per engine could do a memset operation. But this is something that the driver already knows anyway, and since then, the DMA_MEMSET support has been removed.

The driver is already well aware of what each channel supports and the one to one mapping between Linux specific implementation details (such as dmacap,interrupt enabling DMA_INTERRUPT) and DT properties is a good indication that these DT properties are wrong.

Therefore, this commit simply gets rid of these dmacap,* properties, they are now ignored, and the driver is responsible for knowing the capabilities of the hardware with regard to the dmaengine subsystem expectations.

Since commit 3e4f52e2da9f6 ("dma: mv_xor: Simplify the DMA_MEMCPY operation"), this field is no longer used, so get rid of it.

When commit 6f166312c6ea2 ("dmaengine: mv_xor: add support for a38x command in descriptor mode") added support for the descriptor mode available in Marvell Armada 38x and later SoCs, it added a new function mv_chan_set_mode_to_desc() which allows to configure a XOR channel to get the specific operation to be done from each individual DMA descriptor.

However, this function was mainly a duplicate of the existing mv_chan_set_mode(), with just the operation being different.

This commit re-organizes the code into a single mv_chan_set_mode() function, which takes the operation mode as argument, and the mv_xor_channel_add() function decides whether to use XOR_OPERATION_MODE_IN_DESC or XOR_OPERATION_MODE_XOR.

Due to how async_tx behaves internally, having more XOR channels than CPUs is actually hurting performance more than it improves it, because memcpy requests get scheduled on a different channel than the XOR requests, but async_tx will still wait for the completion of the memcpy requests before scheduling the XOR requests.

It is in fact more efficient to have at most one channel per CPU, which this patch implements by limiting the number of channels per engine, and the number of engines registered depending on the number of availables CPUs.

Marvell platforms are currently available in one CPU, two CPUs and four CPUs configurations:

- in the configurations with one CPU, only one channel from one engine is used.

- in the configurations with two CPUs, only one channel from each engine is used (they are two XOR engines)

- in the configurations with four CPUs, both channels of both engines are used.

Hello,

Here is a v4 of the series making some fixes and improvements to the mv_xor driver. I'd like to see them merged for 4.3 if possible.

Changes v3 -> v4:

* Rebased on 4.2-rc1.