arm: socfpga: Board cleanup
Subsystems (3)
cover arm: socfpga: Board cleanup
This series cleans up the QTS-generated header files and cleans up the SoCDK support such that they fit into the framework just like any other SoCFPGA boards.
Marek Vasut (8):
arm: socfpga: Move wrappers into platform directory
arm: socfpga: Unbind CPU type from board type
arm: socfpga: Split Altera socfpga into AV and CV SoCDK
arm: socfpga: Remove CV-specific parts from AV-SoCDK
arm: socfpga: Remove AV-specific parts from CV-SoCDK
arm: socfpga: Add qts-filter.sh script
arm: socfpga: Switch to filtered QTS files
arm: socfpga: Make the pinmux table const u8
arch/arm/mach-socfpga/Kconfig | 26 +-
arch/arm/mach-socfpga/Makefile | 9 +
.../arm/mach-socfpga/include/mach/system_manager.h | 3 +-
arch/arm/mach-socfpga/qts-filter.sh | 205 +++
arch/arm/mach-socfpga/system_manager.c | 2 +-
.../arm/mach-socfpga}/wrap_iocsr_config.c | 7 +-
arch/arm/mach-socfpga/wrap_pinmux_config.c | 17 +
.../arm/mach-socfpga}/wrap_pll_config.c | 2 +-
.../arm/mach-socfpga}/wrap_sdram_config.c | 8 +-
board/altera/{socfpga => arria5-socdk}/MAINTAINERS | 0
board/altera/{socfpga => arria5-socdk}/Makefile | 4 +-
board/altera/arria5-socdk/qts/iocsr_config.h | 696 ++++++++++
board/altera/arria5-socdk/qts/pinmux_config.h | 219 ++++
board/altera/arria5-socdk/qts/pll_config.h | 85 ++
board/altera/arria5-socdk/qts/sdram_config.h | 340 +++++
board/altera/{socfpga => arria5-socdk}/socfpga.c | 0
.../altera/{socfpga => cyclone5-socdk}/MAINTAINERS | 0
board/altera/{socfpga => cyclone5-socdk}/Makefile | 4 +-
board/altera/cyclone5-socdk/qts/iocsr_config.h | 660 ++++++++++
board/altera/cyclone5-socdk/qts/pinmux_config.h | 219 ++++
board/altera/cyclone5-socdk/qts/pll_config.h | 85 ++
board/altera/cyclone5-socdk/qts/sdram_config.h | 342 +++++
board/altera/{socfpga => cyclone5-socdk}/socfpga.c | 0
board/altera/socfpga/qts/iocsr_config.c | 1345 --------------------
board/altera/socfpga/qts/iocsr_config.h | 26 -
board/altera/socfpga/qts/pinmux_config.c | 429 -------
board/altera/socfpga/qts/pinmux_config.h | 54 -
board/altera/socfpga/qts/pll_config.h | 109 --
board/altera/socfpga/qts/sdram_config.h | 100 --
board/altera/socfpga/qts/sequencer_auto.h | 128 --
board/altera/socfpga/qts/sequencer_auto_ac_init.h | 84 --
.../altera/socfpga/qts/sequencer_auto_inst_init.h | 268 ----
board/altera/socfpga/qts/sequencer_defines.h | 122 --
board/altera/socfpga/wrap_pinmux_config.c | 35 -
configs/socfpga_arria5_defconfig | 1 +
configs/socfpga_cyclone5_defconfig | 1 +
configs/socfpga_socrates_defconfig | 1 +
37 files changed, 2908 insertions(+), 2728 deletions(-)
create mode 100755 arch/arm/mach-socfpga/qts-filter.sh
rename {board/altera/socfpga => arch/arm/mach-socfpga}/wrap_iocsr_config.c (87%)
create mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config.c
rename {board/altera/socfpga => arch/arm/mach-socfpga}/wrap_pll_config.c (99%)
rename {board/altera/socfpga => arch/arm/mach-socfpga}/wrap_sdram_config.c (98%)
copy board/altera/{socfpga => arria5-socdk}/MAINTAINERS (100%)
copy board/altera/{socfpga => arria5-socdk}/Makefile (57%)
create mode 100644 board/altera/arria5-socdk/qts/iocsr_config.h
create mode 100644 board/altera/arria5-socdk/qts/pinmux_config.h
create mode 100644 board/altera/arria5-socdk/qts/pll_config.h
create mode 100644 board/altera/arria5-socdk/qts/sdram_config.h
copy board/altera/{socfpga => arria5-socdk}/socfpga.c (100%)
rename board/altera/{socfpga => cyclone5-socdk}/MAINTAINERS (100%)
rename board/altera/{socfpga => cyclone5-socdk}/Makefile (57%)
create mode 100644 board/altera/cyclone5-socdk/qts/iocsr_config.h
create mode 100644 board/altera/cyclone5-socdk/qts/pinmux_config.h
create mode 100644 board/altera/cyclone5-socdk/qts/pll_config.h
create mode 100644 board/altera/cyclone5-socdk/qts/sdram_config.h
rename board/altera/{socfpga => cyclone5-socdk}/socfpga.c (100%)
delete mode 100644 board/altera/socfpga/qts/iocsr_config.c
delete mode 100644 board/altera/socfpga/qts/iocsr_config.h
delete mode 100644 board/altera/socfpga/qts/pinmux_config.c
delete mode 100644 board/altera/socfpga/qts/pinmux_config.h
delete mode 100644 board/altera/socfpga/qts/pll_config.h
delete mode 100644 board/altera/socfpga/qts/sdram_config.h
delete mode 100644 board/altera/socfpga/qts/sequencer_auto.h
delete mode 100644 board/altera/socfpga/qts/sequencer_auto_ac_init.h
delete mode 100644 board/altera/socfpga/qts/sequencer_auto_inst_init.h
delete mode 100644 board/altera/socfpga/qts/sequencer_defines.h
delete mode 100644 board/altera/socfpga/wrap_pinmux_config.cSignature · 1 line
2.1.4
PATCH 1/8 arm: socfpga: Move wrappers into platform directory
Move the wrappers for QTS-generated files into platform directory out of the board directory. The trick here is to add -I to CFLAGS such that it points to the board directory in source tree and thus the qts/ directory there is still reachable.
Signed-off-by Marek Vasut <[email protected]>
---
arch/arm/mach-socfpga/Makefile | 9 +++++++++
.../socfpga => arch/arm/mach-socfpga}/wrap_iocsr_config.c | 2 +-
.../socfpga => arch/arm/mach-socfpga}/wrap_pinmux_config.c | 2 +-
.../altera/socfpga => arch/arm/mach-socfpga}/wrap_pll_config.c | 2 +-
.../socfpga => arch/arm/mach-socfpga}/wrap_sdram_config.c | 10 +++++-----
board/altera/socfpga/Makefile | 4 +---
6 files changed, 18 insertions(+), 11 deletions(-)
rename {board/altera/socfpga => arch/arm/mach-socfpga}/wrap_iocsr_config.c (96%)
rename {board/altera/socfpga => arch/arm/mach-socfpga}/wrap_pinmux_config.c (97%)
rename {board/altera/socfpga => arch/arm/mach-socfpga}/wrap_pll_config.c (99%)
rename {board/altera/socfpga => arch/arm/mach-socfpga}/wrap_sdram_config.c (98%)arch/arm/mach-socfpga/Makefile +9 -0
@@ -10,3 +10,12 @@ obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ fpga_manager.o scan_manager.o obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o + +# QTS-generated config file wrappers +obj-y += wrap_pll_config.o +obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \ + wrap_sdram_config.o +CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) +CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR) +CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR) +CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
arch/arm/mach-socfpga/wrap_iocsr_config.c renamed from board/altera/socfpga/wrap_iocsr_config.c +1 -1
@@ -10,7 +10,7 @@/* * Yes, dear reader, we're including a C file here, this is no mistake :-) */ -#include "qts/iocsr_config.c" +#include <qts/iocsr_config.c> int iocsr_get_config_table(const unsigned int chain_id, const unsigned long **table,
arch/arm/mach-socfpga/wrap_pinmux_config.c renamed from board/altera/socfpga/wrap_pinmux_config.c +1 -1
@@ -25,7 +25,7 @@*/ #define _PRELOADER_PINMUX_CONFIG_H_#define CONFIG_HPS_PINMUX_NUM -#include "qts/pinmux_config.c" +#include <qts/pinmux_config.c> void sysmgr_get_pinmux_table (const unsigned long **table,unsigned int *table_len)
arch/arm/mach-socfpga/wrap_pll_config.c renamed from board/altera/socfpga/wrap_pll_config.c +1 -1
@@ -6,7 +6,7 @@#include <common.h> #include <asm/arch/clock_manager.h> -#include "qts/pll_config.h" +#include <qts/pll_config.h> #define MAIN_VCO_BASE ( \ (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
arch/arm/mach-socfpga/wrap_sdram_config.c renamed from board/altera/socfpga/wrap_sdram_config.c +5 -5
@@ -8,12 +8,12 @@#include <errno.h> #include <asm/arch/sdram.h> /* QTS output file. */ -#include "qts/sdram_config.h" +#include <qts/sdram_config.h> -#include "qts/sequencer_auto_ac_init.h" -#include "qts/sequencer_auto_inst_init.h" -#include "qts/sequencer_auto.h" -#include "qts/sequencer_defines.h" +#include <qts/sequencer_auto_ac_init.h> +#include <qts/sequencer_auto_inst_init.h> +#include <qts/sequencer_auto.h> +#include <qts/sequencer_defines.h> static const struct socfpga_sdram_config sdram_config = { .ctrl_cfg =
board/altera/socfpga/Makefile +1 -3
@@ -6,6 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := socfpga.o wrap_pll_config.o -obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \ - wrap_sdram_config.o +obj-y := socfpga.o
Signature · 1 line
2.1.4
PATCH 2/8 arm: socfpga: Unbind CPU type from board type
In reply to Marek VasutThe CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board.
All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option.
The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/Kconfig | 26 ++++++++++++++++++-------- configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + 4 files changed, 21 insertions(+), 8 deletions(-)
arch/arm/mach-socfpga/Kconfig +18 -8
@@ -1,28 +1,38 @@ if ARCH_SOCFPGA +config TARGET_SOCFPGA_ARRIA5 + bool + +config TARGET_SOCFPGA_CYCLONE5 + bool + choice prompt "Altera SOCFPGA board select" optional -config TARGET_SOCFPGA_ARRIA5 - bool "Altera SOCFPGA Arria V" +config TARGET_SOCFPGA_ARRIA5_SOCDK + bool "Altera SOCFPGA SoCDK (Arria V)" + select TARGET_SOCFPGA_ARRIA5 -config TARGET_SOCFPGA_CYCLONE5 - bool "Altera SOCFPGA Cyclone V" +config TARGET_SOCFPGA_CYCLONE5_SOCDK + bool "Altera SOCFPGA SoCDK (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 endchoice config SYS_BOARD - default "socfpga" + default "socfpga" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "socfpga" if TARGET_SOCFPGA_CYCLONE5_SOCDK config SYS_VENDOR - default "altera" + default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK config SYS_SOC default "socfpga" config SYS_CONFIG_NAME - default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5 - default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5 + default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK endif
configs/socfpga_arria5_defconfig +1 -0
@@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_TARGET_SOCFPGA_ARRIA5=y +CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk" CONFIG_SPL=y # CONFIG_CMD_IMLS is not set
configs/socfpga_cyclone5_defconfig +1 -0
@@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_TARGET_SOCFPGA_CYCLONE5=y +CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk" CONFIG_SPL=y # CONFIG_CMD_IMLS is not set
configs/socfpga_socrates_defconfig +1 -0
@@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_TARGET_SOCFPGA_CYCLONE5=y +CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" CONFIG_SPL=y # CONFIG_CMD_IMLS is not set
Signature · 1 line
2.1.4
PATCH 3/8 arm: socfpga: Split Altera socfpga into AV and CV SoCDK
In reply to Marek VasutThe board/altera/socfpga directory is not a generic SoCFPGA machine anymore, but instead it represents the Altera SoCDK board. To make matters more complicated, it represents both CycloneV and ArriaV variant.
On the other hand, nowadays, the content of this board directory is mostly comprised of QTS-generated header files, while all the generic code is in arch/arm/mach-socfpga already.
Thus, this patch splits the board/altera/socfpga into a separate board directory for ArriaV SoCDK and CycloneV SoCDK, so that each can be populated with the correct QTS-generated header files for that particular board.
Signed-off-by Marek Vasut <[email protected]>
---
arch/arm/mach-socfpga/Kconfig | 4 ++--
board/altera/{socfpga => arria5-socdk}/MAINTAINERS | 0
board/altera/{socfpga => arria5-socdk}/Makefile | 0
board/altera/{socfpga => arria5-socdk}/qts/iocsr_config.c | 0
board/altera/{socfpga => arria5-socdk}/qts/iocsr_config.h | 0
board/altera/{socfpga => arria5-socdk}/qts/pinmux_config.c | 0
board/altera/{socfpga => arria5-socdk}/qts/pinmux_config.h | 0
board/altera/{socfpga => arria5-socdk}/qts/pll_config.h | 0
board/altera/{socfpga => arria5-socdk}/qts/sdram_config.h | 0
board/altera/{socfpga => arria5-socdk}/qts/sequencer_auto.h | 0
board/altera/{socfpga => arria5-socdk}/qts/sequencer_auto_ac_init.h | 0
board/altera/{socfpga => arria5-socdk}/qts/sequencer_auto_inst_init.h | 0
board/altera/{socfpga => arria5-socdk}/qts/sequencer_defines.h | 0
board/altera/{socfpga => arria5-socdk}/socfpga.c | 0
board/altera/{socfpga => cyclone5-socdk}/MAINTAINERS | 0
board/altera/{socfpga => cyclone5-socdk}/Makefile | 0
board/altera/{socfpga => cyclone5-socdk}/qts/iocsr_config.c | 0
board/altera/{socfpga => cyclone5-socdk}/qts/iocsr_config.h | 0
board/altera/{socfpga => cyclone5-socdk}/qts/pinmux_config.c | 0
board/altera/{socfpga => cyclone5-socdk}/qts/pinmux_config.h | 0
board/altera/{socfpga => cyclone5-socdk}/qts/pll_config.h | 0
board/altera/{socfpga => cyclone5-socdk}/qts/sdram_config.h | 0
board/altera/{socfpga => cyclone5-socdk}/qts/sequencer_auto.h | 0
board/altera/{socfpga => cyclone5-socdk}/qts/sequencer_auto_ac_init.h | 0
.../altera/{socfpga => cyclone5-socdk}/qts/sequencer_auto_inst_init.h | 0
board/altera/{socfpga => cyclone5-socdk}/qts/sequencer_defines.h | 0
board/altera/{socfpga => cyclone5-socdk}/socfpga.c | 0
27 files changed, 2 insertions(+), 2 deletions(-)
copy board/altera/{socfpga => arria5-socdk}/MAINTAINERS (100%)
copy board/altera/{socfpga => arria5-socdk}/Makefile (100%)
copy board/altera/{socfpga => arria5-socdk}/qts/iocsr_config.c (100%)
copy board/altera/{socfpga => arria5-socdk}/qts/iocsr_config.h (100%)
copy board/altera/{socfpga => arria5-socdk}/qts/pinmux_config.c (100%)
copy board/altera/{socfpga => arria5-socdk}/qts/pinmux_config.h (100%)
copy board/altera/{socfpga => arria5-socdk}/qts/pll_config.h (100%)
copy board/altera/{socfpga => arria5-socdk}/qts/sdram_config.h (100%)
copy board/altera/{socfpga => arria5-socdk}/qts/sequencer_auto.h (100%)
copy board/altera/{socfpga => arria5-socdk}/qts/sequencer_auto_ac_init.h (100%)
copy board/altera/{socfpga => arria5-socdk}/qts/sequencer_auto_inst_init.h (100%)
copy board/altera/{socfpga => arria5-socdk}/qts/sequencer_defines.h (100%)
copy board/altera/{socfpga => arria5-socdk}/socfpga.c (100%)
rename board/altera/{socfpga => cyclone5-socdk}/MAINTAINERS (100%)
rename board/altera/{socfpga => cyclone5-socdk}/Makefile (100%)
rename board/altera/{socfpga => cyclone5-socdk}/qts/iocsr_config.c (100%)
rename board/altera/{socfpga => cyclone5-socdk}/qts/iocsr_config.h (100%)
rename board/altera/{socfpga => cyclone5-socdk}/qts/pinmux_config.c (100%)
rename board/altera/{socfpga => cyclone5-socdk}/qts/pinmux_config.h (100%)
rename board/altera/{socfpga => cyclone5-socdk}/qts/pll_config.h (100%)
rename board/altera/{socfpga => cyclone5-socdk}/qts/sdram_config.h (100%)
rename board/altera/{socfpga => cyclone5-socdk}/qts/sequencer_auto.h (100%)
rename board/altera/{socfpga => cyclone5-socdk}/qts/sequencer_auto_ac_init.h (100%)
rename board/altera/{socfpga => cyclone5-socdk}/qts/sequencer_auto_inst_init.h (100%)
rename board/altera/{socfpga => cyclone5-socdk}/qts/sequencer_defines.h (100%)
rename board/altera/{socfpga => cyclone5-socdk}/socfpga.c (100%)arch/arm/mach-socfpga/Kconfig +2 -2
@@ -21,8 +21,8 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK endchoice config SYS_BOARD - default "socfpga" if TARGET_SOCFPGA_ARRIA5_SOCDK - default "socfpga" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
board/altera/arria5-socdk/MAINTAINERS renamed from board/altera/socfpga/MAINTAINERS +0 -0
board/altera/arria5-socdk/Makefile renamed from board/altera/socfpga/Makefile +0 -0
board/altera/arria5-socdk/qts/iocsr_config.c renamed from board/altera/socfpga/qts/iocsr_config.c +0 -0
board/altera/arria5-socdk/qts/iocsr_config.h renamed from board/altera/socfpga/qts/iocsr_config.h +0 -0
board/altera/arria5-socdk/qts/pinmux_config.c renamed from board/altera/socfpga/qts/pinmux_config.c +0 -0
board/altera/arria5-socdk/qts/pinmux_config.h renamed from board/altera/socfpga/qts/pinmux_config.h +0 -0
board/altera/arria5-socdk/qts/pll_config.h renamed from board/altera/socfpga/qts/pll_config.h +0 -0
board/altera/arria5-socdk/qts/sdram_config.h renamed from board/altera/socfpga/qts/sdram_config.h +0 -0
board/altera/arria5-socdk/qts/sequencer_auto.h renamed from board/altera/socfpga/qts/sequencer_auto.h +0 -0
board/altera/arria5-socdk/qts/sequencer_auto_ac_init.h renamed from board/altera/socfpga/qts/sequencer_auto_ac_init.h +0 -0
board/altera/arria5-socdk/qts/sequencer_auto_inst_init.h renamed from board/altera/socfpga/qts/sequencer_auto_inst_init.h +0 -0
board/altera/arria5-socdk/qts/sequencer_defines.h renamed from board/altera/socfpga/qts/sequencer_defines.h +0 -0
board/altera/arria5-socdk/socfpga.c renamed from board/altera/socfpga/socfpga.c +0 -0
board/altera/cyclone5-socdk/MAINTAINERS renamed from board/altera/socfpga/MAINTAINERS +0 -0
board/altera/cyclone5-socdk/Makefile renamed from board/altera/socfpga/Makefile +0 -0
board/altera/cyclone5-socdk/qts/iocsr_config.c renamed from board/altera/socfpga/qts/iocsr_config.c +0 -0
board/altera/cyclone5-socdk/qts/iocsr_config.h renamed from board/altera/socfpga/qts/iocsr_config.h +0 -0
board/altera/cyclone5-socdk/qts/pinmux_config.c renamed from board/altera/socfpga/qts/pinmux_config.c +0 -0
board/altera/cyclone5-socdk/qts/pinmux_config.h renamed from board/altera/socfpga/qts/pinmux_config.h +0 -0
board/altera/cyclone5-socdk/qts/pll_config.h renamed from board/altera/socfpga/qts/pll_config.h +0 -0
board/altera/cyclone5-socdk/qts/sdram_config.h renamed from board/altera/socfpga/qts/sdram_config.h +0 -0
board/altera/cyclone5-socdk/qts/sequencer_auto.h renamed from board/altera/socfpga/qts/sequencer_auto.h +0 -0
board/altera/cyclone5-socdk/qts/sequencer_auto_ac_init.h renamed from board/altera/socfpga/qts/sequencer_auto_ac_init.h +0 -0
board/altera/cyclone5-socdk/qts/sequencer_auto_inst_init.h renamed from board/altera/socfpga/qts/sequencer_auto_inst_init.h +0 -0
board/altera/cyclone5-socdk/qts/sequencer_defines.h renamed from board/altera/socfpga/qts/sequencer_defines.h +0 -0
board/altera/cyclone5-socdk/socfpga.c renamed from board/altera/socfpga/socfpga.c +0 -0
Signature · 1 line
2.1.4
PATCH 4/8 arm: socfpga: Remove CV-specific parts from AV-SoCDK
In reply to Marek VasutJust remove the CycloneV specific parts from the ArriaV SoCDK board and they are no longer needed now.
Signed-off-by Marek Vasut <[email protected]>
--- board/altera/arria5-socdk/qts/iocsr_config.c | 652 --------------------- board/altera/arria5-socdk/qts/iocsr_config.h | 9 - board/altera/arria5-socdk/qts/pinmux_config.c | 215 ------- board/altera/arria5-socdk/qts/sdram_config.h | 14 - board/altera/arria5-socdk/qts/sequencer_auto.h | 20 - .../arria5-socdk/qts/sequencer_auto_ac_init.h | 39 -- .../arria5-socdk/qts/sequencer_auto_inst_init.h | 133 ----- board/altera/arria5-socdk/qts/sequencer_defines.h | 35 -- 8 files changed, 1117 deletions(-)
board/altera/arria5-socdk/qts/iocsr_config.c +0 -652
@@ -8,657 +8,6 @@#include "iocsr_config.h" -#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 -const unsigned long iocsr_scan_chain0_table[(( -CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH /32 ) +1 )] = { -0x00000000 , -0x00000000 , -0x0FF00000 , -0xC0000000 , -0x0000003F , -0x00008000 , -0x00020080 , -0x08020000 , -0x08000000 , -0x00018020 , -0x00000000 , -0x00004000 , -0x00010040 , -0x04010000 , -0x04000000 , -0x00000010 , -0x00004010 , -0x00002000 , -0x00020000 , -0x02008000 , -0x02000000 , -0x00000008 , -0x00002008 , -0x00001000 , -}; - -const unsigned long iocsr_scan_chain1_table[(( -CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH /32 ) +1 )] = { -0x000C0300 , -0x10040000 , -0x100000C0 , -0x00000040 , -0x00010040 , -0x00008000 , -0x00080000 , -0x18060000 , -0x18000000 , -0x00000060 , -0x00018060 , -0x00004000 , -0x00010040 , -0x10000000 , -0x04000000 , -0x00000010 , -0x00004010 , -0x00002000 , -0x06008020 , -0x02008000 , -0x01FE0000 , -0xF8000000 , -0x00000007 , -0x00001000 , -0x00004010 , -0x01004000 , -0x01000000 , -0x00003004 , -0x00001004 , -0x00000800 , -0x00000000 , -0x00000000 , -0x00800000 , -0x00000002 , -0x00002000 , -0x00000400 , -0x00000000 , -0x00401000 , -0x00000003 , -0x00000000 , -0x00000000 , -0x00000200 , -0x00600802 , -0x00000000 , -0x80200000 , -0x80000600 , -0x00000200 , -0x00000100 , -0x00300401 , -0xC0100400 , -0x40100000 , -0x40000300 , -0x000C0100 , -0x00000080 , -}; - -const unsigned long iocsr_scan_chain2_table[(( -CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH /32 ) +1 )] = { -0x80040100 , -0x00000000 , -0x0FF00000 , -0x00000000 , -0x0C010040 , -0x00008000 , -0x18020080 , -0x00000000 , -0x08000000 , -0x00040020 , -0x06018060 , -0x00004000 , -0x0C010040 , -0x04010000 , -0x00000030 , -0x00000000 , -0x03004010 , -0x00002000 , -0x06008020 , -0x02008000 , -0x02000018 , -0x00006008 , -0x01802008 , -0x00001000 , -0x03004010 , -0x01004000 , -0x0100000C , -0x00003004 , -0x00C01004 , -0x00000800 , -}; - -const unsigned long iocsr_scan_chain3_table[(( -CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH /32 ) +1 )] = { -0x2C420D80 , -0x082000FF , -0x0A804001 , -0x07900000 , -0x08020000 , -0x00100000 , -0x0A800000 , -0x07900000 , -0x08020000 , -0x00100000 , -0xC8800000 , -0x00003001 , -0x00C00722 , -0x00000000 , -0x00000021 , -0x82000004 , -0x05400000 , -0x03C80000 , -0x04010000 , -0x00080000 , -0x05400000 , -0x03C80000 , -0x05400000 , -0x03C80000 , -0xE4400000 , -0x00001800 , -0x00600391 , -0x800E4400 , -0x00000001 , -0x40000002 , -0x02A00000 , -0x01E40000 , -0x02A00000 , -0x01E40000 , -0x02A00000 , -0x01E40000 , -0x02A00000 , -0x01E40000 , -0x72200000 , -0x80000C00 , -0x003001C8 , -0xC0072200 , -0x1C880000 , -0x20000300 , -0x00040000 , -0x50670000 , -0x00000070 , -0x24590000 , -0x00001000 , -0xA0000034 , -0x0D000001 , -0x906808A2 , -0xA2834024 , -0x05141A00 , -0x808A20D0 , -0x34024906 , -0x01A00A28 , -0xA20D0000 , -0x24906808 , -0x00A28340 , -0xD000001A , -0x06808A20 , -0x10040000 , -0x00200000 , -0x10040000 , -0x00200000 , -0x15000000 , -0x0F200000 , -0x15000000 , -0x0F200000 , -0x01FE0000 , -0x00000000 , -0x01800E44 , -0x00391000 , -0x007F8006 , -0x00000000 , -0x0A800001 , -0x07900000 , -0x0A800000 , -0x07900000 , -0x0A800000 , -0x07900000 , -0x08020000 , -0x00100000 , -0xC8800000 , -0x00003001 , -0x00C00722 , -0x00000FF0 , -0x72200000 , -0x80000C00 , -0x05400000 , -0x02480000 , -0x04000000 , -0x00080000 , -0x05400000 , -0x03C80000 , -0x05400000 , -0x03C80000 , -0x6A1C0000 , -0x00001800 , -0x00600391 , -0x800E4400 , -0x1A870001 , -0x40000600 , -0x02A00040 , -0x01E40000 , -0x02A00000 , -0x01E40000 , -0x02A00000 , -0x01E40000 , -0x02A00000 , -0x01E40000 , -0x72200000 , -0x80000C00 , -0x003001C8 , -0xC0072200 , -0x1C880000 , -0x20000300 , -0x00040000 , -0x50670000 , -0x00000070 , -0x24590000 , -0x00001000 , -0xA0000034 , -0x0D000001 , -0x906808A2 , -0xA2834024 , -0x05141A00 , -0x808A20D0 , -0x34024906 , -0x01A00040 , -0xA20D0002 , -0x24906808 , -0x00A28340 , -0xD005141A , -0x06808A20 , -0x10040000 , -0x00200000 , -0x10040000 , -0x00200000 , -0x15000000 , -0x0F200000 , -0x15000000 , -0x0F200000 , -0x01FE0000 , -0x00000000 , -0x01800E44 , -0x00391000 , -0x007F8006 , -0x00000000 , -0x99300001 , -0x34343400 , -0xAA0D4000 , -0x01C3A810 , -0xAA0D4000 , -0x01C3A808 , -0xAA0D4000 , -0x01C3A810 , -0x00040100 , -0x00000800 , -0x00000000 , -0x00001208 , -0x00482000 , -0x000001C1 , -0x00000000 , -0x00410482 , -0x0006A000 , -0x0001B400 , -0x00020000 , -0x00000400 , -0x0002A000 , -0x0001E400 , -0x5506A000 , -0x00E1D404 , -0x00000000 , -0xC880090C , -0x00003001 , -0x90400000 , -0x00000000 , -0x2020C243 , -0x2A835000 , -0x0070EA04 , -0x2A835000 , -0x0070EA02 , -0x2A835000 , -0x0070EA04 , -0x00010040 , -0x00000200 , -0x00000000 , -0x00000482 , -0x00120800 , -0x00002000 , -0x80000000 , -0x00104120 , -0x00000200 , -0xAC255F80 , -0xF1C71C71 , -0x14F3690D , -0x1A041414 , -0x00D00000 , -0x14864000 , -0x59647A05 , -0xBA28A3D8 , -0xF511451E , -0x0341D348 , -0x821A0000 , -0x0000D000 , -0x04510680 , -0xD859647A , -0x1EBA28A3 , -0x48F51145 , -0x000341D3 , -0x00080200 , -0x00001000 , -0x00080200 , -0x00001000 , -0x000A8000 , -0x00075000 , -0x541A8000 , -0x03875011 , -0x10000000 , -0x00000000 , -0x0080C000 , -0x41000000 , -0x00003FC2 , -0x00820000 , -0xAA0D4000 , -0x01C3A810 , -0xAA0D4000 , -0x01C3A808 , -0xAA0D4000 , -0x01C3A810 , -0x00040100 , -0x00000800 , -0x00000000 , -0x00001208 , -0x00482000 , -0x00008000 , -0x00000000 , -0x00410482 , -0x0006A000 , -0x0001B400 , -0x00020000 , -0x00000400 , -0x00020080 , -0x00000400 , -0x5506A000 , -0x00E1D404 , -0x00000000 , -0x0000090C , -0x00000010 , -0x90400000 , -0x00000000 , -0x2020C243 , -0x2A835000 , -0x0070EA04 , -0x2A835000 , -0x0070EA02 , -0x2A835000 , -0x0070EA04 , -0x00015000 , -0x0000F200 , -0x00000000 , -0x00000482 , -0x00120800 , -0x00600391 , -0x80000000 , -0x00104120 , -0x00000200 , -0xAC255F80 , -0xF1C71C71 , -0x14F3690D , -0x1A041414 , -0x00D00000 , -0x14864000 , -0x59647A05 , -0xBA28A3D8 , -0xF511451E , -0x8341D348 , -0x821A0124 , -0x0000D000 , -0x00000680 , -0xD859647A , -0x1EBA28A3 , -0x48F51145 , -0x000341D3 , -0x00080200 , -0x00001000 , -0x00080200 , -0x00001000 , -0x000A8000 , -0x00075000 , -0x541A8000 , -0x03875011 , -0x10000000 , -0x00000000 , -0x0080C000 , -0x41000000 , -0x04000002 , -0x00820000 , -0xAA0D4000 , -0x01C3A810 , -0xAA0D4000 , -0x01C3A808 , -0xAA0D4000 , -0x01C3A810 , -0x00040100 , -0x00000800 , -0x00000000 , -0x00001208 , -0x00482000 , -0x00008000 , -0x00000000 , -0x00410482 , -0x0006A000 , -0x0001B400 , -0x00020000 , -0x00000400 , -0x0002A000 , -0x0001E400 , -0x5506A000 , -0x00E1D404 , -0x00000000 , -0xC880090C , -0x00003001 , -0x90400000 , -0x00000000 , -0x2020C243 , -0x2A835000 , -0x0070EA04 , -0x2A835000 , -0x0070EA02 , -0x2A835000 , -0x0070EA04 , -0x00010040 , -0x00000200 , -0x00000000 , -0x00000482 , -0x00120800 , -0x00002000 , -0x80000000 , -0x00104120 , -0x00000200 , -0xAC255F80 , -0xF1C71C71 , -0x14F3690D , -0x1A041414 , -0x00D00000 , -0x14864000 , -0x59647A05 , -0xBA28A3D8 , -0xF511451E , -0x0341D348 , -0x821A0000 , -0x0000D000 , -0x00000680 , -0xD859647A , -0x1EBA28A3 , -0x48F51145 , -0x000341D3 , -0x00080200 , -0x00001000 , -0x00080200 , -0x00001000 , -0x000A8000 , -0x00075000 , -0x541A8000 , -0x03875011 , -0x10000000 , -0x00000000 , -0x0080C000 , -0x41000000 , -0x04000002 , -0x00820000 , -0xAA0D4000 , -0x01C3A810 , -0xAA0D4000 , -0x01C3A808 , -0xAA0D4000 , -0x01C3A810 , -0x00040100 , -0x00000800 , -0x00000000 , -0x00001208 , -0x00482000 , -0x00008000 , -0x00000000 , -0x00410482 , -0x0006A000 , -0x0001B400 , -0x00020000 , -0x00000400 , -0x00020080 , -0x00000400 , -0x5506A000 , -0x00E1D404 , -0x00000000 , -0x0000090C , -0x00000010 , -0x90400000 , -0x00000000 , -0x2020C243 , -0x2A835000 , -0x0070EA04 , -0x2A835000 , -0x0070EA02 , -0x2A835000 , -0x0070EA04 , -0x00010040 , -0x00000200 , -0x00000000 , -0x00000482 , -0x40120800 , -0x00000070 , -0x80000000 , -0x00104120 , -0x00000200 , -0xAC255F80 , -0xF1C71C71 , -0x14F1690D , -0x1A041414 , -0x00D00000 , -0x14864000 , -0x59647A05 , -0xBA28A3D8 , -0xF511451E , -0x0341D348 , -0x821A0000 , -0x0000D000 , -0x00000680 , -0xD859647A , -0x1EBA28A3 , -0x48F51145 , -0x000341D3 , -0x00080200 , -0x00001000 , -0x00080200 , -0x00001000 , -0x000A8000 , -0x00075000 , -0x541A8000 , -0x03875011 , -0x10000000 , -0x00000000 , -0x0080C000 , -0x41000000 , -0x04000002 , -0x00820000 , -0x00489800 , -0x001A1A1A , -0x085506A0 , -0x0000E1D4 , -0x045506A0 , -0x0000E1D4 , -0x085506A0 , -0x8000E1D4 , -0x00000200 , -0x00000004 , -0x04000000 , -0x00000009 , -0x00002410 , -0x00000040 , -0x41000000 , -0x00002082 , -0x00000350 , -0x000000DA , -0x00000100 , -0x40000002 , -0x00000100 , -0x00000002 , -0x022A8350 , -0x000070EA , -0x86000000 , -0x08000004 , -0x00000000 , -0x00482000 , -0x21800000 , -0x00101061 , -0x021541A8 , -0x00003875 , -0x011541A8 , -0x00003875 , -0x021541A8 , -0x20003875 , -0x00000080 , -0x00000001 , -0x41000000 , -0x00000002 , -0x00FF0904 , -0x00000000 , -0x90400000 , -0x00000820 , -0xC0000001 , -0x38D612AF , -0x86F8E38E , -0x0A0A78B4 , -0x000D020A , -0x00006800 , -0x028A4320 , -0xEC2CB23D , -0x8F5D1451 , -0xA47A88A2 , -0x0001A0E9 , -0x00410D00 , -0x40000068 , -0x3D000003 , -0x51EC2CB2 , -0xA28F5D14 , -0xE9A47A88 , -0x000001A0 , -0x00000401 , -0x00000008 , -0x00000401 , -0x00000008 , -0x00000540 , -0x000003A8 , -0x08AA0D40 , -0x8001C3A8 , -0x0000007F , -0x00000000 , -0x00004060 , -0xE1208000 , -0x0000001F , -0x00004100 , -}; -#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */ - -#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5 const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH /32 ) +1 )] = {0x00000000 ,
@@ -1342,4 +691,3 @@ const unsigned long iocsr_scan_chain3_table[((0x0000001F , 0x00004100, }; -#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */
board/altera/arria5-socdk/qts/iocsr_config.h +0 -9
@@ -9,18 +9,9 @@#ifndef _PRELOADER_IOCSR_CONFIG_H_#define _PRELOADER_IOCSR_CONFIG_H_ -#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) -#endif - -#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5 #define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (1337)#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (1528)#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) -#endif #endif /*_PRELOADER_IOCSR_CONFIG_H_*/
board/altera/arria5-socdk/qts/pinmux_config.c +0 -215
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board/altera/arria5-socdk/qts/sdram_config.h +0 -14
@@ -20,7 +20,6 @@#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#ifdef CONFIG_SOCFPGA_ARRIA5 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139
@@ -32,19 +31,6 @@#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26 -#else -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
board/altera/arria5-socdk/qts/sequencer_auto.h +0 -20
@@ -19,29 +19,14 @@#define RW_MGR_MRS2 0x04#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34#define RW_MGR_MRS1 0x03 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ #define RW_MGR_IDLE_LOOP1 0x7A -#else -#define RW_MGR_IDLE_LOOP1 0x7C -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18#define RW_MGR_MRS3 0x05 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ #define RW_MGR_IDLE_LOOP2 0x79 -#else -#define RW_MGR_IDLE_LOOP2 0x7B -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ #define RW_MGR_RDIMM_CMD 0x78 -#else -#define RW_MGR_RDIMM_CMD 0x7A -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
@@ -54,12 +39,7 @@#define RW_MGR_GUARANTEED_WRITE 0x17#define RW_MGR_PRECHARGE_ALL 0x12#define RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ #define RW_MGR_SGLE_READ 0x7C -#else -#define RW_MGR_SGLE_READ 0x7E -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define RW_MGR_MRS0_USER_MIRR 0x0C#define RW_MGR_RETURN 0x01#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
board/altera/arria5-socdk/qts/sequencer_auto_ac_init.h +0 -39
@@ -5,7 +5,6 @@*/ const uint32_t ac_rom_init[] = { -#ifdef CONFIG_SOCFPGA_ARRIA5/* The if..else... is not required if generated by tools */ 0x20700000 ,0x20780000 ,
@@ -43,42 +42,4 @@ const uint32_t ac_rom_init[] = {0x33780000 ,0x10580008 , 0x10780000 -#else -0x20700000 , -0x20780000 , -0x10080431 , -0x10080530 , -0x10090004 , -0x100a0008 , -0x100b0000 , -0x10380400 , -0x10080449 , -0x100804c8 , -0x100a0004 , -0x10090010 , -0x100b0000 , -0x30780000 , -0x38780000 , -0x30780000 , -0x10680000 , -0x106b0000 , -0x10280400 , -0x10480000 , -0x1c980000 , -0x1c9b0000 , -0x1c980008 , -0x1c9b0008 , -0x38f80000 , -0x3cf80000 , -0x38780000 , -0x18180000 , -0x18980000 , -0x13580000 , -0x135b0000 , -0x13580008 , -0x135b0008 , -0x33780000 , -0x10580008 , -0x10780000 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ };
board/altera/arria5-socdk/qts/sequencer_auto_inst_init.h +0 -133
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board/altera/arria5-socdk/qts/sequencer_defines.h +0 -35
@@ -12,39 +12,20 @@#define AC_ROM_MR2_MIRR 0000000010000#define AC_ROM_MR3_MIRR 0000000000000#define AC_ROM_MR0_CALIB -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ #define AC_ROM_MR0_DLL_RESET_MIRR 0100011001000#define AC_ROM_MR0_DLL_RESET 0100100110000#define AC_ROM_MR0_MIRR 0100001001001#define AC_ROM_MR0 0100000110001 -#else -#define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000 -#define AC_ROM_MR0_DLL_RESET 0010100110000 -#define AC_ROM_MR0_MIRR 0010001001001 -#define AC_ROM_MR0 0010000110001 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define AC_ROM_MR1 0000000000100#define AC_ROM_MR2 0000000001000#define AC_ROM_MR3 0000000000000 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ #define AFI_CLK_FREQ 534 -#else -#define AFI_CLK_FREQ 401 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define AFI_RATE_RATIO 1#define AVL_CLK_FREQ 67#define BFM_MODE 0#define BURST2 0 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ #define CALIB_LFIFO_OFFSET 8#define CALIB_VFIFO_OFFSET 6 -#else -#define CALIB_LFIFO_OFFSET 7 -#define CALIB_VFIFO_OFFSET 5 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0#define ENABLE_SUPER_QUICK_CALIBRATION 0#define GUARANTEED_READ_BRINGUP_TEST 0
@@ -54,23 +35,12 @@#define HR_DDIO_OUT_HAS_THREE_REGS 0#define IO_DELAY_PER_DCHAIN_TAP 25#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ #define IO_DELAY_PER_OPA_TAP 234 -#else -#define IO_DELAY_PER_OPA_TAP 312 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define IO_DLL_CHAIN_LENGTH 8#define IO_DM_OUT_RESERVE 0#define IO_DQDQS_OUT_PHASE_MAX 0 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ #define IO_DQS_EN_DELAY_MAX 15#define IO_DQS_EN_DELAY_OFFSET 16 -#else -#define IO_DQS_EN_DELAY_MAX 31 -#define IO_DQS_EN_DELAY_OFFSET 0 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define IO_DQS_EN_PHASE_MAX 7#define IO_DQS_IN_DELAY_MAX 31#define IO_DQS_IN_RESERVE 4
@@ -84,12 +54,7 @@#define MAX_LATENCY_COUNT_WIDTH 5#define MEM_ADDR_WIDTH 13#define READ_VALID_FIFO_SIZE 16 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ #define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c -#else -#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define RW_MGR_MEM_ADDRESS_MIRRORING 0#define RW_MGR_MEM_ADDRESS_WIDTH 15#define RW_MGR_MEM_BANK_WIDTH 3
Signature · 1 line
2.1.4
PATCH 5/8 arm: socfpga: Remove AV-specific parts from CV-SoCDK
In reply to Marek VasutJust remove the ArriaV specific parts from the CycloneV SoCDK board and they are no longer needed now.
Signed-off-by Marek Vasut <[email protected]>
--- board/altera/cyclone5-socdk/qts/iocsr_config.c | 688 --------------------- board/altera/cyclone5-socdk/qts/iocsr_config.h | 9 - board/altera/cyclone5-socdk/qts/pinmux_config.c | 215 ------- board/altera/cyclone5-socdk/qts/sdram_config.h | 14 - board/altera/cyclone5-socdk/qts/sequencer_auto.h | 20 - .../cyclone5-socdk/qts/sequencer_auto_ac_init.h | 40 -- .../cyclone5-socdk/qts/sequencer_auto_inst_init.h | 132 ---- .../altera/cyclone5-socdk/qts/sequencer_defines.h | 35 -- 8 files changed, 1153 deletions(-)
board/altera/cyclone5-socdk/qts/iocsr_config.c +0 -688
@@ -8,7 +8,6 @@#include "iocsr_config.h" -#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH /32 ) +1 )] = {0x00000000 ,
@@ -656,690 +655,3 @@ const unsigned long iocsr_scan_chain3_table[((0x0000001F , 0x00004100, }; -#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */ - -#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5 -const unsigned long iocsr_scan_chain0_table[(( -CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH /32 ) +1 )] = { -0x00000000 , -0x00000000 , -0x00000000 , -0x00000000 , -0x00000000 , -0x00008000 , -0x00060180 , -0x18060000 , -0x18000060 , -0x00018060 , -0x06018060 , -0x00004000 , -0x0C0300C0 , -0x0C030000 , -0x00000030 , -0x00000000 , -0x00000000 , -0x00002000 , -0x00000000 , -0x00000000 , -0x06000000 , -0x00006018 , -0x01806018 , -0x00001000 , -0x0000C030 , -0x04000000 , -0x03000000 , -0x0000300C , -0x00000000 , -0x00000800 , -0x00006018 , -0x01806000 , -0x01800000 , -0x00000006 , -0x00001806 , -0x00000400 , -0x0000300C , -0x00C03000 , -0x00C00000 , -0x00000003 , -0x00000C03 , -0x00000200 , -}; - -const unsigned long iocsr_scan_chain1_table[(( -CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH /32 ) +1 )] = { -0x00100000 , -0x300C0000 , -0x300000C0 , -0x000000C0 , -0x000300C0 , -0x00008000 , -0x00060180 , -0x18060000 , -0x18000000 , -0x00000060 , -0x00018060 , -0x00004000 , -0x000300C0 , -0x10000000 , -0x0C000000 , -0x00000030 , -0x0000C030 , -0x00002000 , -0x06018060 , -0x06018000 , -0x01FE0000 , -0xF8000000 , -0x00000007 , -0x00001000 , -0x0000C030 , -0x0300C000 , -0x03000000 , -0x0000300C , -0x0000300C , -0x00000800 , -0x00006018 , -0x01806000 , -0x01800000 , -0x00000006 , -0x00002000 , -0x00000400 , -0x0000300C , -0x01000000 , -0x00000000 , -0x00000004 , -0x00000C03 , -0x00000200 , -0x00001806 , -0x00800000 , -0x00000000 , -0x00000002 , -0x00000800 , -0x00000100 , -0x00001000 , -0x00400000 , -0xC0300000 , -0x00000000 , -0x00000400 , -0x00000080 , -}; - -const unsigned long iocsr_scan_chain2_table[(( -CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH /32 ) +1 )] = { -0x00100000 , -0x40000000 , -0x00000000 , -0x00000100 , -0x00040000 , -0x00008000 , -0x18060180 , -0x20000000 , -0x00000000 , -0x00000080 , -0x00020000 , -0x00004000 , -0x00040000 , -0x10000000 , -0x00000000 , -0x00000000 , -0x00010000 , -0x00002000 , -0x10038060 , -0x00000000 , -0x00000000 , -0x00000020 , -0x01806018 , -0x00001000 , -0x00010000 , -0x04000000 , -0x03000000 , -0x0000801C , -0x00004000 , -0x00000800 , -0x01806018 , -0x02000000 , -0x00000000 , -0x00000008 , -0x00002000 , -0x00000400 , -0x00C0300C , -0x00C03000 , -0x00C00003 , -0x00000C03 , -0x00300C03 , -0x00000200 , -0x00601806 , -0x80601800 , -0x80600001 , -0x80000601 , -0x00180601 , -0x00000100 , -}; - -const unsigned long iocsr_scan_chain3_table[(( -CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH /32 ) +1 )] = { -0x2C820D80 , -0x082000FF , -0x0A804001 , -0x07900000 , -0x08020000 , -0x00100000 , -0x0A800000 , -0x07900000 , -0x08020000 , -0x00100000 , -0xC8800000 , -0x00003001 , -0x00C00722 , -0x00000000 , -0x00000021 , -0x82000004 , -0x05400000 , -0x03C80000 , -0x04010000 , -0x00080000 , -0x05400000 , -0x03C80000 , -0x05400000 , -0x03C80000 , -0xE4400000 , -0x00001800 , -0x00600391 , -0x800E4400 , -0x00000001 , -0x40000002 , -0x02A00000 , -0x01E40000 , -0x02A00000 , -0x01E40000 , -0x02A00000 , -0x01E40000 , -0x02A00000 , -0x01E40000 , -0x72200000 , -0x80000C00 , -0x003001C8 , -0xC0072200 , -0x1C880000 , -0x20000300 , -0x00040000 , -0x50670000 , -0x00000050 , -0x24590000 , -0x00001000 , -0xA0000034 , -0x0D000001 , -0x906808A2 , -0xA2834024 , -0x05141A00 , -0x808A20D0 , -0x34024906 , -0x01A00A28 , -0xA20D0000 , -0x24906808 , -0x00A28340 , -0xD000001A , -0x06808A20 , -0x10040000 , -0x00200000 , -0x10040000 , -0x00200000 , -0x15000000 , -0x0F200000 , -0x15000000 , -0x0F200000 , -0x01FE0000 , -0x00000000 , -0x01800E44 , -0x00391000 , -0x007F8006 , -0x00000000 , -0x0A800001 , -0x07900000 , -0x0A800000 , -0x07900000 , -0x0A800000 , -0x07900000 , -0x08020000 , -0x00100000 , -0xC8800000 , -0x00003001 , -0x00C00722 , -0x00000FF0 , -0x72200000 , -0x80000C00 , -0x05400000 , -0x02480000 , -0x04000000 , -0x00080000 , -0x05400000 , -0x03C80000 , -0x05400000 , -0x03C80000 , -0x6A1C0000 , -0x00001800 , -0x00600391 , -0x800E4400 , -0x1A870001 , -0x40000600 , -0x02A00040 , -0x01E40000 , -0x02A00000 , -0x01E40000 , -0x02A00000 , -0x01E40000 , -0x02A00000 , -0x01E40000 , -0x72200000 , -0x80000C00 , -0x003001C8 , -0xC0072200 , -0x1C880000 , -0x20000300 , -0x00040000 , -0x50670000 , -0x00000050 , -0x24590000 , -0x00001000 , -0xA0000034 , -0x0D000001 , -0x906808A2 , -0xA2834024 , -0x05141A00 , -0x808A20D0 , -0x34024906 , -0x01A00040 , -0xA20D0002 , -0x24906808 , -0x00A28340 , -0xD005141A , -0x06808A20 , -0x10040000 , -0x00200000 , -0x10040000 , -0x00200000 , -0x15000000 , -0x0F200000 , -0x15000000 , -0x0F200000 , -0x01FE0000 , -0x00000000 , -0x01800E44 , -0x00391000 , -0x007F8006 , -0x00000000 , -0x99300001 , -0x34343400 , -0xAA0D4000 , -0x01C3A810 , -0xAA0D4000 , -0x01C3A808 , -0xAA0D4000 , -0x01C3A810 , -0x00040100 , -0x00000800 , -0x00000000 , -0x00001208 , -0x00482000 , -0x01000000 , -0x00000000 , -0x00410482 , -0x0006A000 , -0x0001B400 , -0x00020000 , -0x00000400 , -0x0002A000 , -0x0001E400 , -0x5506A000 , -0x00E1D404 , -0x00000000 , -0xC880090C , -0x00003001 , -0x90400000 , -0x00000000 , -0x2020C243 , -0x2A835000 , -0x0070EA04 , -0x2A835000 , -0x0070EA02 , -0x2A835000 , -0x0070EA04 , -0x00010040 , -0x00000200 , -0x00000000 , -0x00000482 , -0x00120800 , -0x00002000 , -0x80000000 , -0x00104120 , -0x00000200 , -0xAC055F80 , -0xFFFFFFFF , -0x14F3690D , -0x1A041414 , -0x00D00000 , -0x14864000 , -0x59647A05 , -0xBA28A3D8 , -0xF511451E , -0x0341D348 , -0x821A0000 , -0x0000D000 , -0x04510680 , -0xD859647A , -0x1EBA28A3 , -0x48F51145 , -0x000341D3 , -0x00080200 , -0x00001000 , -0x00080200 , -0x00001000 , -0x000A8000 , -0x00075000 , -0x541A8000 , -0x03875011 , -0x10000000 , -0x00000000 , -0x0080C000 , -0x41000000 , -0x00003FC2 , -0x00820000 , -0xAA0D4000 , -0x01C3A810 , -0xAA0D4000 , -0x01C3A808 , -0xAA0D4000 , -0x01C3A810 , -0x00040100 , -0x00000800 , -0x00000000 , -0x00001208 , -0x00482000 , -0x00008000 , -0x00000000 , -0x00410482 , -0x0006A000 , -0x0001B400 , -0x00020000 , -0x00000400 , -0x00020080 , -0x00000400 , -0x5506A000 , -0x00E1D404 , -0x00000000 , -0x0000090C , -0x00000010 , -0x90400000 , -0x00000000 , -0x2020C243 , -0x2A835000 , -0x0070EA04 , -0x2A835000 , -0x0070EA02 , -0x2A835000 , -0x0070EA04 , -0x00015000 , -0x0000F200 , -0x00000000 , -0x00000482 , -0x00120800 , -0x00600391 , -0x80000000 , -0x00104120 , -0x00000200 , -0xAC055F80 , -0xFFFFFFFF , -0x14F3690D , -0x1A041414 , -0x00D00000 , -0x14864000 , -0x59647A05 , -0xBA28A3D8 , -0xF511451E , -0x8341D348 , -0x821A0124 , -0x0000D000 , -0x00000680 , -0xD859647A , -0x1EBA28A3 , -0x48F51145 , -0x000341D3 , -0x00080200 , -0x00001000 , -0x00080200 , -0x00001000 , -0x000A8000 , -0x00075000 , -0x541A8000 , -0x03875011 , -0x10000000 , -0x00000000 , -0x0080C000 , -0x41000000 , -0x04000002 , -0x00820000 , -0xAA0D4000 , -0x01C3A810 , -0xAA0D4000 , -0x01C3A808 , -0xAA0D4000 , -0x01C3A810 , -0x00040100 , -0x00000800 , -0x00000000 , -0x00001208 , -0x00482000 , -0x00008000 , -0x00000000 , -0x00410482 , -0x0006A000 , -0x0001B400 , -0x00020000 , -0x00000400 , -0x0002A000 , -0x0001E400 , -0x5506A000 , -0x00E1D404 , -0x00000000 , -0xC880090C , -0x00003001 , -0x90400000 , -0x00000000 , -0x2020C243 , -0x2A835000 , -0x0070EA04 , -0x2A835000 , -0x0070EA02 , -0x2A835000 , -0x0070EA04 , -0x00010040 , -0x00000200 , -0x00000000 , -0x00000482 , -0x00120800 , -0x00002000 , -0x80000000 , -0x00104120 , -0x00000200 , -0xAC055F80 , -0xFFFFFFFF , -0x14F3690D , -0x1A041414 , -0x00D00000 , -0x14864000 , -0x59647A05 , -0xBA28A3D8 , -0xF511451E , -0x0341D348 , -0x821A0000 , -0x0000D000 , -0x00000680 , -0xD859647A , -0x1EBA28A3 , -0x48F51145 , -0x000341D3 , -0x00080200 , -0x00001000 , -0x00080200 , -0x00001000 , -0x000A8000 , -0x00075000 , -0x541A8000 , -0x03875011 , -0x10000000 , -0x00000000 , -0x0080C000 , -0x41000000 , -0x04000002 , -0x00820000 , -0xAA0D4000 , -0x01C3A810 , -0xAA0D4000 , -0x01C3A808 , -0xAA0D4000 , -0x01C3A810 , -0x00040100 , -0x00000800 , -0x00000000 , -0x00001208 , -0x00482000 , -0x00008000 , -0x00000000 , -0x00410482 , -0x0006A000 , -0x0001B400 , -0x00020000 , -0x00000400 , -0x00020080 , -0x00000400 , -0x5506A000 , -0x00E1D404 , -0x00000000 , -0x0000090C , -0x00000010 , -0x90400000 , -0x00000000 , -0x2020C243 , -0x2A835000 , -0x0070EA04 , -0x2A835000 , -0x0070EA02 , -0x2A835000 , -0x0070EA04 , -0x00010040 , -0x00000200 , -0x00000000 , -0x00000482 , -0x00120800 , -0x00400000 , -0x80000000 , -0x00104120 , -0x00000200 , -0xAC055F80 , -0xFFFFFFFF , -0x14F1690D , -0x1A041414 , -0x00D00000 , -0x14864000 , -0x59647A05 , -0xBA28A3D8 , -0xF511451E , -0x0341D348 , -0x821A0000 , -0x0000D000 , -0x00000680 , -0xD859647A , -0x1EBA28A3 , -0x48F51145 , -0x000341D3 , -0x00080200 , -0x00001000 , -0x00080200 , -0x00001000 , -0x000A8000 , -0x00075000 , -0x541A8000 , -0x03875011 , -0x10000000 , -0x00000000 , -0x0080C000 , -0x41000000 , -0x04000002 , -0x00820000 , -0x00481800 , -0x001A1A1A , -0x085506A0 , -0x0000E1D4 , -0x045506A0 , -0x0000E1D4 , -0x085506A0 , -0x8000E1D4 , -0x00000200 , -0x00000004 , -0x04000000 , -0x00000009 , -0x00002410 , -0x00000040 , -0x41000000 , -0x00002082 , -0x00000350 , -0x000000DA , -0x00000100 , -0x40000002 , -0x00000100 , -0x00000002 , -0x022A8350 , -0x000070EA , -0x86000000 , -0x08000004 , -0x00000000 , -0x00482000 , -0x21800000 , -0x00101061 , -0x021541A8 , -0x00003875 , -0x011541A8 , -0x00003875 , -0x021541A8 , -0x20003875 , -0x00000080 , -0x00000001 , -0x41000000 , -0x00000002 , -0x00FF0904 , -0x00000000 , -0x90400000 , -0x00000820 , -0xC0000001 , -0xFFD602AF , -0x86FFFFFF , -0x0A0A78B4 , -0x000D020A , -0x00006800 , -0x028A4320 , -0xEC2CB23D , -0x8F5D1451 , -0xA47A88A2 , -0x0001A0E9 , -0x00410D00 , -0x40000068 , -0x3D000003 , -0x51EC2CB2 , -0xA28F5D14 , -0xE9A47A88 , -0x000001A0 , -0x00000401 , -0x00000008 , -0x00000401 , -0x00000008 , -0x00000540 , -0x000003A8 , -0x08AA0D40 , -0x8001C3A8 , -0x0000007F , -0x00000000 , -0x00004060 , -0xE1208000 , -0x0000001F , -0x00004100 , -}; -#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */
board/altera/cyclone5-socdk/qts/iocsr_config.h +0 -9
@@ -9,18 +9,9 @@#ifndef _PRELOADER_IOCSR_CONFIG_H_#define _PRELOADER_IOCSR_CONFIG_H_ -#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 #define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764)#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955)#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) -#endif - -#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5 -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (1337) -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (1528) -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) -#endif #endif /*_PRELOADER_IOCSR_CONFIG_H_*/
board/altera/cyclone5-socdk/qts/pinmux_config.c +0 -215
224 lines not on this page · raw message
board/altera/cyclone5-socdk/qts/sdram_config.h +0 -14
@@ -20,19 +20,6 @@#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#ifdef CONFIG_SOCFPGA_ARRIA5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26 -#else #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
@@ -44,7 +31,6 @@#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
board/altera/cyclone5-socdk/qts/sequencer_auto.h +0 -20
@@ -19,29 +19,14 @@#define RW_MGR_MRS2 0x04#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34#define RW_MGR_MRS1 0x03 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define RW_MGR_IDLE_LOOP1 0x7A -#else #define RW_MGR_IDLE_LOOP1 0x7C -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18#define RW_MGR_MRS3 0x05 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define RW_MGR_IDLE_LOOP2 0x79 -#else #define RW_MGR_IDLE_LOOP2 0x7B -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define RW_MGR_RDIMM_CMD 0x78 -#else #define RW_MGR_RDIMM_CMD 0x7A -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
@@ -54,12 +39,7 @@#define RW_MGR_GUARANTEED_WRITE 0x17#define RW_MGR_PRECHARGE_ALL 0x12#define RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define RW_MGR_SGLE_READ 0x7C -#else #define RW_MGR_SGLE_READ 0x7E -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define RW_MGR_MRS0_USER_MIRR 0x0C#define RW_MGR_RETURN 0x01#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
board/altera/cyclone5-socdk/qts/sequencer_auto_ac_init.h +0 -40
@@ -5,45 +5,6 @@*/ const uint32_t ac_rom_init[] = { -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -0x20700000 , -0x20780000 , -0x10080831 , -0x10080930 , -0x10090004 , -0x100a0008 , -0x100b0000 , -0x10380400 , -0x10080849 , -0x100808c8 , -0x100a0004 , -0x10090010 , -0x100b0000 , -0x30780000 , -0x38780000 , -0x30780000 , -0x10680000 , -0x106b0000 , -0x10280400 , -0x10480000 , -0x1c980000 , -0x1c9b0000 , -0x1c980008 , -0x1c9b0008 , -0x38f80000 , -0x3cf80000 , -0x38780000 , -0x18180000 , -0x18980000 , -0x13580000 , -0x135b0000 , -0x13580008 , -0x135b0008 , -0x33780000 , -0x10580008 , - 0x10780000 -#else0x20700000 ,0x20780000 ,0x10080431 ,
@@ -80,5 +41,4 @@ const uint32_t ac_rom_init[] = {0x33780000 ,0x10580008 , 0x10780000 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ };
board/altera/cyclone5-socdk/qts/sequencer_auto_inst_init.h +0 -132
141 lines not on this page · raw message
board/altera/cyclone5-socdk/qts/sequencer_defines.h +0 -35
@@ -12,39 +12,20 @@#define AC_ROM_MR2_MIRR 0000000010000#define AC_ROM_MR3_MIRR 0000000000000#define AC_ROM_MR0_CALIB -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define AC_ROM_MR0_DLL_RESET_MIRR 0100011001000 -#define AC_ROM_MR0_DLL_RESET 0100100110000 -#define AC_ROM_MR0_MIRR 0100001001001 -#define AC_ROM_MR0 0100000110001 -#else #define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000#define AC_ROM_MR0_DLL_RESET 0010100110000#define AC_ROM_MR0_MIRR 0010001001001#define AC_ROM_MR0 0010000110001 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define AC_ROM_MR1 0000000000100#define AC_ROM_MR2 0000000001000#define AC_ROM_MR3 0000000000000 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define AFI_CLK_FREQ 534 -#else #define AFI_CLK_FREQ 401 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define AFI_RATE_RATIO 1#define AVL_CLK_FREQ 67#define BFM_MODE 0#define BURST2 0 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define CALIB_LFIFO_OFFSET 8 -#define CALIB_VFIFO_OFFSET 6 -#else #define CALIB_LFIFO_OFFSET 7#define CALIB_VFIFO_OFFSET 5 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0#define ENABLE_SUPER_QUICK_CALIBRATION 0#define GUARANTEED_READ_BRINGUP_TEST 0
@@ -54,23 +35,12 @@#define HR_DDIO_OUT_HAS_THREE_REGS 0#define IO_DELAY_PER_DCHAIN_TAP 25#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define IO_DELAY_PER_OPA_TAP 234 -#else #define IO_DELAY_PER_OPA_TAP 312 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define IO_DLL_CHAIN_LENGTH 8#define IO_DM_OUT_RESERVE 0#define IO_DQDQS_OUT_PHASE_MAX 0 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define IO_DQS_EN_DELAY_MAX 15 -#define IO_DQS_EN_DELAY_OFFSET 16 -#else #define IO_DQS_EN_DELAY_MAX 31#define IO_DQS_EN_DELAY_OFFSET 0 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define IO_DQS_EN_PHASE_MAX 7#define IO_DQS_IN_DELAY_MAX 31#define IO_DQS_IN_RESERVE 4
@@ -84,12 +54,7 @@#define MAX_LATENCY_COUNT_WIDTH 5#define MEM_ADDR_WIDTH 13#define READ_VALID_FIFO_SIZE 16 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c -#else #define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define RW_MGR_MEM_ADDRESS_MIRRORING 0#define RW_MGR_MEM_ADDRESS_WIDTH 15#define RW_MGR_MEM_BANK_WIDTH 3
Signature · 1 line
2.1.4
PATCH 6/8 arm: socfpga: Add qts-filter.sh script
In reply to Marek VasutAdd script which loads the QTS-generated sources and headers and converts them into sensible format which can be used with much more easy in mainline U-Boot. The script also filters out macros which makes no sense anymore, so they don't pollute namespace and waste space.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/qts-filter.sh | 205 ++++++++++++++++++++++++++++++++++++ 1 file changed, 205 insertions(+) create mode 100755 arch/arm/mach-socfpga/qts-filter.sh
arch/arm/mach-socfpga/qts-filter.sh new file +118 -0
@@ -0,0 +1,205 @@ +#!/bin/sh + +# +# Process iocsr_config_*.[ch] +# $1: SoC type +# $2: Input directory +# $3: Output directory +# +process_iocsr_config() { + soc="$1" + in_dir="$2" + out_dir="$3" + + ( + cat << EOF +/* + * Altera SoCFPGA IOCSR configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +EOF + + # Retrieve the scan chain lengths + grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \ + ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()" + + echo "" + + # Retrieve the scan chain config and zap the ad-hoc length encoding + sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \ + ${in_dir}/generated/iocsr_config_${soc}.c + + cat << EOF + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ +EOF + ) > "${out_dir}/iocsr_config.h" +} + +# +# Process pinmux_config_*.c (and ignore pinmux_config.h) +# $1: SoC type +# $2: Input directory +# $3: Output directory +# +process_pinmux_config() { + soc="$1" + in_dir="$2" + out_dir="$3" + + ( + cat << EOF +/* + * Altera SoCFPGA PinMux configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +EOF + + # Retrieve the pinmux config and zap the ad-hoc length encoding + sed -n '/^unsigned/ !b; :next {/^unsigned/ s/\[.*\]/[]/;p;n;b next}' \ + ${in_dir}/generated/pinmux_config_${soc}.c + + cat << EOF + +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ +EOF + ) > "${out_dir}/pinmux_config.h" +} + +# +# Process pll_config.h +# $1: SoC type (not used) +# $2: Input directory +# $3: Output directory +# +process_pll_config() { + soc="$1" + in_dir="$2" + out_dir="$3" + + ( + cat << EOF +/* + * Altera SoCFPGA Clock and PLL configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +EOF + + # Retrieve the pll config and zap parenthesis + sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' \ + ${in_dir}/generated/pll_config.h + + cat << EOF + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ +EOF + ) > "${out_dir}/pll_config.h" +} + +# +# Filter out only the macros which are actually used by the code +# +grep_sdram_config() { + egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_
SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CT RLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_ AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WA IT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNT R0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL)[[:space:]]"
+}
+
+#
+# Process sdram_config.h, sequencer_auto*h and sequencer_defines.h
+# $1: SoC type (not used)
+# $2: Input directory
+# $3: Output directory
+#
+process_sdram_config() {
+ soc="$1"
+ in_dir="$2"
+ out_dir="$3"
+
+ (
+ cat << EOF
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+EOF
+
+ echo "/* SDRAM configuration */"
+ # Retrieve the sdram config, zap broken lines and zap parenthesis
+ sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" ${in_dir}/generated/sdram/sdram_config.h |
+ sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
+ sort -u | grep_sdram_config
+
+ echo ""
+ echo "/* Sequencer auto configuration */"
+ sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
+ ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u | grep_sdram_config
+
+ echo ""
+ echo "/* Sequencer defines configuration */"
+ sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
+ ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u | grep_sdram_config
+
+ echo ""
+ echo "/* Sequencer ac_rom_init configuration */"
+ sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
+ ${in_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
+
+ echo ""
+ echo "/* Sequencer inst_rom_init configuration */"
+ sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
+ ${in_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
+
+ cat << EOF
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
+EOF
+ ) > "${out_dir}/sdram_config.h"
+}
+
+usage() {
+ echo "$0 [soc_type] [input_dir] [output_dir]"
+ echo "Process QTS-generated headers into U-Boot compatible ones."
+ echo ""
+ echo " soc_type\t\tType of SoC, either 'cyclone5' or 'arria5'," + echo " input_dir\t\tDirectory with the QTS project." + echo " output_dir\t\tDirectory to store the U-Boot compatible headers."
+ echo ""
+}
+
+soc="$1"
+in_dir="$2"
+out_dir="$3"
+
+if [ "$#" -ne 3 ] ; then
+ usage
+ exit 1
+fi
+
+if [ ! -d "${in_dir}" -o ! -d "${out_dir}" -o -z "${soc}" ] ; then
+ usage
+ exit 3
+fi
+
+process_iocsr_config "${soc}" "${in_dir}" "${out_dir}" +process_pinmux_config "${soc}" "${in_dir}" "${out_dir}"
+process_pll_config "${soc}" "${in_dir}" "${out_dir}"
+process_sdram_config "${soc}" "${in_dir}" "${out_dir}"
Signature · 1 line
2.1.4
PATCH 7/8 arm: socfpga: Switch to filtered QTS files
In reply to Marek VasutSigned-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/wrap_iocsr_config.c | 7 +- arch/arm/mach-socfpga/wrap_pinmux_config.c | 23 +- arch/arm/mach-socfpga/wrap_sdram_config.c | 8 +- board/altera/arria5-socdk/qts/iocsr_config.c | 693 -------------------- board/altera/arria5-socdk/qts/iocsr_config.h | 699 ++++++++++++++++++++- board/altera/arria5-socdk/qts/pinmux_config.c | 214 ------- board/altera/arria5-socdk/qts/pinmux_config.h | 265 ++++++-- board/altera/arria5-socdk/qts/pll_config.h | 172 +++-- board/altera/arria5-socdk/qts/sdram_config.h | 362 +++++++++-- board/altera/arria5-socdk/qts/sequencer_auto.h | 108 ---- .../arria5-socdk/qts/sequencer_auto_ac_init.h | 45 -- .../arria5-socdk/qts/sequencer_auto_inst_init.h | 135 ---- board/altera/arria5-socdk/qts/sequencer_defines.h | 87 --- board/altera/cyclone5-socdk/qts/iocsr_config.c | 657 ------------------- board/altera/cyclone5-socdk/qts/iocsr_config.h | 663 ++++++++++++++++++- board/altera/cyclone5-socdk/qts/pinmux_config.c | 214 ------- board/altera/cyclone5-socdk/qts/pinmux_config.h | 265 ++++++-- board/altera/cyclone5-socdk/qts/pll_config.h | 172 +++-- board/altera/cyclone5-socdk/qts/sdram_config.h | 364 +++++++++-- board/altera/cyclone5-socdk/qts/sequencer_auto.h | 108 ---- .../cyclone5-socdk/qts/sequencer_auto_ac_init.h | 44 -- .../cyclone5-socdk/qts/sequencer_auto_inst_init.h | 136 ---- .../altera/cyclone5-socdk/qts/sequencer_defines.h | 87 --- 23 files changed, 2546 insertions(+), 2982 deletions(-) delete mode 100644 board/altera/arria5-socdk/qts/iocsr_config.c delete mode 100644 board/altera/arria5-socdk/qts/pinmux_config.c delete mode 100644 board/altera/arria5-socdk/qts/sequencer_auto.h delete mode 100644 board/altera/arria5-socdk/qts/sequencer_auto_ac_init.h delete mode 100644 board/altera/arria5-socdk/qts/sequencer_auto_inst_init.h delete mode 100644 board/altera/arria5-socdk/qts/sequencer_defines.h delete mode 100644 board/altera/cyclone5-socdk/qts/iocsr_config.c delete mode 100644 board/altera/cyclone5-socdk/qts/pinmux_config.c delete mode 100644 board/altera/cyclone5-socdk/qts/sequencer_auto.h delete mode 100644 board/altera/cyclone5-socdk/qts/sequencer_auto_ac_init.h delete mode 100644 board/altera/cyclone5-socdk/qts/sequencer_auto_inst_init.h delete mode 100644 board/altera/cyclone5-socdk/qts/sequencer_defines.h
arch/arm/mach-socfpga/wrap_iocsr_config.c +3 -4
@@ -7,10 +7,9 @@#include <common.h> #include <errno.h> #include <asm/arch/clock_manager.h> -/* -* Yes, dear reader, we're including a C file here, this is no mistake :-) -*/ -#include <qts/iocsr_config.c> + +/* Board-specific header. */ +#include <qts/iocsr_config.h> int iocsr_get_config_table(const unsigned int chain_id, const unsigned long **table,
arch/arm/mach-socfpga/wrap_pinmux_config.c +3 -20
@@ -6,26 +6,9 @@#include <common.h> #include <errno.h> -/* -* Yes, dear reader, we're including a C file here, this is no mistake. -* But this time around, we do even more perverse hacking here to be -* compatible with QTS headers and obtain reasonably nice results too. -* -* First, we define _PRELOADER_PINMUX_CONFIG_H_, which will neutralise -* the pinmux_config.h inclusion in pinmux_config.c . Since we are -* probing everything from DT, we do NOT want those macros from the -* pinmux_config.h to ooze into our build system, anywhere, ever. So -* we nip it at the bud. -* -* Next, pinmux_config.c needs CONFIG_HPS_PINMUX_NUM and uses it to -* specify sized array explicitly. Instead, we want to use ARRAY_SIZE -* to figure out the size of the array, so define this macro as an -* empty one, so that the preprocessor optimizes things such that the -* arrays are not sized by default. -*/ -#define _PRELOADER_PINMUX_CONFIG_H_ -#define CONFIG_HPS_PINMUX_NUM -#include <qts/pinmux_config.c> + +/* Board-specific header. */ +#include <qts/pinmux_config.h> void sysmgr_get_pinmux_table (const unsigned long **table,unsigned int *table_len)
arch/arm/mach-socfpga/wrap_sdram_config.c +2 -6
@@ -7,13 +7,9 @@#include <common.h> #include <errno.h> #include <asm/arch/sdram.h> -/* QTS output file. */ -#include <qts/sdram_config.h> -#include <qts/sequencer_auto_ac_init.h> -#include <qts/sequencer_auto_inst_init.h> -#include <qts/sequencer_auto.h> -#include <qts/sequencer_defines.h> +/* Board-specific header. */ +#include <qts/sdram_config.h> static const struct socfpga_sdram_config sdram_config = { .ctrl_cfg =
board/altera/arria5-socdk/qts/iocsr_config.c deleted +0 -0
board/altera/arria5-socdk/qts/iocsr_config.h +689 -10
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board/altera/arria5-socdk/qts/pinmux_config.c deleted +0 -0
board/altera/arria5-socdk/qts/pinmux_config.h +215 -50
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board/altera/arria5-socdk/qts/pll_config.h +74 -98
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board/altera/arria5-socdk/qts/sdram_config.h +308 -54
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board/altera/arria5-socdk/qts/sequencer_auto.h deleted +0 -0
board/altera/arria5-socdk/qts/sequencer_auto_ac_init.h deleted +0 -0
board/altera/arria5-socdk/qts/sequencer_auto_inst_init.h deleted +0 -0
board/altera/arria5-socdk/qts/sequencer_defines.h deleted +0 -0
board/altera/cyclone5-socdk/qts/iocsr_config.c deleted +0 -0
board/altera/cyclone5-socdk/qts/iocsr_config.h +653 -10
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board/altera/cyclone5-socdk/qts/pinmux_config.c deleted +0 -0
board/altera/cyclone5-socdk/qts/pinmux_config.h +215 -50
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board/altera/cyclone5-socdk/qts/pll_config.h +74 -98
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board/altera/cyclone5-socdk/qts/sdram_config.h +310 -54
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board/altera/cyclone5-socdk/qts/sequencer_auto.h deleted +0 -0
board/altera/cyclone5-socdk/qts/sequencer_auto_ac_init.h deleted +0 -0
board/altera/cyclone5-socdk/qts/sequencer_auto_inst_init.h deleted +0 -0
board/altera/cyclone5-socdk/qts/sequencer_defines.h deleted +0 -0
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Signature · 1 line
2.1.4
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PATCH 8/8 arm: socfpga: Make the pinmux table const u8
In reply to Marek VasutNow that we're actually converting the QTS-generated header files, we can even adjust their data types. A good candidate for this is the pinmux table, where each entry can have value in the range of 0..3, but each element is declared as unsigned long. By changing the type to u8, we can save over 600 Bytes from the SPL, so do it. This patch also constifies the array.
Signed-off-by Marek Vasut <[email protected]>
--- arch/arm/mach-socfpga/include/mach/system_manager.h | 3 +-- arch/arm/mach-socfpga/qts-filter.sh | 2 +- arch/arm/mach-socfpga/system_manager.c | 2 +- arch/arm/mach-socfpga/wrap_pinmux_config.c | 3 +-- board/altera/arria5-socdk/qts/pinmux_config.h | 2 +- board/altera/cyclone5-socdk/qts/pinmux_config.h | 2 +- 6 files changed, 6 insertions(+), 8 deletions(-)
arch/arm/mach-socfpga/include/mach/system_manager.h +1 -2
@@ -12,8 +12,7 @@void sysmgr_pinmux_init (void );void sysmgr_config_warmrstcfgio (int enable); -void sysmgr_get_pinmux_table (const unsigned long **table, -unsigned int *table_len); +void sysmgr_get_pinmux_table (const u8 **table,unsigned int *table_len);#endif struct socfpga_system_manager {
arch/arm/mach-socfpga/qts-filter.sh +1 -1
@@ -66,7 +66,7 @@ process_pinmux_config() { EOF # Retrieve the pinmux config and zap the ad-hoc length encoding - sed -n '/^unsigned/ !b; :next {/^unsigned/ s/\[.*\]/[]/;p;n;b next}' \ + sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/s/unsigned long/const u8/};p;n;b next}' \ ${in_dir}/generated/pinmux_config_${soc}.c cat << EOF
arch/arm/mach-socfpga/system_manager.c +1 -1
@@ -57,7 +57,7 @@ static void populate_sysmgr_fpgaintf_module(void)void sysmgr_pinmux_init (void ) {uint32_t regs = (uint32_t )&sysmgr_regs->emacio[0 ]; -const unsigned long *sys_mgr_init_table; +const u8 *sys_mgr_init_table;unsigned int len;int i;
arch/arm/mach-socfpga/wrap_pinmux_config.c +1 -2
@@ -10,8 +10,7 @@/* Board-specific header. */ #include <qts/pinmux_config.h> -void sysmgr_get_pinmux_table (const unsigned long **table, -unsigned int *table_len) +void sysmgr_get_pinmux_table (const u8 **table,unsigned int *table_len) { *table = sys_mgr_init_table; *table_len =ARRAY_SIZE (sys_mgr_init_table);
board/altera/arria5-socdk/qts/pinmux_config.h +1 -1
@@ -7,7 +7,7 @@#ifndef __SOCFPGA_PINMUX_CONFIG_H__#define __SOCFPGA_PINMUX_CONFIG_H__ -unsigned long sys_mgr_init_table[] = { +const u8 sys_mgr_init_table[] = {0 ,/* EMACIO0 */ 2 ,/* EMACIO1 */ 2, /* EMACIO2 */
board/altera/cyclone5-socdk/qts/pinmux_config.h +1 -1
@@ -7,7 +7,7 @@#ifndef __SOCFPGA_PINMUX_CONFIG_H__#define __SOCFPGA_PINMUX_CONFIG_H__ -unsigned long sys_mgr_init_table[] = { +const u8 sys_mgr_init_table[] = {3 ,/* EMACIO0 */ 3 ,/* EMACIO1 */ 3, /* EMACIO2 */
Signature · 1 line
2.1.4
PATCH 8/8 arm: socfpga: Make the pinmux table const u8
Quoted 36 lines · Marek Vasut
Now that we're actually converting the QTS-generated header files, we can even adjust their data types. A good candidate for this is the pinmux table, where each entry can have value in the range of 0..3, but each element is declared as unsigned long. By changing the type to u8, we can save over 600 Bytes from the SPL, so do it. This patch also constifies the array.
Signed-off-by Marek Vasut <[email protected]>--- arch/arm/mach-socfpga/include/mach/system_manager.h | 3 +-- arch/arm/mach-socfpga/qts-filter.sh | 2 +- arch/arm/mach-socfpga/system_manager.c | 2 +- arch/arm/mach-socfpga/wrap_pinmux_config.c | 3 +-- board/altera/arria5-socdk/qts/pinmux_config.h | 2 +- board/altera/cyclone5-socdk/qts/pinmux_config.h | 2 +- 6 files changed, 6 insertions(+), 8 deletions(-)arch/arm/mach-socfpga/include/mach/system_manager.h +1
-2@@ -12,8 +12,7 @@void sysmgr_pinmux_init (void );void sysmgr_config_warmrstcfgio (int enable); -void sysmgr_get_pinmux_table (const unsigned long **table, -unsigned int *table_len); +void sysmgr_get_pinmux_table (const u8 **table,unsigned int *table_len);#endif struct socfpga_system_manager {arch/arm/mach-socfpga/qts-filter.sh +0
-0
arch/arm/mach-socfpga/qts-filter.sh process_pinmux_config() { · line 71
Quoted 7 lines
arch/arm/mach-socfpga/qts-filter.sh +1
-1@@ -66,7 +66,7 @@ process_pinmux_config() { EOF # Retrieve the pinmux config and zap the ad-hoc length encoding - sed -n '/^unsigned/ !b; :next {/^unsigned/ s/\[.*\]/[]/;p;n;b next}' \ + sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/s/unsigned long/const u8/};p;n;b next}' \ ${in_dir}/generated/pinmux_config_${soc}.c
Should this change be in it's own patch?
Thanks,
Dinh
PATCH 8/8 arm: socfpga: Make the pinmux table const u8
Quoted 47 lines · Dinh Nguyen
Quoted 46 lines · Marek Vasut
Now that we're actually converting the QTS-generated header files, we can even adjust their data types. A good candidate for this is the pinmux table, where each entry can have value in the range of 0..3, but each element is declared as unsigned long. By changing the type to u8, we can save over 600 Bytes from the SPL, so do it. This patch also constifies the array.
Signed-off-by Marek Vasut <[email protected]>---
arch/arm/mach-socfpga/include/mach/system_manager.h | 3 +-- arch/arm/mach-socfpga/qts-filter.sh | 2 +- arch/arm/mach-socfpga/system_manager.c | 2 +- arch/arm/mach-socfpga/wrap_pinmux_config.c | 3 +-- board/altera/arria5-socdk/qts/pinmux_config.h | 2 +- board/altera/cyclone5-socdk/qts/pinmux_config.h | 2 +- 6 files changed, 6 insertions(+), 8 deletions(-)(quoted diff) +0
-0
b/arch/arm/mach-socfpga/include/mach/system_manager.hindex 46af30b..8712f8e 100644arch/arm/mach-socfpga/include/mach/system_manager.h +1
-2@@ -12,8 +12,7 @@void sysmgr_pinmux_init (void );void sysmgr_config_warmrstcfgio (int enable); -void sysmgr_get_pinmux_table (const unsigned long **table, -unsigned int *table_len); +void sysmgr_get_pinmux_table (const u8 **table,unsigned int *table_len);#endif struct
socfpga_system_manager{(quoted diff) +0
-0
b/arch/arm/mach-socfpga/qts-filter.shindex 16d3a2a..fc41d99 100755arch/arm/mach-socfpga/qts-filter.sh +0
-0@@ -66,7 +66,7 @@ process_pinmux_config() { EOF # Retrieve the pinmux config and zap the ad-hoc length encoding
Quoted 7 lines
Quoted 5 lines
arch/arm/mach-socfpga/qts-filter.sh +1
-1- sed -n '/^unsigned/ !b; :next {/^unsigned/ s/\[.*\]/[]/;p;n;b next}' \ + sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/s/unsigned long/const u8/};p;n;b next}' \
${in_dir}/generated/pinmux_config_${soc}.cShould this change be in it's own patch?
Not really, I think you want to change all the places atomically.
Best regards,
Marek Vasut
PATCH 8/8 arm: socfpga: Make the pinmux table const u8
Hi Marek,
the last sed line is invalid for my GNU sed 4.2.2. Maybe missed a semicolon?
sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}' \
# ^here
Best regards,
*Jian Luo
DC-IA/EAH2*
Tel. +49(9352)18-4266
*Be**QIK
*
Quoted 62 lines · Marek Vasut
Quoted 45 lines · Dinh Nguyen
Quoted 44 lines · Marek Vasut
Now that we're actually converting the QTS-generated header files, we can even adjust their data types. A good candidate for this is the pinmux table, where each entry can have value in the range of 0..3, but each element is declared as unsigned long. By changing the type to u8, we can save over 600 Bytes from the SPL, so do it. This patch also constifies the array.
Signed-off-by Marek Vasut <[email protected]>---
arch/arm/mach-socfpga/include/mach/system_manager.h | 3 +-- arch/arm/mach-socfpga/qts-filter.sh | 2 +- arch/arm/mach-socfpga/system_manager.c | 2 +- arch/arm/mach-socfpga/wrap_pinmux_config.c | 3 +-- board/altera/arria5-socdk/qts/pinmux_config.h | 2 +- board/altera/cyclone5-socdk/qts/pinmux_config.h | 2 +- 6 files changed, 6 insertions(+), 8 deletions(-)(quoted diff) +0
-0
b/arch/arm/mach-socfpga/include/mach/system_manager.hindex 46af30b..8712f8e 100644arch/arm/mach-socfpga/include/mach/system_manager.h +1
-2@@ -12,8 +12,7 @@void sysmgr_pinmux_init (void );void sysmgr_config_warmrstcfgio (int enable); -void sysmgr_get_pinmux_table (const unsigned long **table, -unsigned int *table_len); +void sysmgr_get_pinmux_table (const u8 **table,unsigned int *table_len);#endif struct socfpga_system_manager {(quoted diff) +0
-0
b/arch/arm/mach-socfpga/qts-filter.shindex 16d3a2a..fc41d99 100755arch/arm/mach-socfpga/qts-filter.sh +0
-0@@ -66,7 +66,7 @@ process_pinmux_config() { EOFQuoted 8 lines
Quoted 7 lines
arch/arm/mach-socfpga/qts-filter.sh +1
-1# Retrieve the pinmux config and zap the ad-hoc length encoding - sed -n '/^unsigned/ !b; :next {/^unsigned/ s/\[.*\]/[]/;p;n;b next}' \ + sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/s/unsigned long/const u8/};p;n;b next}' \${in_dir}/generated/pinmux_config_${soc}.cShould this change be in it's own patch?
Not really, I think you want to change all the places atomically.
Best regards,
Marek Vasut
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U-Boot at lists.denx.de
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PATCH 8/8 arm: socfpga: Make the pinmux table const u8
Quoted 1 line · On Wednesday, August 19, 2015 at 12:14:21 PM, Jian.Luo4 wrote:
Hi Marek,
Hi,
Quoted 8 lines
the last sed line is invalid for my GNU sed 4.2.2. Maybe missed a semicolon?
sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}' \ #
^hereBest regards,
Nice catch, fixed before applying, thanks :)
Best regards,
Marek Vasut
cover arm: socfpga: Board cleanup
In reply to Marek VasutQuoted 4 lines · Marek Vasut
This series cleans up the QTS-generated header files and cleans up the SoCDK support such that they fit into the framework just like any other SoCFPGA boards.
Quoted 9 lines
Marek Vasut (8):
arm: socfpga: Move wrappers into platform directory
arm: socfpga: Unbind CPU type from board type
arm: socfpga: Split Altera socfpga into AV and CV SoCDK
arm: socfpga: Remove CV-specific parts from AV-SoCDK
arm: socfpga: Remove AV-specific parts from CV-SoCDK
arm: socfpga: Addqts-filter.shscript
arm: socfpga: Switch to filtered QTS files
arm: socfpga: Make the pinmux table const u8
Hi Dinh,
could it be that Altera is now filtering me as a spammer, so you're not getting my patches (wouldn't be all that surprising :-) ) ?
Best regards,
Marek Vasut
cover arm: socfpga: Board cleanup
Quoted 15 lines · Marek Vasut
Quoted 4 lines · Marek Vasut
This series cleans up the QTS-generated header files and cleans up the SoCDK support such that they fit into the framework just like any other SoCFPGA boards.
Quoted 9 lines
Marek Vasut (8):
arm: socfpga: Move wrappers into platform directory
arm: socfpga: Unbind CPU type from board type
arm: socfpga: Split Altera socfpga into AV and CV SoCDK
arm: socfpga: Remove CV-specific parts from AV-SoCDK
arm: socfpga: Remove AV-specific parts from CV-SoCDK
arm: socfpga: Addqts-filter.shscript
arm: socfpga: Switch to filtered QTS files
arm: socfpga: Make the pinmux table const u8
Quoted 5 lines
Hi Dinh,
could it be that Altera is now filtering me as a spammer, so you're not getting my patches (wouldn't be all that surprising :-) ) ?
I didn't see these patches because my filter was looking for [U-Boot][PATCH]
Anyways...I see them now...
Dinh
cover arm: socfpga: Board cleanup
Quoted 18 lines · Dinh Nguyen
Quoted 17 lines · Marek Vasut
Quoted 4 lines · Marek Vasut
This series cleans up the QTS-generated header files and cleans up the SoCDK support such that they fit into the framework just like any other SoCFPGA boards.
Quoted 9 lines
Marek Vasut (8):
arm: socfpga: Move wrappers into platform directory
arm: socfpga: Unbind CPU type from board type
arm: socfpga: Split Altera socfpga into AV and CV SoCDK
arm: socfpga: Remove CV-specific parts from AV-SoCDK
arm: socfpga: Remove AV-specific parts from CV-SoCDK
arm: socfpga: Addqts-filter.shscript
arm: socfpga: Switch to filtered QTS files
arm: socfpga: Make the pinmux table const u8Hi Dinh,
Quoted 7 lines
Quoted 2 lines
could it be that Altera is now filtering me as a spammer, so you're not getting my patches (wouldn't be all that surprising :-) ) ?
I didn't see these patches because my filter was looking for [U-Boot][PATCH]
Anyways...I see them now...
Whew, that's a relief :-)
Best regards,
Marek Vasut
cover arm: socfpga: Board cleanup
In reply to Marek VasutQuoted 4 lines · Marek Vasut
This series cleans up the QTS-generated header files and cleans up the SoCDK support such that they fit into the framework just like any other SoCFPGA boards.
Quoted 10 lines
Marek Vasut (8):
arm: socfpga: Move wrappers into platform directory
arm: socfpga: Unbind CPU type from board type
arm: socfpga: Split Altera socfpga into AV and CV SoCDK
arm: socfpga: Remove CV-specific parts from AV-SoCDK
arm: socfpga: Remove AV-specific parts from CV-SoCDK
arm: socfpga: Addqts-filter.shscript
arm: socfpga: Switch to filtered QTS files
arm: socfpga: Make the pinmux table const u8
Only comment was in patch 8/8.
For the series:
Acked-by Dinh Nguyen <[email protected]>
Thanks,
Dinh