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ARM: Add workaround for Cortex-A9 errata 845369

PATCH RESEND New Peng Fan 2 participants 3 messages Aug 31, 2015 Arm (32-bit)

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Peng Fan

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#0 lore raw

PATCH RESEND 1/2 ARM: Add workaround for Cortex-A9 errata 845369

From: Nitin Garg <[email protected]>

Under very rare timing circumstances, transition into streaming mode might create a data corruption. Exists on all Cortex-A9 revisions.

Cc Stefano Babic <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Albert Aribaud <[email protected]>

---

Original patch:
http://lists.denx.de/pipermail/u-boot/2015-April/209724.html

 README                     | 1 +
 arch/arm/cpu/armv7/start.S | 5 +++++
 2 files changed, 6 insertions(+)
README +1 -0
index a52ff46..7da9415 100644
@@ -683,6 +683,7 @@ The following options need to be configured:
 		CONFIG_ARM_ERRATA_751472
 		CONFIG_ARM_ERRATA_794072
 		CONFIG_ARM_ERRATA_761320
+		CONFIG_ARM_ERRATA_845369
 
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the
arch/arm/cpu/armv7/start.S +5 -0
index b180944..0c4fe61 100644
@@ -163,6 +163,11 @@ ENTRY(cpu_init_cp15)
 	orr	r0, r0, #1 << 21	@ set bit #21
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_845369
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 22	@ set bit #22
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
 
 	mov	r5, lr			@ Store my Caller
 	mrc	p15, 0, r1, c0, c0, 0	@ r1 has Read Main ID Register (MIDR)
Signature · 1 line
1.8.4
#1 lore raw

PATCH RESEND 1/2 ARM: Add workaround for Cortex-A9 errata 845369

My bad. Please ignore the two patches 1/2 and 2/2.

Regards,
Peng.

Quoted 52 lines · Peng Fan

From: Nitin Garg <[email protected]>

Under very rare timing circumstances, transition into streaming mode might create a data corruption. Exists on all Cortex-A9 revisions.

Cc Stefano Babic <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Albert Aribaud <[email protected]>

---

Original patch:
http://lists.denx.de/pipermail/u-boot/2015-April/209724.html

README | 1 +
arch/arm/cpu/armv7/start.S | 5 +++++

2 files changed, 6 insertions(+)
README +1 -0
index a52ff46..7da9415 100644
@@ -683,6 +683,7 @@ The following options need to be configured:
 		CONFIG_ARM_ERRATA_751472
 		CONFIG_ARM_ERRATA_794072
 		CONFIG_ARM_ERRATA_761320
+		CONFIG_ARM_ERRATA_845369
 
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the
arch/arm/cpu/armv7/start.S +5 -0
index b180944..0c4fe61 100644
@@ -163,6 +163,11 @@ ENTRY(cpu_init_cp15)
 	orr	r0, r0, #1 << 21	@ set bit #21
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_845369
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 22	@ set bit #22
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
 
 	mov	r5, lr			@ Store my Caller
 	mrc	p15, 0, r1, c0, c0, 0	@ r1 has Read Main ID Register (MIDR)
Signature · 1 line
1.8.4
author
#2 lore raw

PATCH RESEND 2/2 imx: mx6: Enable ARM errata workaround for 845369

In reply to Peng Fan

From: Nitin Garg <[email protected]>

Since MX6 is Cortex-A9 r2p10, enable software workaround for errata 845369.

Cc Stefano Babic <[email protected]>
Cc Fabio Estevam <[email protected]>

---

Original patch:
http://lists.denx.de/pipermail/u-boot/2015-April/209725.html

 include/configs/mx6_common.h | 1 +
 1 file changed, 1 insertion(+)
include/configs/mx6_common.h +1 -0
index ef4cb68..3f1b6b9 100644
@@ -22,6 +22,7 @@
 #define CONFIG_ARM_ERRATA_751472
 #define CONFIG_ARM_ERRATA_794072
 #define CONFIG_ARM_ERRATA_761320
+#define CONFIG_ARM_ERRATA_845369
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
 #define CONFIG_SYS_L2_PL310
Signature · 1 line
1.8.4