Intel Code/Data Prioritization(CDP) feature enabling

Detect Intel Code/Data Prioritization(CDP) feature and store cpuid information for later use. CDP feature is based on CAT, note that all sockets in the platform must have CDP either enabled or disabled, not a mix. cdp_socket_avail saves CDP capability of every socket so that we can determine if CDP is supported in the platform.

Signed-off-by He Chen <[email protected]>

---
 xen/arch/x86/psr.c        | 13 ++++++++++++-
 xen/include/asm-x86/psr.h |  4 ++++
 2 files changed, 16 insertions(+), 1 deletion(-)

xen/arch/x86/psr.c +1 -0

index c0daa2e..b357816 100644
@@ -43,6 +43,7 @@ struct psr_cmt *__read_mostly psr_cmt;
 
 static unsigned long *__read_mostly cat_socket_enable;
 static struct psr_cat_socket_info *__read_mostly cat_socket_info;
+static unsigned long *__read_mostly cdp_socket_avail;
 
 static unsigned int __initdata opt_psr;
 static unsigned int __initdata opt_rmid_max = 255;

xen/arch/x86/psr.c +4 -1

 }
 
 static void cat_cpu_fini(unsigned int cpu)

@@ -523,6 +531,8 @@ static void __init psr_cat_free(void)
     cat_socket_enable = NULL;
     xfree(cat_socket_info);
     cat_socket_info = NULL;
+    xfree(cdp_socket_avail);
+    cdp_socket_avail = NULL;
 }
 
 static void __init init_psr_cat(void)

@@ -535,8 +545,9 @@ static void __init init_psr_cat(void)
 
     cat_socket_enable = xzalloc_array(unsigned long, BITS_TO_LONGS(nr_sockets));
     cat_socket_info = xzalloc_array(struct psr_cat_socket_info, nr_sockets);
+    cdp_socket_avail = xzalloc_array(unsigned long, BITS_TO_LONGS(nr_sockets));
 
-    if ( !cat_socket_enable || !cat_socket_info )
+    if ( !cat_socket_enable || !cat_socket_info || !cdp_socket_avail )
         psr_cat_free();
 }
 

xen/include/asm-x86/psr.h +0 -0

index 081750f..a6b83df 100644

cdp_enabled is added to CAT socket info to indicate CDP is on or off on the socket and struct psr_cat_cbm is extended to support CDP operation. IA32_L3_QOS_CFG is a new MSR to enable/disable L3 CDP, when enable or disable CDP, all domains will reset to COS0 with fully access all L3 cache.

Signed-off-by He Chen <[email protected]>

---
 xen/arch/x86/psr.c          | 164 ++++++++++++++++++++++++++++++++++++++++----
 xen/arch/x86/sysctl.c       |   9 ++-
 xen/include/asm-x86/psr.h   |  10 ++-
 xen/include/public/sysctl.h |   5 ++
 4 files changed, 174 insertions(+), 14 deletions(-)

xen/arch/x86/psr.c +1 -0

index b357816..26596dd 100644
@@ -17,13 +17,20 @@
 #include <xen/cpu.h>
 #include <xen/err.h>
 #include <xen/sched.h>
+#include <xen/domain.h>
 #include <asm/psr.h>
 
 #define PSR_CMT        (1<<0)
 #define PSR_CAT        (1<<1)

xen/arch/x86/psr.c +1 -0

     unsigned int ref;
 };
 

@@ -32,6 +39,7 @@ struct psr_cat_socket_info {
     unsigned int cos_max;
     struct psr_cat_cbm *cos_to_cbm;
     spinlock_t cbm_lock;
+    bool_t cdp_enabled;
 };
 
 struct psr_assoc {

xen/arch/x86/psr.c +1 -1

     return 0;
 }

@@ -283,7 +292,7 @@ int psr_get_l3_cbm(struct domain *d, unsigned int socket, uint64_t *cbm)
     if ( IS_ERR(info) )
         return PTR_ERR(info);
 
-    *cbm = info->cos_to_cbm[d->arch.psr_cos_ids[socket]].cbm;
+    *cbm = info->cos_to_cbm[d->arch.psr_cos_ids[socket]].u.cbm;
 
     return 0;
 }

xen/arch/x86/psr.c +40 -5

+      .cbm_code = cbm_code,
+      .cbm_data = cbm_data,
+      .cdp_mode = cdp_mode,
+    };
 
     if ( socket == cpu_to_socket(smp_processor_id()) )
         do_write_l3_cbm(&info);

@@ -364,7 +387,7 @@ int psr_set_l3_cbm(struct domain *d, unsigned int socket, uint64_t cbm)
         /* If still not found, then keep unused one. */
         if ( !found && cos != 0 && map[cos].ref == 0 )
             found = map + cos;
-        else if ( map[cos].cbm == cbm )
+        else if ( map[cos].u.cbm == cbm )
         {
             if ( unlikely(cos == old_cos) )
             {

@@ -388,16 +411,16 @@ int psr_set_l3_cbm(struct domain *d, unsigned int socket, uint64_t cbm)
     }
 
     cos = found - map;
-    if ( found->cbm != cbm )
+    if ( found->u.cbm != cbm )
     {
-        int ret = write_l3_cbm(socket, cos, cbm);
+        int ret = write_l3_cbm(socket, cos, cbm, 0, 0);
 
         if ( ret )
         {
             spin_unlock(&info->cbm_lock);
             return ret;
         }
-        found->cbm = cbm;
+        found->u.cbm = cbm;
     }
 
     found->ref++;

@@ -491,7 +514,7 @@ static void cat_cpu_init(void)
         info->cos_to_cbm = temp_cos_to_cbm;
         temp_cos_to_cbm = NULL;
         /* cos=0 is reserved as default cbm(all ones). */
-        info->cos_to_cbm[0].cbm = (1ull << info->cbm_len) - 1;
+        info->cos_to_cbm[0].u.cbm = (1ull << info->cbm_len) - 1;
 
         spin_lock_init(&info->cbm_lock);
 

@@ -556,6 +579,123 @@ static int psr_cpu_prepare(unsigned int cpu)
     return cat_cpu_prepare(cpu);
 }
 
+static void do_write_l3_config(void *data)
+{
+    uint64_t val;
+    uint64_t *mask = data;
+
+    rdmsrl(PSR_L3_QOS_CFG, val);
+    wrmsrl(PSR_L3_QOS_CFG, val | *mask);
+}
+
+static int config_socket_l3_cdp(unsigned int socket, uint64_t cdp_mask)
+{
+    unsigned int cpu;
+    uint64_t mask = cdp_mask;
+
+    if ( socket == cpu_to_socket(smp_processor_id()) )
+        do_write_l3_config(&mask);
+    else
+    {
+        cpu = get_socket_cpu(socket);
+        if ( cpu >= nr_cpu_ids )
+            return -ENOTSOCK;
+        on_selected_cpus(cpumask_of(cpu), do_write_l3_config, &mask, 1);
+    }
+    return 0;
+}
+
+int psr_cat_enable_cdp(void)
+{
+    int i, ret;
+    struct psr_cat_socket_info *info;
+    unsigned int socket;

xen/arch/x86/psr.c +17 -0

+            return 0;
+
+        /* Cut half of cos_max when CDP enabled */
+        info->cos_max = info->cos_max / 2;
+
+        spin_lock(&info->cbm_lock);
+
+        /* Reset COS0 code CBM & data CBM for all domain */
+        info->cos_to_cbm[0].u.cdp.code = (1ull << info->cbm_len) - 1;
+        info->cos_to_cbm[0].u.cdp.data = (1ull << info->cbm_len) - 1;
+
+        for ( i = 0; i <= info->cos_max; i++ )
+            info->cos_to_cbm[0].ref = 0;
+
+        /* Only write mask1 since mask0 is always all 1 by CAT. */
+        ret = write_l3_cbm(socket, 1, info->cos_to_cbm[0].u.cdp.code, 0, 0);
+        if ( ret )

xen/arch/x86/psr.c +49 -0

+        }
+
+        spin_unlock(&info->cbm_lock);
+        info->cdp_enabled = 1;
+    }
+
+    return 0;
+}
+
+int psr_cat_disable_cdp(void)
+{
+    int i, ret;
+    struct psr_cat_socket_info *info;
+    unsigned int socket;
+    struct domain *d;
+
+    for_each_set_bit(socket, cat_socket_enable, nr_sockets)
+    {
+        ret = config_socket_l3_cdp(socket, 0 << PSR_L3_QOS_CDP_ENABLE_BIT);
+        if ( ret )
+            return ret;
+
+        info = cat_socket_info + socket;
+        if( !info->cdp_enabled )
+            return 0;
+
+        /* Restore CAT cos_max when CDP disabled */
+        info->cos_max = info->cos_max * 2 + 1;
+        spin_lock(&info->cbm_lock);
+
+        /* Reset all CBMs and set fully open COS0 for all domains */
+        info->cos_to_cbm[0].u.cbm = (1ull << info->cbm_len) - 1;
+        for ( i = 0; i <= info->cos_max; i++ )
+            info->cos_to_cbm[i].ref = 0;
+
+        /* Reset all domains to COS0 */
+        for_each_domain( d )
+        {
+            d->arch.psr_cos_ids[socket] = 0;
+            info->cos_to_cbm[0].ref++;
+        }
+
+        spin_unlock(&info->cbm_lock);
+        info->cdp_enabled = 0;
+    }
+
+    return 0;
+}
+
 static void psr_cpu_init(void)
 {
     if ( cat_socket_info )

xen/arch/x86/sysctl.c +2 -1

index f36b52f..51b03a4 100644
@@ -177,12 +177,19 @@ long arch_do_sysctl(
         case XEN_SYSCTL_PSR_CAT_get_l3_info:
             ret = psr_get_cat_l3_info(sysctl->u.psr_cat_op.target,
                                       &sysctl->u.psr_cat_op.u.l3_info.cbm_len,
-                                      &sysctl->u.psr_cat_op.u.l3_info.cos_max);
+                                      &sysctl->u.psr_cat_op.u.l3_info.cos_max,
+                                      &sysctl->u.psr_cat_op.u.l3_info.cdp_enabled);
 

xen/arch/x86/sysctl.c +0 -0

         default:
             ret = -EOPNOTSUPP;
             break;

xen/include/asm-x86/psr.h +9 -1

index a6b83df..2b79a92 100644
@@ -30,6 +30,11 @@
 /* CDP Capability */
 #define PSR_CAT_CDP_CAPABILITY       0x4
 
+/* L3 QoS Config MSR Address */
+#define PSR_L3_QOS_CFG           0xc81
+
+/* L3 CDP Enable bit*/
+#define PSR_L3_QOS_CDP_ENABLE_BIT       0x0
 
 struct psr_cmt_l3 {
     unsigned int features;

@@ -56,13 +61,16 @@ void psr_free_rmid(struct domain *d);
 void psr_ctxt_switch_to(struct domain *d);
 
 int psr_get_cat_l3_info(unsigned int socket, uint32_t *cbm_len,
-                        uint32_t *cos_max);
+                        uint32_t *cos_max, uint8_t *cdp_enabled);
 int psr_get_l3_cbm(struct domain *d, unsigned int socket, uint64_t *cbm);
 int psr_set_l3_cbm(struct domain *d, unsigned int socket, uint64_t cbm);
 
 int psr_domain_init(struct domain *d);
 void psr_domain_free(struct domain *d);
 
+int psr_cat_enable_cdp(void);
+int psr_cat_disable_cdp(void);
+
 #endif /* __ASM_PSR_H__ */
 
 /*

xen/include/public/sysctl.h +2 -0

index 58c9be2..8b97137 100644
@@ -697,6 +697,8 @@ typedef struct xen_sysctl_pcitopoinfo xen_sysctl_pcitopoinfo_t;
 DEFINE_XEN_GUEST_HANDLE(xen_sysctl_pcitopoinfo_t);
 
 #define XEN_SYSCTL_PSR_CAT_get_l3_info               0
+#define XEN_SYSCTL_PSR_CAT_enable_cdp                1
+#define XEN_SYSCTL_PSR_CAT_disable_cdp               2
 struct xen_sysctl_psr_cat_op {
     uint32_t cmd;       /* IN: XEN_SYSCTL_PSR_CAT_* */
     uint32_t target;    /* IN */

Quoted 1 line

Quoted 1 line · On 02.09.15 at 13:39, <[email protected]> wrote:

xen/arch/x86/psr.c static int psr_cpu_prepare(unsigned int cpu) · line 649

Quoted 5 lines · He Chen

xen/arch/x86/psr.c +5 -0

+        /* Reset all domain to COS0 */
+        for_each_domain( d )
+        {
+            d->arch.psr_cos_ids[socket] = 0;
+            info->cos_to_cbm[0].ref++;

This is a long running operation and must not be done synchronously like this. Unfortunately, it is not easy to make restartable.

I think it would be perfectly reasonable to have cdp as a boot time switch only, and have no ability to change it at runtime. I don't see a reasonable case to change it dynamically at runtime; users will either want to use it, or not.

Making this a boot-time choice (i.e. psr=cat,cdp) removes all of this re-juggling logic, and simplifies things greatly.

Thoughts?

CDP extends CAT and provides the capacity to control L3 code & data cache. With CDP, one COS correspond to two CMBs(code & data). cbm_type is added to support distinguish different CBM operation. Besides, new domctl cmds are introdunced to support set/get CDP CBM. Some CAT functions to operation CBMs are extended to support CDP.

Signed-off-by He Chen <[email protected]>

---
 xen/arch/x86/domctl.c       |  33 +++++++++-
 xen/arch/x86/psr.c          | 142 ++++++++++++++++++++++++++++++++------------
 xen/include/asm-x86/psr.h   |  12 +++-
 xen/include/public/domctl.h |   4 ++
 4 files changed, 150 insertions(+), 41 deletions(-)

xen/arch/x86/domctl.c +31 -2

index bf62a88..c2d771e 100644
@@ -1167,12 +1167,41 @@ long arch_do_domctl(
         {
         case XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM:
             ret = psr_set_l3_cbm(d, domctl->u.psr_cat_op.target,
-                                 domctl->u.psr_cat_op.data);
+                                 domctl->u.psr_cat_op.data,
+                                 PSR_CBM_TYPE_L3);
             break;
 
+        case XEN_DOMCTL_PSR_CAT_OP_SET_L3_CODE:
+            ret = psr_set_l3_cbm(d, domctl->u.psr_cat_op.target,
+                                 domctl->u.psr_cat_op.data,
+                                 PSR_CBM_TYPE_L3_CODE);
+            break;
+
+        case XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA:
+            ret = psr_set_l3_cbm(d, domctl->u.psr_cat_op.target,
+                                 domctl->u.psr_cat_op.data,
+                                 PSR_CBM_TYPE_L3_DATA);
+            break;
+
+
         case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM:
             ret = psr_get_l3_cbm(d, domctl->u.psr_cat_op.target,
-                                 &domctl->u.psr_cat_op.data);
+                                 &domctl->u.psr_cat_op.data,
+                                 PSR_CBM_TYPE_L3);
+            copyback = 1;
+            break;
+
+        case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE:
+            ret = psr_get_l3_cbm(d, domctl->u.psr_cat_op.target,
+                                 &domctl->u.psr_cat_op.data,
+                                 PSR_CBM_TYPE_L3_CODE);
+            copyback = 1;
+            break;
+
+        case XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA:
+            ret = psr_get_l3_cbm(d, domctl->u.psr_cat_op.target,
+                                 &domctl->u.psr_cat_op.data,
+                                 PSR_CBM_TYPE_L3_DATA);
             copyback = 1;
             break;
 

xen/arch/x86/psr.c +2 -1

index 26596dd..8e92d24 100644
@@ -285,14 +285,20 @@ int psr_get_cat_l3_info(unsigned int socket, uint32_t *cbm_len,
     return 0;
 }
 
-int psr_get_l3_cbm(struct domain *d, unsigned int socket, uint64_t *cbm)
+int psr_get_l3_cbm(struct domain *d, unsigned int socket,
+                   uint64_t *cbm, enum cbm_type type)
 {
     struct psr_cat_socket_info *info = get_cat_socket_info(socket);
 
     if ( IS_ERR(info) )

xen/arch/x86/psr.c +22 -0

+
+    if ( !cdp_enabled )
+    {
+        for ( cos = 0; cos <= cos_max; cos++ )
+            if ( map[cos].ref && map[cos].u.cbm == cbm_code )
+                return cos;
+    }
+    else
+    {
+        for ( cos = 0; cos <= cos_max; cos++ )
+            if ( map[cos].ref && map[cos].u.cdp.code == cbm_code &&
+                 map[cos].u.cdp.data == cbm_data )
+                return cos;
+    }
+
+    return -ENOENT;
+}
+
+static int pick_avail_cos(struct psr_cat_cbm *map, int cos_max, int old_cos)
+{
+    int cos;
+

xen/arch/x86/psr.c +3 -0

+    uint64_t cbm_data, cbm_code;
+    struct psr_cat_cbm *map;
     struct psr_cat_socket_info *info = get_cat_socket_info(socket);
 
     if ( IS_ERR(info) )

@@ -377,53 +424,74 @@ int psr_set_l3_cbm(struct domain *d, unsigned int socket, uint64_t cbm)
     if ( !psr_check_cbm(info->cbm_len, cbm) )
         return -EINVAL;
 
+    cos_max = info->cos_max;

xen/arch/x86/psr.c +0 -3

     {
-        /* If still not found, then keep unused one. */
-        if ( !found && cos != 0 && map[cos].ref == 0 )
-            found = map + cos;

xen/arch/x86/psr.c +19 -10

+        case PSR_CBM_TYPE_L3_CODE:
+            cbm_code = cbm;
+            cbm_data = map[old_cos].u.cdp.data;
+            break;
+        case PSR_CBM_TYPE_L3_DATA:
+            cbm_code = map[old_cos].u.cdp.code;
+            cbm_data = cbm;
+            break;
+        default:
+            return -EINVAL;
     }
 
-    /* If old cos is referred only by the domain, then use it. */
-    if ( !found && map[old_cos].ref == 1 )
-        found = map + old_cos;
-
-    if ( !found )
+    spin_lock(&info->cbm_lock);
+    cos = exist_same_cos(map, cos_max, cbm_code, cbm_data, info->cdp_enabled);
+    if ( cos >= 0 )
     {
-        spin_unlock(&info->cbm_lock);
-        return -EOVERFLOW;
+        if ( unlikely(cos == old_cos) )
+        {
+            spin_unlock(&info->cbm_lock);
+            return 0;
+        }
     }
-
-    cos = found - map;
-    if ( found->u.cbm != cbm )
+    else

xen/arch/x86/psr.c +23 -2

+        }
+
+        /* We try to avoid writing MSR */
+        if ( info->cdp_enabled )
+        {
+            if ( map[cos].u.cdp.code == cbm_code &&
+                 map[cos].u.cdp.data == cbm_data )
+                need_write = 0;
+        }
+        else
+            need_write = map[cos].u.cbm == cbm_code ? 0 : 1;
+
+        if ( need_write )
+        {
+            ret = write_l3_cbm(socket, cos, cbm_code, cbm_data, info->cdp_enabled);
+            if ( ret )
+            {
+                spin_unlock(&info->cbm_lock);
+                return ret;
+            }
+            map[cos].u.cdp.code = cbm_code;
+            map[cos].u.cdp.data = cbm_data;
         }
-        found->u.cbm = cbm;
     }
 
-    found->ref++;
+    map[cos].ref++;
     map[old_cos].ref--;
     spin_unlock(&info->cbm_lock);
 

xen/include/asm-x86/psr.h +10 -2

index 2b79a92..3af4ac2 100644
@@ -49,6 +49,12 @@ struct psr_cmt {
     struct psr_cmt_l3 l3;
 };
 
+enum cbm_type {
+    PSR_CBM_TYPE_L3         = 1,
+    PSR_CBM_TYPE_L3_CODE    = 2,
+    PSR_CBM_TYPE_L3_DATA    = 3,
+};
+
 extern struct psr_cmt *psr_cmt;
 
 static inline bool_t psr_cmt_enabled(void)

@@ -62,8 +68,10 @@ void psr_ctxt_switch_to(struct domain *d);
 
 int psr_get_cat_l3_info(unsigned int socket, uint32_t *cbm_len,
                         uint32_t *cos_max, uint8_t *cdp_enabled);
-int psr_get_l3_cbm(struct domain *d, unsigned int socket, uint64_t *cbm);
-int psr_set_l3_cbm(struct domain *d, unsigned int socket, uint64_t cbm);
+int psr_get_l3_cbm(struct domain *d, unsigned int socket,
+                   uint64_t *cbm, enum cbm_type type);
+int psr_set_l3_cbm(struct domain *d, unsigned int socket,
+                   uint64_t cbm, enum cbm_type type);
 
 int psr_domain_init(struct domain *d);
 void psr_domain_free(struct domain *d);

xen/include/public/domctl.h +4 -0

index 675f021..f438cae 100644
@@ -1056,6 +1056,10 @@ DEFINE_XEN_GUEST_HANDLE(xen_domctl_monitor_op_t);
 struct xen_domctl_psr_cat_op {
 #define XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM     0
 #define XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM     1
+#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_CODE    2
+#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA    3
+#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE    4
+#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA    5
     uint32_t cmd;       /* IN: XEN_DOMCTL_PSR_CAT_OP_* */
     uint32_t target;    /* IN */
     uint64_t data;      /* IN/OUT */

Quoted 26 lines · He Chen

CDP extends CAT and provides the capacity to control L3 code & data cache. With CDP, one COS correspond to two CMBs(code & data). cbm_type is added to support distinguish different CBM operation. Besides, new domctl cmds are introdunced to support set/get CDP CBM. Some CAT functions to operation CBMs are extended to support CDP.

Signed-off-by He Chen <[email protected]>

---
 xen/arch/x86/domctl.c       |  33 +++++++++-
 xen/arch/x86/psr.c          | 142 ++++++++++++++++++++++++++++++++------------
 xen/include/asm-x86/psr.h   |  12 +++-
 xen/include/public/domctl.h |   4 ++
 4 files changed, 150 insertions(+), 41 deletions(-)

xen/arch/x86/psr.c +8 -0

index 26596dd..8e92d24 100644
+static int pick_avail_cos(struct psr_cat_cbm *map, int cos_max, int old_cos)
+{
+    int cos;
+
+    /* If old cos is referred only by the domain, then use it. */
+    if ( map[old_cos].ref == 1 )
+        return old_cos;
+

xen/arch/x86/psr.c static int write_l3_cbm(unsigned int socket, unsigned int cos, · line 409

Quoted 6 lines

xen/arch/x86/psr.c +6 -0

+    /* Then we pick an unused one, never pick 0 */
+    for ( cos = 1; cos <= cos_max; cos++ )
+        if ( map[cos].ref == 0 )
+            return cos;
+
+    return -EOVERFLOW;

ENOENT surely, or use EOVERFLOW consistently.

Quoted 26 lines · Andrew Cooper

Quoted 25 lines · He Chen

CDP extends CAT and provides the capacity to control L3 code & data cache. With CDP, one COS correspond to two CMBs(code & data). cbm_type is added to support distinguish different CBM operation. Besides, new domctl cmds are introdunced to support set/get CDP CBM. Some CAT functions to operation CBMs are extended to support CDP.

Signed-off-by He Chen <[email protected]>

---
  xen/arch/x86/domctl.c       |  33 +++++++++-
  xen/arch/x86/psr.c          | 142 ++++++++++++++++++++++++++++++++------------
  xen/include/asm-x86/psr.h   |  12 +++-
  xen/include/public/domctl.h |   4 ++
  4 files changed, 150 insertions(+), 41 deletions(-)

xen/arch/x86/psr.c +7 -0

index 26596dd..8e92d24 100644
+static int pick_avail_cos(struct psr_cat_cbm *map, int cos_max, int old_cos)
+{
+    int cos;
+
+    /* If old cos is referred only by the domain, then use it. */
+    if ( map[old_cos].ref == 1 )
+        return old_cos;

Quoted 9 lines

xen/arch/x86/psr.c static int write_l3_cbm(unsigned int socket, unsigned int cos, · line 409

Quoted 7 lines

xen/arch/x86/psr.c +7 -0

+
+    /* Then we pick an unused one, never pick 0 */
+    for ( cos = 1; cos <= cos_max; cos++ )
+        if ( map[cos].ref == 0 )
+            return cos;
+
+    return -EOVERFLOW;

ENOENT surely, or use EOVERFLOW consistently.

I am not sure I got your point here. pick_avail_cos is to get an unused COS, if succeed, it returns a positive number which means COS, but when fail, it should return a negative number to indicate an error.

As far as I know, ENOENT is 2 and EOVERFLOW is 75, if I return ENOENT directly, the function which call pick_avail_cos could not tell the value is a valid COS or an error number.

Would you mind explaining in more detail for me and thanks.

This is the xc/xl changes to support Intel Code/Data Prioritization. Two new xl commands are introduced to enable/disable CDP dynamically, and CAT xl commands to set/get CBMs are extended to support CDP.

Signed-off-by He Chen <[email protected]>

---
 tools/libxc/include/xenctrl.h | 10 ++++--
 tools/libxc/xc_psr.c          | 42 +++++++++++++++++++++-
 tools/libxl/libxl.h           | 12 +++++++
 tools/libxl/libxl_psr.c       | 64 +++++++++++++++++++++++++++++++++-
 tools/libxl/libxl_types.idl   |  3 ++
 tools/libxl/xl.h              |  4 +++
 tools/libxl/xl_cmdimpl.c      | 81 +++++++++++++++++++++++++++++++++++++------
 tools/libxl/xl_cmdtable.c     | 15 ++++++++
 8 files changed, 217 insertions(+), 14 deletions(-)

tools/libxc/include/xenctrl.h +0 -0

index de3c0ad..665e6bd 100644

tools/libxc/include/xenctrl.h +2 -0

+int xc_psr_cat_enable_cdp(xc_interface *xch);
+int xc_psr_cat_disable_cdp(xc_interface *xch);
 #endif
 
 #endif /* XENCTRL_H */

tools/libxc/xc_psr.c +12 -0

index d8b3a51..d4ff6f6 100644
@@ -260,6 +260,12 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
     case XC_PSR_CAT_L3_CBM:
         cmd = XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM;
         break;
+    case XC_PSR_CAT_L3_CODE:
+        cmd = XEN_DOMCTL_PSR_CAT_OP_SET_L3_CODE;
+        break;
+    case XC_PSR_CAT_L3_DATA:
+        cmd = XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA;
+        break;
     default:
         errno = EINVAL;
         return -1;

@@ -287,6 +293,12 @@ int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
     case XC_PSR_CAT_L3_CBM:
         cmd = XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM;
         break;
+    case XC_PSR_CAT_L3_CODE:
+        cmd = XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE;
+        break;
+    case XC_PSR_CAT_L3_DATA:
+        cmd = XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA;
+        break;
     default:
         errno = EINVAL;
         return -1;

@@ -306,7 +318,8 @@ int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
 }
 

tools/libxc/xc_psr.c +1 -1

@@ -352,7 +369,7 @@ int libxl_psr_cat_get_l3_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
 
     for (i = 0; i < nr_sockets; i++) {
         if (xc_psr_cat_get_l3_info(ctx->xch, i, &ptr[i].cos_max,
-                                                &ptr[i].cbm_len)) {
+                                   &ptr[i].cbm_len, &ptr[i].cdp_enabled)) {
             libxl__psr_cat_log_err_msg(gc, errno);
             rc = ERROR_FAIL;
             free(ptr);

@@ -376,6 +393,51 @@ void libxl_psr_cat_info_list_free(libxl_psr_cat_info *list, int nr)
     free(list);
 }
 

tools/libxl/xl.h +4 -0

index 13bccba..e8bb774 100644
@@ -121,6 +121,10 @@ int main_psr_cmt_show(int argc, char **argv);
 int main_psr_cat_cbm_set(int argc, char **argv);
 int main_psr_cat_show(int argc, char **argv);
 #endif
+#ifdef LIBXL_HAVE_PSR_CDP
+int main_psr_cat_cdp_enable(int argc, char **argv);
+int main_psr_cat_cdp_disable(int argc, char **argv);
+#endif
 
 void help(const char *command);
 

tools/libxl/xl_cmdimpl.c +0 -0

index ebbb9a5..825d707 100644
@@ -8366,6 +8366,15 @@ int main_psr_cmt_show(int argc, char **argv)
 #endif
 

tools/libxl/xl_cmdimpl.c +1 -0

 static int psr_cat_hwinfo(void)
 {
     int rc;

@@ -8390,6 +8399,7 @@ static int psr_cat_hwinfo(void)
         }
         printf("%-16s: %u\n", "Socket ID", socketid);
         printf("%-16s: %uKB\n", "L3 Cache", l3_cache_size);
+        psr_cat_print_cdp_status(info->cdp_enabled);
         printf("%-16s: %u\n", "Maximum COS", info->cos_max);
         printf("%-16s: %u\n", "CBM length", info->cbm_len);
         printf("%-16s: %#llx\n", "Default CBM",

@@ -8401,7 +8411,8 @@ out:
     return rc;
 }
 

docs/misc/xl-psr.markdown +10 -0

+Code/Data Prioritization (CDP) Technology is an extension of CAT, which is
+available on Intel Broadwell and later server platforms. CDP enables isolation
+and separate prioritization of code and data fetches to the L3 cache in a
+software configurable manner, which can enable workload prioritization and
+tuning of cache capacity to the characteristics of the workload. CDP extends
+Cache Allocation Technology (CAT) by providing separate code and data masks
+per Class of Service (COS).
+
+CDP is disabled on the processor by default. If the CAT MSRs are used without
+enabling CDP, the processor operates in a traditional CAT-only mode.

Hi all,

Code/Data Prioritization(CDP) is offered in Intel Broadwell and later server platforms, which is an extension of CAT. CDP enables isolation and separate prioritization of code and data fetches to the L3 cache in a software configurable manner, which can enable workload prioritization and tuning of cache capacity to the characteristics of the workload. CDP extends Cache Allocation Technology (CAT) by providing separate code and data capacity bit masks(CBM) per Class of Service (COS). CDP is used on VM basis in the Xen implementation.

More information about CDP, please refer to Intel SDM, Volumn 3, section 17.16
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf

This patch series enables CDP feature in Xen based on CAT code, including extending CBM operation functions and introducing new commands to enable/disable CDP dynamically. For all the changes, please see in each patch.

This patchset has been tested on Intel Broadwell server platform.

To make this patchset better, any comment or suggestion is welcomed, I would really appreciate it.

Quoted 14 lines · He Chen

Hi all,

Code/Data Prioritization(CDP) is offered in Intel Broadwell and later server platforms, which is an extension of CAT. CDP enables isolation and separate prioritization of code and data fetches to the L3 cache in a software configurable manner, which can enable workload prioritization and tuning of cache capacity to the characteristics of the workload. CDP extends Cache Allocation Technology (CAT) by providing separate code and data capacity bit masks(CBM) per Class of Service (COS). CDP is used on VM basis in the Xen implementation.

More information about CDP, please refer to Intel SDM, Volumn 3, section 17.16
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf

Quoted 8 lines

This patch series enables CDP feature in Xen based on CAT code, including extending CBM operation functions and introducing new commands to enable/disable CDP dynamically. For all the changes, please see in each patch.

This patchset has been tested on Intel Broadwell server platform.

To make this patchset better, any comment or suggestion is welcomed, I would really appreciate it.

I have taken a look at patches 1-3. For the most part, it looks good.

The main point I have is on patch 2, as to whether it is sensible to permit enabling/disabling cdp at runtime. I suggest that it is not sensible, and should be a command line parameter instead.

If this is agreed as ok going forwards, patches 3 through 5 should become rather more simple.

Quoted 14 lines · He Chen

Hi all,

Code/Data Prioritization(CDP) is offered in Intel Broadwell and later server platforms, which is an extension of CAT. CDP enables isolation and separate prioritization of code and data fetches to the L3 cache in a software configurable manner, which can enable workload prioritization and tuning of cache capacity to the characteristics of the workload. CDP extends Cache Allocation Technology (CAT) by providing separate code and data capacity bit masks(CBM) per Class of Service (COS). CDP is used on VM basis in the Xen implementation.

More information about CDP, please refer to Intel SDM, Volumn 3, section 17.16
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf

Quoted 8 lines

This patch series enables CDP feature in Xen based on CAT code, including extending CBM operation functions and introducing new commands to enable/disable CDP dynamically. For all the changes, please see in each patch.

This patchset has been tested on Intel Broadwell server platform.

To make this patchset better, any comment or suggestion is welcomed, I would really appreciate it.

I have taken a look at patches 1-3. For the most part, it looks good.

The main point I have is on patch 2, as to whether it is sensible to permit enabling/disabling cdp at runtime. I suggest that it is not sensible, and should be a command line parameter instead.

If this is agreed as ok going forwards, patches 3 through 5 should become rather more simple.

~Andrew