Renesas R-Car Gen3 CPG support V7

Renesas R-Car Gen3 CPG support V7

[PATCH v7 01/05] clk: shmobile: Rework CONFIG_ARCH_SHMOBILE_MULTI [PATCH v7 02/05] clk: shmobile: Add r8a7795 SoC to MSTP bindings [PATCH v7 03/05] clk: shmobile: Make MSTP clock-output-names optional [PATCH v7 04/05] clk: shmobile: Add Renesas R-Car Gen3 CPG support [PATCH v7 05/05] clk: shmobile: rcar-gen3: Add CPG/MSTP Clock Domain support

Here's the latest R-Car Gen3 clock support patch collection through a single "easy to use" patch series for drivers/clk and DT documentation bits. This version of the series only updates patch 4 with PLL1 divider removal changes as well as some clock registration rework.

For details please see each individual patch.

---

Developed against e2a147e in renesas-drivers with reverted V6 series

 Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt      |    1 
 Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt |   58 ++
 drivers/clk/Makefile                                                     |    1 
 drivers/clk/shmobile/Makefile                                            |   23 
 drivers/clk/shmobile/clk-mstp.c                                          |   24 
 drivers/clk/shmobile/clk-rcar-gen3.c                                     |  244 ++++++++++
 6 files changed, 328 insertions(+), 23 deletions(-)

From: Magnus Damm <[email protected]>

Shmobile is all multiplatform these days, so in get rid of the reference to CONFIG_ARCH_SHMOBILE_MULTI in drivers/clk/shmobile/.

Also instead of always enabling DIV6 and MSTP adjust the Makefile to enable DIV6 and MSTP depending on if they are included in the SoC or not.

---

Earlier known as "clk: shmobile: Get rid of CONFIG_ARCH_SHMOBILE_MULTI"

Changes since V6:
- None

Changes since V5:
- None

Changes since V4:
- Added Acked-by from Laurent

Changes since V3:
- Got rid of hunks that modified drivers/clk/Makefile
- This to prevent build issue with non-CCF enabled SH arch
- A nice side effect is that this patch now can be merged any time

Changes since V2:
- Fixed patch subject typo CONFIG_SHMOBILE_MULTI -> CONFIG_ARCH_SHMOBILE_MULTI

Changes since V1:
- Added Acked-by from Geert

 drivers/clk/shmobile/Makefile |   22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

@@ -1,13 +1,11 @@
 obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
-obj-$(CONFIG_ARCH_R7S72100)		+= clk-rz.o
-obj-$(CONFIG_ARCH_R8A73A4)		+= clk-r8a73a4.o
-obj-$(CONFIG_ARCH_R8A7740)		+= clk-r8a7740.o
-obj-$(CONFIG_ARCH_R8A7778)		+= clk-r8a7778.o
-obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
-obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
-obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
-obj-$(CONFIG_ARCH_R8A7793)		+= clk-rcar-gen2.o
-obj-$(CONFIG_ARCH_R8A7794)		+= clk-rcar-gen2.o
-obj-$(CONFIG_ARCH_SH73A0)		+= clk-sh73a0.o
-obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
-obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-mstp.o
+obj-$(CONFIG_ARCH_R7S72100)		+= clk-rz.o clk-mstp.o
+obj-$(CONFIG_ARCH_R8A73A4)		+= clk-r8a73a4.o clk-mstp.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7740)		+= clk-r8a7740.o clk-mstp.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7778)		+= clk-r8a7778.o clk-mstp.o
+obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o clk-mstp.o
+obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o clk-mstp.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o clk-mstp.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7793)		+= clk-rcar-gen2.o clk-mstp.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7794)		+= clk-rcar-gen2.o clk-mstp.o clk-div6.o
+obj-$(CONFIG_ARCH_SH73A0)		+= clk-sh73a0.o clk-mstp.o clk-div6.o

From: Kuninori Morimoto <[email protected]>

Add r8a7795 to the MSTP DT binding documentation.

---

Changes since V6: (Magnus Damm <[email protected]>)
- None

Changes since V5: (Magnus Damm <[email protected]>)
- Added Acked-by from Laurent

Changes since V4: (Magnus Damm <[email protected]>)
- Added Acked-by from Geert

Changes since V3: (Magnus Damm <[email protected]>)
- Picked up patch floating around on ML, added change log

 Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt |    1 +
 1 file changed, 1 insertion(+)

@@ -19,6 +19,7 @@ Required Properties:
     - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
     - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
     - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
+    - "renesas,r8a7795-mstp-clocks" for R8A7795 (R-Car H3) MSTP gate clocks
     - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
     and "renesas,cpg-mstp-clocks" as a fallback.
   - reg: Base address and length of the I/O mapped registers used by the MSTP

From: Magnus Damm <[email protected]>

This patch updates the MSTP driver to make the "clock-output-names" DT property optional instead of mandatory. In case the DT property is omitted then the function clk_register_clkdev() is skipped.

The default for new SoCs is to not use "clock-output-names".

---

Changes since V6:
- None

Changes since V5:
- Simplified code using const char *allocated_name - thanks Geert!

Changes since V4:
- None

Changes since V3:
- Added support for multiple MSTP bits. =)

 drivers/clk/shmobile/clk-mstp.c |   24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

@@ -193,26 +193,26 @@ static void __init cpg_mstp_clocks_init(
 	for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
 		const char *parent_name;
 		const char *name;
+		const char *allocated_name = NULL;
 		u32 clkidx;
 		int ret;
 
-		/* Skip clocks with no name. */
-		ret = of_property_read_string_index(np, "clock-output-names",
-						    i, &name);
-		if (ret < 0 || strlen(name) == 0)
-			continue;
-
 		parent_name = of_clk_get_parent_name(np, i);
 		ret = of_property_read_u32_index(np, idxname, i, &clkidx);
 		if (parent_name == NULL || ret < 0)
 			break;
 
 		if (clkidx >= MSTP_MAX_CLOCKS) {
-			pr_err("%s: invalid clock %s %s index %u)\n",
-			       __func__, np->name, name, clkidx);
+			pr_err("%s: invalid clock %s index %u)\n",
+			       __func__, np->name, clkidx);
 			continue;
 		}
 
+		if (of_property_read_string_index(np, "clock-output-names",
+						  i, &name) < 0)
+			allocated_name = name = kasprintf(GFP_KERNEL, "%s.%u",
+							   np->name, clkidx);
+
 		clks[clkidx] = cpg_mstp_clock_register(name, parent_name,
 						       clkidx, group);
 		if (!IS_ERR(clks[clkidx])) {

@@ -225,12 +225,18 @@ static void __init cpg_mstp_clocks_init(
 			 *
 			 * FIXME: Remove this when all devices that require a
 			 * clock will be instantiated from DT.
+			 *
+			 * We currently register clkdev only when the DT
+			 * property clock-output-names is present.
 			 */
-			clk_register_clkdev(clks[clkidx], name, NULL);
+			if (!allocated_name)
+				clk_register_clkdev(clks[clkidx], name, NULL);
 		} else {
 			pr_err("%s: failed to register %s %s clock (%ld)\n",
 			       __func__, np->name, name, PTR_ERR(clks[clkidx]));
 		}
+
+		kfree(allocated_name);
 	}
 
 	of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);

From: Gaku Inami <[email protected]>

This V7 patch adds initial CPG support for R-Car Generation 3 and in particular the R8A7795 SoC.

The R-Car Gen3 clock hardware has a register write protection feature that needs to be shared between the CPG function and the MSTP hardware somehow. So far this feature is simply ignored.

---

Changes since V6: (Magnus Damm <[email protected]>)
- Moved PLL1 div-by-2 unit to outside of the CPG - thanks Laurent!
- Updated table to reflect PLL1 divider move.
- Reworked clock registration loop to prevent re-registering clocks.

Changes since V5: (Magnus Damm <[email protected]>)
- Removed unused spinlock, use 0x3f as mask - thanks Laurent!
- Fixed space -> tab for DT binding documentation - thanks Geert!
- Postponed PLL1 divide-by-2 rewrite - requires a tad more effort.
- Updated commit log

Changes since V4: (Magnus Damm <[email protected]>)
- Simplified clks array handling - thanks Geert!
- Updated th DT binding documentation to reflect latest state
- of_property_count_strings() -> of_property_count_u32_elems() fix

Changes since V3: (Magnus Damm <[email protected]>)
- Reworked driver to incorporate most feedback from Stephen Boyd - thanks!!
- Major things like syscon and driver model require more discussion.
- Added hunk to build drivers/clk/shmobile if ARCH_RENESAS is set.

Changes since V2: (Magnus Damm <[email protected]>)
- Reworked driver to rely on clock index instead of strings.
- Dropped use of "clock-output-names".

Earlier versions: Kuninori Morimoto <[email protected]> Initial version: Gaku Inami <[email protected]>

 Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt |   32 +
 drivers/clk/Makefile                                                     |    1 
 drivers/clk/shmobile/Makefile                                            |    1 
 drivers/clk/shmobile/clk-rcar-gen3.c                                     |  242 ++++++++++
 4 files changed, 276 insertions(+)

@@ -0,0 +1,32 @@
+* Renesas R-Car Gen3 Clock Pulse Generator (CPG)
+
+The CPG generates core clocks for the R-Car Gen3 SoCs. It includes three PLLs
+and several fixed ratio dividers.
+
+Required Properties:
+
+  - compatible: Must be one of
+    - "renesas,r8a7795-cpg-clocks" for the r8a7795 CPG
+    - "renesas,rcar-gen3-cpg-clocks" for the generic R-Car Gen3 CPG
+
+  - reg: Base address and length of the memory resource used by the CPG
+
+  - clocks: References to the parent clocks: first to the EXTAL clock
+  - #clock-cells: Must be 1
+  - clock-indices: Indices of the exported clocks
+
+Example
+-------
+
+	cpg_clocks: cpg_clocks@e6150000 {
+		compatible = "renesas,r8a7795-cpg-clocks",
+			     "renesas,rcar-gen3-cpg-clocks";
+		reg = <0 0xe6150000 0 0x1000>;
+		clocks = <&extal_clk>;
+		#clock-cells = <1>;
+		clock-indices = <
+				R8A7795_CLK_MAIN R8A7795_CLK_PLL0
+				R8A7795_CLK_PLL1 R8A7795_CLK_PLL2
+				R8A7795_CLK_PLL3 R8A7795_CLK_PLL4
+		>;
+	};

@@ -67,6 +67,7 @@ obj-$(CONFIG_COMMON_CLK_QCOM)		+= qcom/
 obj-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip/
 obj-$(CONFIG_COMMON_CLK_SAMSUNG)	+= samsung/
 obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= shmobile/
+obj-$(CONFIG_ARCH_RENESAS)		+= shmobile/
 obj-$(CONFIG_ARCH_SIRF)			+= sirf/
 obj-$(CONFIG_ARCH_SOCFPGA)		+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)		+= spear/

@@ -8,4 +8,5 @@ obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-
 obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o clk-mstp.o clk-div6.o
 obj-$(CONFIG_ARCH_R8A7793)		+= clk-rcar-gen2.o clk-mstp.o clk-div6.o
 obj-$(CONFIG_ARCH_R8A7794)		+= clk-rcar-gen2.o clk-mstp.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7795)		+= clk-rcar-gen3.o clk-mstp.o clk-div6.o
 obj-$(CONFIG_ARCH_SH73A0)		+= clk-sh73a0.o clk-mstp.o clk-div6.o

From: Geert Uytterhoeven <[email protected]>

Add Clock Domain support to the R-Car Gen3 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed through an MSTP clock should be tagged in DT with a proper "power-domains" property.

---

Changes since V6:
- None

Changes since V5:
- Rebased to fit on top of updated CPG DT binding document

Changes since V4:
- Rebased to fit on top of updated CPG DT binding document

Changes since V3:
- Fixed so correct file is actually used. =)
- Took V2 from Geert but filtered out Kconfig.platforms bits

 Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt |   26 +++++++++-
 drivers/clk/shmobile/clk-rcar-gen3.c                                     |    2 
 2 files changed, 26 insertions(+), 2 deletions(-)

@@ -2,6 +2,8 @@
 
 The CPG generates core clocks for the R-Car Gen3 SoCs. It includes three PLLs
 and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
 
 Required Properties:
 

@@ -14,9 +16,17 @@ Required Properties:
   - clocks: References to the parent clocks: first to the EXTAL clock
   - #clock-cells: Must be 1
   - clock-indices: Indices of the exported clocks
+  - #power-domain-cells: Must be 0
 
-Example
--------
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
+
+Examples
+--------
+
+  - CPG device node:
 
 	cpg_clocks: cpg_clocks@e6150000 {
 		compatible = "renesas,r8a7795-cpg-clocks",

@@ -29,4 +39,16 @@ Example
 				R8A7795_CLK_PLL1 R8A7795_CLK_PLL2
 				R8A7795_CLK_PLL3 R8A7795_CLK_PLL4
 		>;
+		#power-domain-cells = <0>;
+	};
+
+  - CPG/MSTP Clock Domain member device node:
+
+	scif2: serial@e6e88000 {
+		compatible = "renesas,scif-r8a7795", "renesas,scif";
+		reg = <0 0xe6e88000 0 64>;
+		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks RCAR_R8A7795_CLK_SCIF2>;
+		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 	};

@@ -236,6 +236,8 @@ static void __init rcar_gen3_cpg_clocks_
 	}
 
 	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+	cpg_mstp_add_clk_domain(np);
 }
 CLK_OF_DECLARE(rcar_gen3_cpg_clks, "renesas,rcar-gen3-cpg-clocks",
 	       rcar_gen3_cpg_clocks_init);

Hi Magnus,

Hi Geert,

Sorry, I forgot to refresh the patch. Will update next time I resend.

Thanks,

/ magnus

Hi Magnus,

Don't worry, I can handle it fine.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds