fix clock issue for fsl,spdi
v2 cover fix clock issue for fsl,spdi
fix clock issue for fsl,spdi in imx6.
Changes in v2:
move the dts change to another patch
Shengjiu Wang (2):
clk: imx6: Add SPDIF_GCLK clock in clock tree
ARM: dts: imx6: change the core clock of spdif
arch/arm/boot/dts/imx6qdl.dtsi | 2 +- arch/arm/boot/dts/imx6sl.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/imx6sx.dtsi | 2 +- drivers/clk/imx/clk-imx6q.c | 4 +++- drivers/clk/imx/clk-imx6sl.c | 4 +++- drivers/clk/imx/clk-imx6sx.c | 1 + include/dt-bindings/clock/imx6qdl-clock.h | 3 ++- include/dt-bindings/clock/imx6sl-clock.h | 3 ++- include/dt-bindings/clock/imx6sx-clock.h | 3 ++- 9 files changed, 31 insertions(+), 7 deletions(-)
Signature · 1 line
1.9.1
PATCH v2 1/2 clk: imx6: Add SPDIF_GCLK clock in clock tree
As spdif driver will register SPDIF clock to regmap, regmap will do clk_prepare in init function, so SPDIF clock is prepared in probe, then its root clock (pll clock) is prepared also, which cause the arm can't enter low power mode.
Add SPDIF_GCLK in clock tree which share same gate bits with SPDIF clock. Its root clock is ipg clock, and register it to regmap, then the issue cam be fixed.
--- drivers/clk/imx/clk-imx6q.c | 4 +++- drivers/clk/imx/clk-imx6sl.c | 4 +++- drivers/clk/imx/clk-imx6sx.c | 1 + include/dt-bindings/clock/imx6qdl-clock.h | 3 ++- include/dt-bindings/clock/imx6sl-clock.h | 3 ++- include/dt-bindings/clock/imx6sx-clock.h | 3 ++- 6 files changed, 13 insertions(+), 5 deletions(-)
drivers/clk/imx/clk-imx6q.c +3 -1
@@ -119,6 +119,7 @@ static unsigned int share_count_ssi1;static unsigned int share_count_ssi2;static unsigned int share_count_ssi3;static unsigned int share_count_mipi_core_cfg; +static unsigned int share_count_spdif;static inline int clk_on_imx6q (void ) {
@@ -456,7 +457,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_SATA ] =imx_clk_gate2 ("sata" ,"ahb" , base +0x7c ,4 ); clk[IMX6QDL_CLK_SDMA ] =imx_clk_gate2 ("sdma" ,"ahb" , base +0x7c ,6 ); clk[IMX6QDL_CLK_SPBA ] =imx_clk_gate2 ("spba" ,"ipg" , base +0x7c ,12 ); - clk[IMX6QDL_CLK_SPDIF ] =imx_clk_gate2 ("spdif" ,"spdif_podf" , base +0x7c ,14 ); + clk[IMX6QDL_CLK_SPDIF ] =imx_clk_gate2_shared ("spdif" ,"spdif_podf" , base +0x7c ,14 , &share_count_spdif); + clk[IMX6QDL_CLK_SPDIF_GCLK ] =imx_clk_gate2_shared ("spdif_gclk" ,"ipg" , base +0x7c ,14 , &share_count_spdif); clk[IMX6QDL_CLK_SSI1_IPG ] =imx_clk_gate2_shared ("ssi1_ipg" ,"ipg" , base +0x7c ,18 , &share_count_ssi1); clk[IMX6QDL_CLK_SSI2_IPG ] =imx_clk_gate2_shared ("ssi2_ipg" ,"ipg" , base +0x7c ,20 , &share_count_ssi2); clk[IMX6QDL_CLK_SSI3_IPG ] =imx_clk_gate2_shared ("ssi3_ipg" ,"ipg" , base +0x7c ,22 , &share_count_ssi3);
drivers/clk/imx/clk-imx6sl.c +3 -1
@@ -97,6 +97,7 @@ static struct clk_div_table video_div_table[] = {static unsigned int share_count_ssi1;static unsigned int share_count_ssi2;static unsigned int share_count_ssi3; +static unsigned int share_count_spdif;static struct clk *clks[IMX6SL_CLK_END ];static struct clk_onecell_data clk_data;
@@ -391,7 +392,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clks[IMX6SL_CLK_PWM4 ] =imx_clk_gate2 ("pwm4" ,"perclk" , base +0x78 ,22 ); clks[IMX6SL_CLK_SDMA ] =imx_clk_gate2 ("sdma" ,"ipg" , base +0x7c ,6 ); clks[IMX6SL_CLK_SPBA ] =imx_clk_gate2 ("spba" ,"ipg" , base +0x7c ,12 ); - clks[IMX6SL_CLK_SPDIF ] =imx_clk_gate2 ("spdif" ,"spdif0_podf" , base +0x7c ,14 ); + clks[IMX6SL_CLK_SPDIF ] =imx_clk_gate2_shared ("spdif" ,"spdif0_podf" , base +0x7c ,14 , &share_count_spdif); + clks[IMX6SL_CLK_SPDIF_GCLK ] =imx_clk_gate2_shared ("spdif_gclk" ,"ipg" , base +0x7c ,14 , &share_count_spdif); clks[IMX6SL_CLK_SSI1_IPG ] =imx_clk_gate2_shared ("ssi1_ipg" ,"ipg" , base +0x7c ,18 , &share_count_ssi1); clks[IMX6SL_CLK_SSI2_IPG ] =imx_clk_gate2_shared ("ssi2_ipg" ,"ipg" , base +0x7c ,20 , &share_count_ssi2); clks[IMX6SL_CLK_SSI3_IPG ] =imx_clk_gate2_shared ("ssi3_ipg" ,"ipg" , base +0x7c ,22 , &share_count_ssi3);
drivers/clk/imx/clk-imx6sx.c +1 -0
@@ -454,6 +454,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_SPBA ] =imx_clk_gate2 ("spba" ,"ipg" , base +0x7c ,12 ); clks[IMX6SX_CLK_AUDIO ] =imx_clk_gate2_shared ("audio" ,"audio_podf" , base +0x7c ,14 , &share_count_audio); clks[IMX6SX_CLK_SPDIF ] =imx_clk_gate2_shared ("spdif" ,"spdif_podf" , base +0x7c ,14 , &share_count_audio); + clks[IMX6SX_CLK_SPDIF_GCLK ] =imx_clk_gate2_shared ("spdif_gclk" ,"ipg" , base +0x7c ,14 , &share_count_audio); clks[IMX6SX_CLK_SSI1_IPG ] =imx_clk_gate2_shared ("ssi1_ipg" ,"ipg" , base +0x7c ,18 , &share_count_ssi1); clks[IMX6SX_CLK_SSI2_IPG ] =imx_clk_gate2_shared ("ssi2_ipg" ,"ipg" , base +0x7c ,20 , &share_count_ssi2); clks[IMX6SX_CLK_SSI3_IPG ] =imx_clk_gate2_shared ("ssi3_ipg" ,"ipg" , base +0x7c ,22 , &share_count_ssi3);
include/dt-bindings/clock/imx6qdl-clock.h +2 -1
@@ -254,6 +254,7 @@#define IMX6QDL_CLK_CAAM_MEM 241#define IMX6QDL_CLK_CAAM_ACLK 242#define IMX6QDL_CLK_CAAM_IPG 243 -#define IMX6QDL_CLK_END 244 +#define IMX6QDL_CLK_SPDIF_GCLK 244 +#define IMX6QDL_CLK_END 245#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
include/dt-bindings/clock/imx6sl-clock.h +2 -1
@@ -174,6 +174,7 @@#define IMX6SL_CLK_SSI1_IPG 161#define IMX6SL_CLK_SSI2_IPG 162#define IMX6SL_CLK_SSI3_IPG 163 -#define IMX6SL_CLK_END 164 +#define IMX6SL_CLK_SPDIF_GCLK 164 +#define IMX6SL_CLK_END 165#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
include/dt-bindings/clock/imx6sx-clock.h +2 -1
@@ -274,6 +274,7 @@#define IMX6SX_PLL5_BYPASS 261#define IMX6SX_PLL6_BYPASS 262#define IMX6SX_PLL7_BYPASS 263 -#define IMX6SX_CLK_CLK_END 264 +#define IMX6SX_CLK_SPDIF_GCLK 264 +#define IMX6SX_CLK_CLK_END 265#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
Signature · 1 line
1.9.1
Re: [PATCH V2 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
Quoted 4 lines · Shengjiu Wang
As spdif driver will register SPDIF clock to regmap, regmap will do
clk_preparein init function, so SPDIF clock is prepared in probe, then its root clock (pll clock) is prepared also, which cause the arm can't enter low power mode.
Can you help me understand why ARM cannot enter low power mode when pll clock is prepared?
Shawn
Quoted 112 lines
Add
SPDIF_GCLKin clock tree which share same gate bits with SPDIF clock. Its root clock is ipg clock, and register it to regmap, then the issue cam be fixed.Signed-off-by Shengjiu Wang <[email protected]>--- drivers/clk/imx/clk-imx6q.c | 4 +++- drivers/clk/imx/clk-imx6sl.c | 4 +++- drivers/clk/imx/clk-imx6sx.c | 1 + include/dt-bindings/clock/imx6qdl-clock.h | 3 ++- include/dt-bindings/clock/imx6sl-clock.h | 3 ++- include/dt-bindings/clock/imx6sx-clock.h | 3 ++- 6 files changed, 13 insertions(+), 5 deletions(-)drivers/clk/imx/clk-imx6q.c +3
-1@@ -119,6 +119,7 @@ static unsigned int share_count_ssi1;static unsigned int share_count_ssi2;static unsigned int share_count_ssi3;static unsigned int share_count_mipi_core_cfg; +static unsigned int share_count_spdif;static inline int clk_on_imx6q (void ) {@@ -456,7 +457,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_SATA ] =imx_clk_gate2 ("sata" ,"ahb" , base +0x7c ,4 ); clk[IMX6QDL_CLK_SDMA ] =imx_clk_gate2 ("sdma" ,"ahb" , base +0x7c ,6 ); clk[IMX6QDL_CLK_SPBA ] =imx_clk_gate2 ("spba" ,"ipg" , base +0x7c ,12 ); - clk[IMX6QDL_CLK_SPDIF ] =imx_clk_gate2 ("spdif" ,"spdif_podf" , base +0x7c ,14 ); + clk[IMX6QDL_CLK_SPDIF ] =imx_clk_gate2_shared ("spdif" ,"spdif_podf" , base +0x7c ,14 , &share_count_spdif); + clk[IMX6QDL_CLK_SPDIF_GCLK ] =imx_clk_gate2_shared ("spdif_gclk" ,"ipg" , base +0x7c ,14 , &share_count_spdif); clk[IMX6QDL_CLK_SSI1_IPG ] =imx_clk_gate2_shared ("ssi1_ipg" ,"ipg" , base +0x7c ,18 , &share_count_ssi1); clk[IMX6QDL_CLK_SSI2_IPG ] =imx_clk_gate2_shared ("ssi2_ipg" ,"ipg" , base +0x7c ,20 , &share_count_ssi2); clk[IMX6QDL_CLK_SSI3_IPG ] =imx_clk_gate2_shared ("ssi3_ipg" ,"ipg" , base +0x7c ,22 , &share_count_ssi3);drivers/clk/imx/clk-imx6sl.c +3
-1@@ -97,6 +97,7 @@ static struct clk_div_table video_div_table[] = {static unsigned int share_count_ssi1;static unsigned int share_count_ssi2;static unsigned int share_count_ssi3; +static unsigned int share_count_spdif;static struct clk *clks[IMX6SL_CLK_END ];static struct clk_onecell_data clk_data;@@ -391,7 +392,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clks[IMX6SL_CLK_PWM4 ] =imx_clk_gate2 ("pwm4" ,"perclk" , base +0x78 ,22 ); clks[IMX6SL_CLK_SDMA ] =imx_clk_gate2 ("sdma" ,"ipg" , base +0x7c ,6 ); clks[IMX6SL_CLK_SPBA ] =imx_clk_gate2 ("spba" ,"ipg" , base +0x7c ,12 ); - clks[IMX6SL_CLK_SPDIF ] =imx_clk_gate2 ("spdif" ,"spdif0_podf" , base +0x7c ,14 ); + clks[IMX6SL_CLK_SPDIF ] =imx_clk_gate2_shared ("spdif" ,"spdif0_podf" , base +0x7c ,14 , &share_count_spdif); + clks[IMX6SL_CLK_SPDIF_GCLK ] =imx_clk_gate2_shared ("spdif_gclk" ,"ipg" , base +0x7c ,14 , &share_count_spdif); clks[IMX6SL_CLK_SSI1_IPG ] =imx_clk_gate2_shared ("ssi1_ipg" ,"ipg" , base +0x7c ,18 , &share_count_ssi1); clks[IMX6SL_CLK_SSI2_IPG ] =imx_clk_gate2_shared ("ssi2_ipg" ,"ipg" , base +0x7c ,20 , &share_count_ssi2); clks[IMX6SL_CLK_SSI3_IPG ] =imx_clk_gate2_shared ("ssi3_ipg" ,"ipg" , base +0x7c ,22 , &share_count_ssi3);drivers/clk/imx/clk-imx6sx.c +1
-0@@ -454,6 +454,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_SPBA ] =imx_clk_gate2 ("spba" ,"ipg" , base +0x7c ,12 ); clks[IMX6SX_CLK_AUDIO ] =imx_clk_gate2_shared ("audio" ,"audio_podf" , base +0x7c ,14 , &share_count_audio); clks[IMX6SX_CLK_SPDIF ] =imx_clk_gate2_shared ("spdif" ,"spdif_podf" , base +0x7c ,14 , &share_count_audio); + clks[IMX6SX_CLK_SPDIF_GCLK ] =imx_clk_gate2_shared ("spdif_gclk" ,"ipg" , base +0x7c ,14 , &share_count_audio); clks[IMX6SX_CLK_SSI1_IPG ] =imx_clk_gate2_shared ("ssi1_ipg" ,"ipg" , base +0x7c ,18 , &share_count_ssi1); clks[IMX6SX_CLK_SSI2_IPG ] =imx_clk_gate2_shared ("ssi2_ipg" ,"ipg" , base +0x7c ,20 , &share_count_ssi2); clks[IMX6SX_CLK_SSI3_IPG ] =imx_clk_gate2_shared ("ssi3_ipg" ,"ipg" , base +0x7c ,22 , &share_count_ssi3);include/dt-bindings/clock/imx6qdl-clock.h +2
-1@@ -254,6 +254,7 @@#define IMX6QDL_CLK_CAAM_MEM 241#define IMX6QDL_CLK_CAAM_ACLK 242#define IMX6QDL_CLK_CAAM_IPG 243 -#define IMX6QDL_CLK_END 244 +#define IMX6QDL_CLK_SPDIF_GCLK 244 +#define IMX6QDL_CLK_END 245#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ include/dt-bindings/clock/imx6sl-clock.h +2
-1@@ -174,6 +174,7 @@#define IMX6SL_CLK_SSI1_IPG 161#define IMX6SL_CLK_SSI2_IPG 162#define IMX6SL_CLK_SSI3_IPG 163 -#define IMX6SL_CLK_END 164 +#define IMX6SL_CLK_SPDIF_GCLK 164 +#define IMX6SL_CLK_END 165#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ include/dt-bindings/clock/imx6sx-clock.h +2
-1@@ -274,6 +274,7 @@#define IMX6SX_PLL5_BYPASS 261#define IMX6SX_PLL6_BYPASS 262#define IMX6SX_PLL7_BYPASS 263 -#define IMX6SX_CLK_CLK_END 264 +#define IMX6SX_CLK_SPDIF_GCLK 264 +#define IMX6SX_CLK_CLK_END 265#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ Signature · 1 line
1.9.1
Re: [PATCH V2 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
Quoted 10 lines · Shawn Guo
Quoted 4 lines · Shengjiu Wang
As spdif driver will register SPDIF clock to regmap, regmap will do
clk_preparein init function, so SPDIF clock is prepared in probe, then its root clock (pll clock) is prepared also, which cause the arm can't enter low power mode.Can you help me understand why ARM cannot enter low power mode when pll clock is prepared?
Shawn
Hi Shawn
In i.mx clock framework, when pll clk is prepared, it will be powerup. when
enterring low power idle mode, the powerdown bit is checked, when pll is not powerdown state, chip will not enter low power idle mode.
best regards
wang shengjiu
Quoted 113 lines
Quoted 113 lines
Add
SPDIF_GCLKin clock tree which share same gate bits with SPDIF clock. Its root clock is ipg clock, and register it to regmap, then the issue cam be fixed.Signed-off-by Shengjiu Wang <[email protected]>--- drivers/clk/imx/clk-imx6q.c | 4 +++- drivers/clk/imx/clk-imx6sl.c | 4 +++- drivers/clk/imx/clk-imx6sx.c | 1 + include/dt-bindings/clock/imx6qdl-clock.h | 3 ++- include/dt-bindings/clock/imx6sl-clock.h | 3 ++- include/dt-bindings/clock/imx6sx-clock.h | 3 ++- 6 files changed, 13 insertions(+), 5 deletions(-)drivers/clk/imx/clk-imx6q.c +3
-1@@ -119,6 +119,7 @@ static unsigned int share_count_ssi1;static unsigned int share_count_ssi2;static unsigned int share_count_ssi3;static unsigned int share_count_mipi_core_cfg; +static unsigned int share_count_spdif;static inline int clk_on_imx6q (void ) {@@ -456,7 +457,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_SATA ] =imx_clk_gate2 ("sata" ,"ahb" , base +0x7c ,4 ); clk[IMX6QDL_CLK_SDMA ] =imx_clk_gate2 ("sdma" ,"ahb" , base +0x7c ,6 ); clk[IMX6QDL_CLK_SPBA ] =imx_clk_gate2 ("spba" ,"ipg" , base +0x7c ,12 ); - clk[IMX6QDL_CLK_SPDIF ] =imx_clk_gate2 ("spdif" ,"spdif_podf" , base +0x7c ,14 ); + clk[IMX6QDL_CLK_SPDIF ] =imx_clk_gate2_shared ("spdif" ,"spdif_podf" , base +0x7c ,14 , &share_count_spdif); + clk[IMX6QDL_CLK_SPDIF_GCLK ] =imx_clk_gate2_shared ("spdif_gclk" ,"ipg" , base +0x7c ,14 , &share_count_spdif); clk[IMX6QDL_CLK_SSI1_IPG ] =imx_clk_gate2_shared ("ssi1_ipg" ,"ipg" , base +0x7c ,18 , &share_count_ssi1); clk[IMX6QDL_CLK_SSI2_IPG ] =imx_clk_gate2_shared ("ssi2_ipg" ,"ipg" , base +0x7c ,20 , &share_count_ssi2); clk[IMX6QDL_CLK_SSI3_IPG ] =imx_clk_gate2_shared ("ssi3_ipg" ,"ipg" , base +0x7c ,22 , &share_count_ssi3);drivers/clk/imx/clk-imx6sl.c +3
-1@@ -97,6 +97,7 @@ static struct clk_div_table video_div_table[] = {static unsigned int share_count_ssi1;static unsigned int share_count_ssi2;static unsigned int share_count_ssi3; +static unsigned int share_count_spdif;static struct clk *clks[IMX6SL_CLK_END ];static struct clk_onecell_data clk_data;@@ -391,7 +392,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clks[IMX6SL_CLK_PWM4 ] =imx_clk_gate2 ("pwm4" ,"perclk" , base +0x78 ,22 ); clks[IMX6SL_CLK_SDMA ] =imx_clk_gate2 ("sdma" ,"ipg" , base +0x7c ,6 ); clks[IMX6SL_CLK_SPBA ] =imx_clk_gate2 ("spba" ,"ipg" , base +0x7c ,12 ); - clks[IMX6SL_CLK_SPDIF ] =imx_clk_gate2 ("spdif" ,"spdif0_podf" , base +0x7c ,14 ); + clks[IMX6SL_CLK_SPDIF ] =imx_clk_gate2_shared ("spdif" ,"spdif0_podf" , base +0x7c ,14 , &share_count_spdif); + clks[IMX6SL_CLK_SPDIF_GCLK ] =imx_clk_gate2_shared ("spdif_gclk" ,"ipg" , base +0x7c ,14 , &share_count_spdif); clks[IMX6SL_CLK_SSI1_IPG ] =imx_clk_gate2_shared ("ssi1_ipg" ,"ipg" , base +0x7c ,18 , &share_count_ssi1); clks[IMX6SL_CLK_SSI2_IPG ] =imx_clk_gate2_shared ("ssi2_ipg" ,"ipg" , base +0x7c ,20 , &share_count_ssi2); clks[IMX6SL_CLK_SSI3_IPG ] =imx_clk_gate2_shared ("ssi3_ipg" ,"ipg" , base +0x7c ,22 , &share_count_ssi3);drivers/clk/imx/clk-imx6sx.c +1
-0@@ -454,6 +454,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clks[IMX6SX_CLK_SPBA ] =imx_clk_gate2 ("spba" ,"ipg" , base +0x7c ,12 ); clks[IMX6SX_CLK_AUDIO ] =imx_clk_gate2_shared ("audio" ,"audio_podf" , base +0x7c ,14 , &share_count_audio); clks[IMX6SX_CLK_SPDIF ] =imx_clk_gate2_shared ("spdif" ,"spdif_podf" , base +0x7c ,14 , &share_count_audio); + clks[IMX6SX_CLK_SPDIF_GCLK ] =imx_clk_gate2_shared ("spdif_gclk" ,"ipg" , base +0x7c ,14 , &share_count_audio); clks[IMX6SX_CLK_SSI1_IPG ] =imx_clk_gate2_shared ("ssi1_ipg" ,"ipg" , base +0x7c ,18 , &share_count_ssi1); clks[IMX6SX_CLK_SSI2_IPG ] =imx_clk_gate2_shared ("ssi2_ipg" ,"ipg" , base +0x7c ,20 , &share_count_ssi2); clks[IMX6SX_CLK_SSI3_IPG ] =imx_clk_gate2_shared ("ssi3_ipg" ,"ipg" , base +0x7c ,22 , &share_count_ssi3);include/dt-bindings/clock/imx6qdl-clock.h +2
-1@@ -254,6 +254,7 @@#define IMX6QDL_CLK_CAAM_MEM 241#define IMX6QDL_CLK_CAAM_ACLK 242#define IMX6QDL_CLK_CAAM_IPG 243 -#define IMX6QDL_CLK_END 244 +#define IMX6QDL_CLK_SPDIF_GCLK 244 +#define IMX6QDL_CLK_END 245#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ include/dt-bindings/clock/imx6sl-clock.h +2
-1@@ -174,6 +174,7 @@#define IMX6SL_CLK_SSI1_IPG 161#define IMX6SL_CLK_SSI2_IPG 162#define IMX6SL_CLK_SSI3_IPG 163 -#define IMX6SL_CLK_END 164 +#define IMX6SL_CLK_SPDIF_GCLK 164 +#define IMX6SL_CLK_END 165#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ include/dt-bindings/clock/imx6sx-clock.h +2
-1@@ -274,6 +274,7 @@#define IMX6SX_PLL5_BYPASS 261#define IMX6SX_PLL6_BYPASS 262#define IMX6SX_PLL7_BYPASS 263 -#define IMX6SX_CLK_CLK_END 264 +#define IMX6SX_CLK_SPDIF_GCLK 264 +#define IMX6SX_CLK_CLK_END 265#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ Signature · 1 line
1.9.1
Re: [PATCH V2 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
Quoted 10 lines · Shengjiu Wang
Quoted 9 lines · Shawn Guo
Quoted 4 lines · Shengjiu Wang
As spdif driver will register SPDIF clock to regmap, regmap will do
clk_preparein init function, so SPDIF clock is prepared in probe, then its root clock (pll clock) is prepared also, which cause the arm can't enter low power mode.Can you help me understand why ARM cannot enter low power mode when pll clock is prepared?
Quoted 6 lines
Quoted 1 line
Shawn
Hi Shawn
In i.mx clock framework, when pll clk is prepared, it will be powerup. when
enterring low power idle mode, the powerdown bit is checked, when pll is not powerdown state, chip will not enter low power idle mode.
So this is not a SPDIF specific problem, and any device driver preparing its clock that is a child of pll clock will run into this problem, right? If so, we should purchase a more generic solution than such device specific one.
Shawn
Re: [PATCH V2 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
Quoted 18 lines · Shawn Guo
Quoted 10 lines · Shengjiu Wang
Quoted 9 lines · Shawn Guo
Quoted 4 lines · Shengjiu Wang
As spdif driver will register SPDIF clock to regmap, regmap will do
clk_preparein init function, so SPDIF clock is prepared in probe, then its root clock (pll clock) is prepared also, which cause the arm can't enter low power mode.Can you help me understand why ARM cannot enter low power mode when pll clock is prepared?
Quoted 6 lines
Quoted 1 line
Shawn
Hi Shawn
In i.mx clock framework, when pll clk is prepared, it will be powerup. when
enterring low power idle mode, the powerdown bit is checked, when pll is not powerdown state, chip will not enter low power idle mode.
Quoted 6 lines
So this is not a SPDIF specific problem, and any device driver preparing its clock that is a child of pll clock will run into this problem, right? If so, we should purchase a more generic solution than such device specific one.
Shawn
Hi shawn
SPDIF_GCLK is also spdif's clock, it use a same enable bit with SPDIF_ROOT_CLK, We didn't separate them in clock tree before.
I can't find a generic solution. But anyway if there is a solution or not, I think we'd better to separate them.
best regards
wang shengjiu
Re: [PATCH V2 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
Quoted 2 lines · Shengjiu Wang
SPDIF_GCLKis also spdif's clock, it use a same enable bit withSPDIF_ROOT_CLK, We didn't separate them in clock tree before.
Is it the clock described as "Global clock" in Reference Manual, SPDIF chapter? If that's the case, you are just adding a missing SPDIF clock rather than fixing a low power mode issue, and I will be fine. But still you should reword the commit log to make it clear, that the patch is to correct a SPDIF clock setting issue, which is just discovered by low power mode support.
Shawn
Re: [PATCH V2 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
Quoted 5 lines · Shawn Guo
Quoted 2 lines · Shengjiu Wang
SPDIF_GCLKis also spdif's clock, it use a same enable bit withSPDIF_ROOT_CLK, We didn't separate them in clock tree before.Is it the clock described as "Global clock" in Reference Manual, SPDIF
Yes.
Quoted 6 lines
chapter? If that's the case, you are just adding a missing SPDIF clock rather than fixing a low power mode issue, and I will be fine. But still you should reword the commit log to make it clear, that the patch is to correct a SPDIF clock setting issue, which is just discovered by low power mode support.
Ok, I will refine the patch comments, and send it later.
Quoted 1 line
Shawn
PATCH v2 2/2 ARM: dts: imx6: change the core clock of spdif
In reply to Shengjiu WangAs core clock is changed in clock tree, the dts also need to be updated.
--- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- arch/arm/boot/dts/imx6sl.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/imx6sx.dtsi | 2 +- 3 files changed, 18 insertions(+), 2 deletions(-)
arch/arm/boot/dts/imx6qdl.dtsi +1 -1
@@ -218,7 +218,7 @@ dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; dma-names = "rx", "tx"; - clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>, + clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
arch/arm/boot/dts/imx6sl.dtsi +16 -0
@@ -135,8 +135,24 @@ ranges; spdif: spdif at 02004000 { + compatible = "fsl,imx6sl-spdif", + "fsl,imx35-spdif"; reg = <0x02004000 0x4000>; interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 14 18 0>, + <&sdma 15 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>, + <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "dma"; + status = "disabled"; }; ecspi1: ecspi at 02008000 {
arch/arm/boot/dts/imx6sx.dtsi +1 -1
@@ -211,7 +211,7 @@ dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; dma-names = "rx", "tx"; - clocks = <&clks IMX6SX_CLK_SPDIF>, + clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>, <&clks IMX6SX_CLK_OSC>, <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>, <&clks 0>,
Signature · 1 line
1.9.1