ARM: dts: imx: imx7d-sbd remove fixed can2-3v3 regulator
Subsystems (5)
PATCH v7 1/7 ARM: dts: imx: imx7d-sbd remove fixed can2-3v3 regulator
Remove incorrect can2-3v3 fixed regulator, imx7d-sdb doesn't have a dedicated can2 fixed regulator instead it shares PERI_3V3 fixed regulator (RT8070ZS) which is enabled by default (hardwired) from pmic pfuze3000 NVCC_3V3 power rail.
---
Changes for V7: New patch in series
arch/arm/boot/dts/imx7d-sdb.dts | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-)
arch/arm/boot/dts/imx7d-sdb.dts +1 -10
@@ -78,16 +78,7 @@ enable-active-high; }; - reg_can2_3v3: regulator at 2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - reg_vref_1v8: regulator at 3 { + reg_vref_1v8: regulator at 2 { compatible = "regulator-fixed"; reg = <3>; regulator-name = "vref-1v8";
Signature · 1 line
2.1.4
PATCH v7 2/7 ARM: dts: imx: imx7d-sbd add iomuxc-lpsr hoggrp-2 pads
Add imx7d-sdb iomuxc-lpsr hoggrp-2 default pads settings Add iomuxc-lpsr usb_otg1_vbus pinctrl settings
---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Resend
Changes for V5: Resend
Changes for V6:
- Add wdog pinctrl group, add comments for hog2 group gpios Changes for V7:
- Remove wdog pinctrl settings as they are not currently used
- Add pinctrl_usb_otg1_vbus settings
arch/arm/boot/dts/imx7d-sdb.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
arch/arm/boot/dts/imx7d-sdb.dts +21 -0
@@ -65,6 +65,8 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_vbus>; enable-active-high; };
@@ -410,3 +412,22 @@ }; }; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2>; + + imx7d-sdb { + pinctrl_hog_2: hog2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x59 /* sensor_int_b */ + >; + }; + + pinctrl_usb_otg1_vbus: usbotg1vbusgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 /* usb_otg1_pwr */ + >; + }; + }; +};
Signature · 1 line
2.1.4
PATCH v7 3/7 ARM: dts: imx: imx7d-sbd add usb_otg2_vbus pinctrl settings
In reply to Adrian AlonsoAdd usb_otg2_vbus pinctrl settings
---
Changes for V7: New patch in series
arch/arm/boot/dts/imx7d-sdb.dts | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)
arch/arm/boot/dts/imx7d-sdb.dts +8 -1
@@ -77,6 +77,8 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2_vbus>; enable-active-high; };
@@ -254,11 +256,16 @@ imx7d-sdb { pinctrl_hog: hoggrp { fsl,pins = < - MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ >; }; + pinctrl_usb_otg2_vbus: usbotg2vbusgrp { + fsl,pins = < + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* usb_otg2_pwr */ + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
Signature · 1 line
2.1.4
PATCH v7 4/7 pinctrl: freescale: imx: allow mux_reg offset zero
In reply to Adrian AlonsoAllow mux_reg offset zero to be a valid pin_id, on imx7d mux_conf reg offset is zero for iomuxc-lspr controller
---
Changes for V2: Resend
Changes for V3: Resend
Changes for V4: Simplify pin_id assigment when ZERO_OFFSET_VALID is set Changes for V5:
- Drop patch pinctrl: freescale: imx: add ZERO_OFFSET_VALID flag
- Allow mux_reg ZERO OFFSET as pin_id
Changes for V6: Restore ZERO_OFFSET_VALID flag
Changes for V7: Resend
drivers/pinctrl/freescale/pinctrl-imx.c | 5 ++++- drivers/pinctrl/freescale/pinctrl-imx.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-)
drivers/pinctrl/freescale/pinctrl-imx.c +4 -1
@@ -542,6 +542,9 @@ static int imx_pinctrl_parse_groups(struct device_node *np,struct imx_pin_reg *pin_reg;struct imx_pin *pin = &grp->pins[i]; +if (!(info->flags &ZERO_OFFSET_VALID ) && !mux_reg) + mux_reg =-1 ; +if (info->flags &SHARE_MUX_CONF_REG ) { conf_reg = mux_reg; }else {
@@ -550,7 +553,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np, conf_reg =-1 ; } - pin_id = mux_reg ? mux_reg /4 : conf_reg /4 ; + pin_id = (mux_reg !=-1 ) ? mux_reg /4 : conf_reg /4 ; pin_reg = &info->pin_regs[pin_id]; pin->pin = pin_id; grp->pin_ids[i] = pin_id;
drivers/pinctrl/freescale/pinctrl-imx.h +1 -0
@@ -85,6 +85,7 @@ struct imx_pinctrl_soc_info { };#define SHARE_MUX_CONF_REG 0x1 +#define ZERO_OFFSET_VALID 0x2#define NO_MUX 0x0#define NO_PAD 0x0
Signature · 1 line
2.1.4
PATCH v7 5/7 pinctrl: freescale: imx: add shared input select reg support
In reply to Adrian Alonso- Add shared input select register support
- imx7d has two iomux controllers iomuxc and iomuxc-lpsr which share select_input register for daisy chain settings
---
Changes for V2: Resend
Changes for V3:
- Use of_parse_phandle instead of of_get_child_by_name to get input select base register address
Changes for V4: Resend
Changes for V5:
- Remove SHARE_INPUT_SELECT_REG flag
- Use fsl,input-sel to check if shared input select register support is used
Changes for V6: Resend
Changes for V7: Resend
drivers/pinctrl/freescale/pinctrl-imx.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-)
drivers/pinctrl/freescale/pinctrl-imx.c +27 -1
@@ -18,6 +18,7 @@#include <linux/module.h> #include <linux/of.h> #include <linux/of_device.h> +#include <linux/of_address.h> #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h>
@@ -39,6 +40,7 @@ struct imx_pinctrl {struct device *dev;struct pinctrl_dev *pctl;void __iomem *base; +void __iomem *input_sel_base;const struct imx_pinctrl_soc_info *info; };
@@ -254,7 +256,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,* Regular select input register can never be at offset * 0, and we only print register value for regular case. */ -writel (pin->input_val, ipctl->base + pin->input_reg); +if (ipctl->input_sel_base) +writel (pin->input_val, ipctl->input_sel_base + + pin->input_reg); +else +writel (pin->input_val, ipctl->base + + pin->input_reg);dev_dbg (ipctl->dev,"==>select_input: offset 0x%x val 0x%x\n" , pin->input_reg, pin->input_val);
@@ -685,6 +692,8 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,int imx_pinctrl_probe (struct platform_device *pdev,struct imx_pinctrl_soc_info *info) { +struct device_node *dev_np = pdev->dev.of_node; +struct device_node *np;struct imx_pinctrl *ipctl;struct resource *res;int ret, i;
@@ -715,6 +724,23 @@ int imx_pinctrl_probe(struct platform_device *pdev,if (IS_ERR (ipctl->base))return PTR_ERR (ipctl->base); +if (of_property_read_bool (dev_np,"fsl,input-sel" )) { + np =of_parse_phandle (dev_np,"fsl,input-sel" ,0 ); +if (np) { + ipctl->input_sel_base =of_iomap (np,0 ); +if (IS_ERR (ipctl->input_sel_base)) { +of_node_put (np); +dev_err (&pdev->dev, +"iomuxc input select base address not found\n" ); +return PTR_ERR (ipctl->input_sel_base); + } + }else { +dev_err (&pdev->dev,"iomuxc fsl,input-sel property not found\n" ); +return -EINVAL ; + } +of_node_put (np); + } + imx_pinctrl_desc.name =dev_name (&pdev->dev); imx_pinctrl_desc.pins = info->pins; imx_pinctrl_desc.npins = info->npins;
Signature · 1 line
2.1.4
PATCH v7 6/7 pinctrl: freescale: imx7d: support iomux lpsr controller
In reply to Adrian AlonsoiMX7D has two iomuxc controllers, iomuxc controller similar as previous iMX SoC generation and iomuxc-lpsr which provides low power state rentetion capabilities on gpios that are part of iomuxc-lpsr
Add iomuxc-lpsr gpio group id's
---
Changes for V2: Add imx7d_lpsr_pads enums Changes for V3: Resend
Changes for V4: Resend
Changes for V5: Remove flags SHARE_INPUT_SELECT_REG and
ZERO_OFFSET_VALID.
Changes for V6: Restore ZERO_OFFSET_VALID flag. Changes for V7: Resend
drivers/pinctrl/freescale/pinctrl-imx7d.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
drivers/pinctrl/freescale/pinctrl-imx7d.c +30 -0
@@ -174,6 +174,17 @@ enum imx7d_pads { MX7D_PAD_ENET1_COL = 154, }; +enum imx7d_lpsr_pads { +MX7D_PAD_GPIO1_IO00 =0 , +MX7D_PAD_GPIO1_IO01 =1 , +MX7D_PAD_GPIO1_IO02 =2 , +MX7D_PAD_GPIO1_IO03 =3 , +MX7D_PAD_GPIO1_IO04 =4 , +MX7D_PAD_GPIO1_IO05 =5 , +MX7D_PAD_GPIO1_IO06 =6 , +MX7D_PAD_GPIO1_IO07 =7 , +}; +/* Pad names for the pinmux subsystem */ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {IMX_PINCTRL_PIN (MX7D_PAD_RESERVE0 ),
@@ -333,13 +344,32 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL), }; +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = { +IMX_PINCTRL_PIN (MX7D_PAD_GPIO1_IO00 ), +IMX_PINCTRL_PIN (MX7D_PAD_GPIO1_IO01 ), +IMX_PINCTRL_PIN (MX7D_PAD_GPIO1_IO02 ), +IMX_PINCTRL_PIN (MX7D_PAD_GPIO1_IO03 ), +IMX_PINCTRL_PIN (MX7D_PAD_GPIO1_IO04 ), +IMX_PINCTRL_PIN (MX7D_PAD_GPIO1_IO05 ), +IMX_PINCTRL_PIN (MX7D_PAD_GPIO1_IO06 ), +IMX_PINCTRL_PIN (MX7D_PAD_GPIO1_IO07 ), +}; +static struct imx_pinctrl_soc_info imx7d_pinctrl_info = { .pins = imx7d_pinctrl_pads, .npins =ARRAY_SIZE (imx7d_pinctrl_pads), }; +static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = { + .pins = imx7d_lpsr_pinctrl_pads, + .npins =ARRAY_SIZE (imx7d_lpsr_pinctrl_pads), + .flags =ZERO_OFFSET_VALID , +}; +static struct of_device_id imx7d_pinctrl_of_match[] = { { .compatible ="fsl,imx7d-iomuxc" , .data = &imx7d_pinctrl_info, }, + { .compatible ="fsl,imx7d-iomuxc-lpsr" , .data = &imx7d_lpsr_pinctrl_info }, {/* sentinel */ } };
Signature · 1 line
2.1.4
PATCH v7 7/7 pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings
In reply to Adrian AlonsoAdd iomuxc-lpsr devicetree bindings documentation Provide documentation context as well an example on pheriperals that could use pad from either iomuxc controller supported by iMX7D SoC
---
Changes for V2: New patch on imx7d iomuxc-lpsr patch series Changes for V3: Add shared input select register notes Changes for V4: Resend
Changes for V5:
- Fix spell error
- Remove references of SHARE_INPUT_SELECT_REG flag Changes for V6: Resend
Changes for v7: Resend
.../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 63 +++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +62 -1
@@ -1,16 +1,42 @@ * Freescale i.MX7 Dual IOMUX Controller +iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar +as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low +power state retention capabilities on gpios that are part of iomuxc-lpsr +(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for +mux and pad control settings, it shares the input select register from main +iomuxc controller for daisy chain settings, the fsl,input-sel property extends +fsl,imx-pinctrl driver to support iomuxc-lpsr controller. + +iomuxc_lpsr: iomuxc-lpsr at 302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; +}; + +iomuxc: iomuxc at 30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; +}; + +Pheriparials using pads from iomuxc-lpsr support low state retention power +state, under LPSR mode GPIO's state of pads are retain. + Please refer to fsl,imx-pinctrl.txt in this directory for common binding part and usage. Required properties: -- compatible: "fsl,imx7d-iomuxc" +- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or + "fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller. - fsl,pins: each entry consists of 6 integers and represents the mux and config setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val input_val> are specified using a PIN_FUNC_ID macro, which can be found in imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual Reference Manual for detailed CONFIG settings. +- fsl,input-sel: required property for iomuxc-lpsr controller, this property is + a phandle for main iomuxc controller which shares the input select register for + daisy chain settings. CONFIG bits definition: PAD_CTL_PUS_100K_DOWN (0 << 5)
@@ -25,3 +51,38 @@ PAD_CTL_DSE_X1 (0 << 0) PAD_CTL_DSE_X2 (1 << 0) PAD_CTL_DSE_X3 (2 << 0) PAD_CTL_DSE_X4 (3 << 0) + +Examples: +While iomuxc-lpsr is intended to be used by dedicated peripherals to take +advantages of LPSR power mode, is also possible that an IP to use pads from +any of the iomux controllers. For example the I2C1 IP can use SCL pad from +iomuxc-lpsr controller and SDA pad from iomuxc controller as: + +i2c1: i2c@30a20000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>; + status = "okay"; +}; + +iomuxc-lpsr at 302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f + >; + }; +}; + +iomuxc at 30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; +};
Signature · 1 line
2.1.4
PATCH v7 7/7 pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings
Quoted 93 lines · Adrian Alonso
Add iomuxc-lpsr devicetree bindings documentation Provide documentation context as well an example on pheriperals that could use pad from either iomuxc controller supported by iMX7D SoC
Signed-off-by Adrian Alonso <[email protected]>---
Changes for V2: New patch on imx7d iomuxc-lpsr patch series Changes for V3: Add shared input select register notes Changes for V4: Resend
Changes for V5:
- Fix spell error
- Remove references ofSHARE_INPUT_SELECT_REGflag Changes for V6: Resend
Changes for v7: Resend.../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 63 +++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +49
-1@@ -1,16 +1,42 @@ * Freescale i.MX7 Dual IOMUX Controller +iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar +as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low +power state retention capabilities on gpios that are part of iomuxc-lpsr +(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for +mux and pad control settings, it shares the input select register from main +iomuxc controller for daisy chain settings, the fsl,input-sel property extends +fsl,imx-pinctrl driver to support iomuxc-lpsr controller. + +iomuxc_lpsr: iomuxc-lpsr at 302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; +}; + +iomuxc: iomuxc at 30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; +}; + +Pheriparials using pads from iomuxc-lpsr support low state retention power +state, under LPSR mode GPIO's state of pads are retain. + Please refer to fsl,imx-pinctrl.txt in this directory for common binding part and usage. Required properties: -- compatible: "fsl,imx7d-iomuxc" +- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or + "fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller. - fsl,pins: each entry consists of 6 integers and represents the mux and config setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val input_val> are specified using a PIN_FUNC_ID macro, which can be found in imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual Reference Manual for detailed CONFIG settings. +- fsl,input-sel: required property for iomuxc-lpsr controller, this property is + a phandle for main iomuxc controller which shares the input select register for + daisy chain settings. CONFIG bits definition: PAD_CTL_PUS_100K_DOWN (0 << 5)@@ -25,3 +51,38 @@ PAD_CTL_DSE_X1 (0 << 0) PAD_CTL_DSE_X2 (1 << 0) PAD_CTL_DSE_X3 (2 << 0) PAD_CTL_DSE_X4 (3 << 0) + +Examples: +While iomuxc-lpsr is intended to be used by dedicated peripherals to take +advantages of LPSR power mode, is also possible that an IP to use pads from +any of the iomux controllers. For example the I2C1 IP can use SCL pad from +iomuxc-lpsr controller and SDA pad from iomuxc controller as: + +i2c1: i2c at 30a20000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>; + status = "okay"; +}; + +iomuxc-lpsr at 302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f + >;
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt PAD_CTL_DSE_X1 (0 << 0) · line 85
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +10
-0+ }; +}; + +iomuxc at 30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
I'm not sure how many times I should repeat: you should set up a I2C1_SDA instead of two I2C1_SCL in this example.
Shawn
Quoted 6 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +3
-0+ >; + }; +};Signature · 1 line
2.1.4
PATCH v7 7/7 pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings
Quoted 126 lines
-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Tuesday, September 29, 2015 9:04 PM
To: Alonso Lazcano Adrian-B38018 <[email protected]>
Cc: linux-arm-kernel at lists.infradead.org; shawn.guo at linaro.org; linus.walleij at linaro.org; lznuaa at gmail.com; linux-gpio at vger.kernel.org; devicetree at vger.kernel.org; kernel at pengutronix.de; robh+dt at kernel.org; Huang Yongcai-B20788 <[email protected]>; Li Frank-B20596 <[email protected]>; Gong Yibin-B38343 <[email protected]>; Garg Nitin-B37173 <[email protected]>
Subject: Re: [PATCH v7 7/7] pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindingsQuoted 23 lines · Adrian Alonso
Add iomuxc-lpsr devicetree bindings documentation Provide documentation context as well an example on pheriperals that could use pad from either iomuxc controller supported by iMX7D SoC
Signed-off-by Adrian Alonso <[email protected]>---
Changes for V2: New patch on imx7d iomuxc-lpsr patch series Changes for V3: Add shared input select register notes Changes for V4: Resend Changes for V5:
- Fix spell error
- Remove references ofSHARE_INPUT_SELECT_REGflag Changes for V6:
Resend Changes for v7: Resend.../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 63 +++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-)diff --git
a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txtb/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txtindex 8bbf25d..aae069f 100644Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt line 9
Quoted 9 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +7
-0@@ -1,16 +1,42 @@ * Freescale i.MX7 Dual IOMUX Controller +iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is +similar as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr +which provides low power state retention capabilities on gpios that +are part of iomuxc-lpsr (GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr +provides its own set of registers for mux and pad control settings, +it shares the input select register from main iomuxc controller for +daisy chain settings, the fsl,input-sel property extends fsl,imx-pinctrl driverto support iomuxc-lpsr controller.
Quoted 18 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +15
-0+ +iomuxc_lpsr: iomuxc-lpsr at 302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; +}; + +iomuxc: iomuxc at 30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; +}; + +Pheriparials using pads from iomuxc-lpsr support low state retention +power state, under LPSR mode GPIO's state of pads are retain. + Please refer to fsl,imx-pinctrl.txt in this directory for commonbinding part and usage.
Quoted 6 lines
Required properties:
-- compatible: "fsl,imx7d-iomuxc"+- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or + "fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller.- fsl,pins: each entry consists of 6 integers and represents the mux and config setting for one pin. The first 5 integers <
mux_regconf_reginput_reg
mux_valQuoted 2 lines
input_val> are specified using aPIN_FUNC_IDmacro, which can be found inimx7d-pinfunc.hunder device tree source folder. The last integer CONFIGis
Quoted 11 lines
the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual Reference Manual for detailed CONFIG settings.
+- fsl,input-sel: required property for iomuxc-lpsr controller, thisDocumentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +4
-0+property is + a phandle for main iomuxc controller which shares the input select +register for + daisy chain settings. CONFIG bits definition: PAD_CTL_PUS_100K_DOWN (0 << 5)Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt PAD_CTL_DSE_X1 (0 << 0) · line 59
Quoted 9 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +6
-0@@ -25,3 +51,38 @@ PAD_CTL_DSE_X1 (0 << 0) PAD_CTL_DSE_X2 (1 << 0) PAD_CTL_DSE_X3 (2 << 0) PAD_CTL_DSE_X4 (3 << 0) + +Examples: +While iomuxc-lpsr is intended to be used by dedicated peripherals to +take advantages of LPSR power mode, is also possible that an IP to +use pads from any of the iomux controllers. For example the I2C1 IP +can use SCL pad from iomuxc-lpsr controller and SDA pad from iomuxccontroller as:
Quoted 16 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +16
-0+ +i2c1: i2c at 30a20000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>; + status = "okay"; +}; + +iomuxc-lpsr at 302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f + >;Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt PAD_CTL_DSE_X1 (0 << 0) · line 85
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +10
-0+ }; +}; + +iomuxc at 30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007fI'm not sure how many times I should repeat: you should set up a
I2C1_SDAinstead of twoI2C1_SCLin this example.
Quoted 1 line
Shawn
[Adrian] Sorry about that, fixed in new patch series, thanks :)
Quoted 7 lines
Quoted 7 lines
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +3
-1+ >; + }; +}; --2.1.4
PATCH v7 1/7 ARM: dts: imx: imx7d-sbd remove fixed can2-3v3 regulator
In reply to Adrian AlonsoQuoted 4 lines · Adrian Alonso
Remove incorrect can2-3v3 fixed regulator, imx7d-sdb doesn't have a dedicated can2 fixed regulator instead it shares
PERI_3V3fixed regulator (RT8070ZS) which is enabled by default (hardwired) from pmic pfuze3000NVCC_3V3power rail.
@Frank, can you please confirm it?
Quoted 2 lines
Signed-off-by Adrian Alonso <[email protected]>
Please stop sending patch to shawn.guo at linaro.org, and shawnguo at kernel.org is good enough.
Quoted 2 lines
---
Changes for V7: New patch in series
I do not understand why the patch has to be included in this series.
Shawn
Quoted 29 lines
arch/arm/boot/dts/imx7d-sdb.dts | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-)arch/arm/boot/dts/imx7d-sdb.dts +1
-10@@ -78,16 +78,7 @@ enable-active-high; }; - reg_can2_3v3: regulator at 2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - reg_vref_1v8: regulator at 3 { + reg_vref_1v8: regulator at 2 { compatible = "regulator-fixed"; reg = <3>; regulator-name = "vref-1v8";Signature · 1 line
2.1.4
PATCH v7 1/7 ARM: dts: imx: imx7d-sbd remove fixed can2-3v3 regulator
Quoted 7 lines · Shawn Guo
Quoted 4 lines · Adrian Alonso
Remove incorrect can2-3v3 fixed regulator, imx7d-sdb doesn't have a dedicated can2 fixed regulator instead it shares
PERI_3V3fixed regulator (RT8070ZS) which is enabled by default (hardwired) from pmic pfuze3000NVCC_3V3power rail.@Frank, can you please confirm it?
@Aisheng,
Can you confirm it?
best regards
Frank Li
Quoted 43 lines
Quoted 3 lines
Signed-off-by Adrian Alonso <[email protected]>Please stop sending patch to shawn.guo at linaro.org, and shawnguo at kernel.org is good enough.
Quoted 2 lines
---
Changes for V7: New patch in seriesI do not understand why the patch has to be included in this series.
Shawn
Quoted 29 lines
arch/arm/boot/dts/imx7d-sdb.dts | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-)arch/arm/boot/dts/imx7d-sdb.dts +1
-11@@ -78,16 +78,7 @@ enable-active-high; }; - reg_can2_3v3: regulator at 2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - reg_vref_1v8: regulator at 3 { + reg_vref_1v8: regulator at 2 { compatible = "regulator-fixed"; reg = <3>; regulator-name = "vref-1v8"; --2.1.4
PATCH v7 1/7 ARM: dts: imx: imx7d-sbd remove fixed can2-3v3 regulator
In reply to Adrian AlonsoQuoted 9 lines · Adrian Alonso
Remove incorrect can2-3v3 fixed regulator, imx7d-sdb doesn't have a dedicated can2 fixed regulator instead it shares
PERI_3V3fixed regulator (RT8070ZS) which is enabled by default (hardwired) from pmic pfuze3000NVCC_3V3power rail.Signed-off-by Adrian Alonso <[email protected]>---
Changes for V7: New patch in series
It is a correct regulator here, but i have to admit that it's a bit confusing. Here the regulator is an abstract regulator which is actually used to control CAN
transceiver STBY signals, it is introduced by below patch:
commit b7c4114b07bbacfe0aee1d04ad1ade9e42309620
Author: Fabio Estevam <[email protected]> Date: Mon Jun 10 23:12:57 2013 -0300
can: flexcan: Use a regulator to control the CAN transceiver
Instead of using a GPIO to turn on/off the CAN transceiver, it is better to use a regulator as some systems may use a PMIC to power the CAN transceiver.
Quoted 1 line
From the commit messages, it should be likely to control the
transceiver external suppy,
not control signals, but it does do that unproper work currently.
Besides the unproperly handling control signals, this solution also can't handle multiple CAN transceiver control signals ways.
I was trying to write a common transceiver driver to handling this issue. But get interrupted by a few other FSL official works, will resume soon.
I would suggest keep the regulator first until the new solution got in.
Regards
Dong Aisheng
Quoted 33 lines
arch/arm/boot/dts/imx7d-sdb.dts | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-)arch/arm/boot/dts/imx7d-sdb.dts +1
-11@@ -78,16 +78,7 @@ enable-active-high; }; - reg_can2_3v3: regulator at 2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - reg_vref_1v8: regulator at 3 { + reg_vref_1v8: regulator at 2 { compatible = "regulator-fixed"; reg = <3>; regulator-name = "vref-1v8"; --2.1.4
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PATCH v7 1/7 ARM: dts: imx: imx7d-sbd remove fixed can2-3v3 regulator
Quoted 28 lines · Dong Aisheng
Quoted 9 lines · Adrian Alonso
Remove incorrect can2-3v3 fixed regulator, imx7d-sdb doesn't have a dedicated can2 fixed regulator instead it shares
PERI_3V3fixed regulator (RT8070ZS) which is enabled by default (hardwired) from pmic pfuze3000NVCC_3V3power rail.Signed-off-by Adrian Alonso <[email protected]>---
Changes for V7: New patch in seriesIt is a correct regulator here, but i have to admit that it's a bit confusing. Here the regulator is an abstract regulator which is actually used to control CAN
transceiver STBY signals, it is introduced by below patch:
commitb7c4114b07bbacfe0aee1d04ad1ade9e42309620Author: Fabio Estevam <[email protected]> Date: Mon Jun 10 23:12:57 2013 -0300can: flexcan: Use a regulator to control the CAN transceiver
Instead of using a GPIO to turn on/off the CAN transceiver, it is better to use a regulator as some systems may use a PMIC to power the CAN transceiver.
Acked-by Shawn Guo <[email protected]>Signed-off-by Fabio Estevam <[email protected]>Signed-off-by Marc Kleine-Budde <[email protected]>
Quoted 6 lines
From the commit messages, it should be likely to control the transceiver external suppy,
not control signals, but it does do that unproper work currently.Besides the unproperly handling control signals, this solution also can't handle multiple CAN transceiver control signals ways.
You can chain several transceivers together if you need to control more than one GPIO line.
Quoted 2 lines
I was trying to write a common transceiver driver to handling this issue. But get interrupted by a few other FSL official works, will resume soon.
Have a look at drivers/phy.
Quoted 1 line
I would suggest keep the regulator first until the new solution got in.
Marc
Signature · 12 lines
Pengutronix e.K. | Marc Kleine-Budde | Industrial Linux Solutions | Phone: +49-231-2826-924 | Vertretung West/Dortmund | Fax: +49-5121-206917-5555 | Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de | -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 455 bytes Desc: OpenPGP digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20151013/405f4bf0/attachment.sig>