arm64: renesas: r8a7795 dtsi: Add all SCIF nodes
Subsystems (4)
Magnus Damm
maintainerPATCH v10 4/7 arm64: renesas: r8a7795 dtsi: Add all SCIF nodes
From: Geert Uytterhoeven <[email protected]>
Add the device nodes for all R-Car H3 SCIF serial ports, incl. clocks, clock domain, and dma properties.
---
Changes since V9: (Magnus Damm <[email protected]>)
- Added SCIF2 DMA bits again
- Converted DT nodes for MSTP to MSSR, adjusted r8a7795-clock.h
- Include clock-output-names
Changes since V8: (Magnus Damm <[email protected]>)
- Dropped SCIF2 DMA bits - thanks Laurent!
- Changed name of mstp2 and mstp3 nodes - thanks Geert!
- Added Acked-by from Laurent
Changes since V7: (Magnus Damm <[email protected]>)
- Folded together above SCIF2 patches
- Added SCIF2 DMA bits
- Got rid of clock-output-names
- Replaced renesas,clock-indices with clock-indices
Based on:
[PATCH 9/25] arm64: renesas: r8a7795: Add SCIF2 support [PATCH 1/6] arm64: renesas: r8a7795 dtsi: Mark scif2 disabled [PATCH 3/6] arm64: renesas: r8a7795 dtsi: Add all SCIF nodes
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 109 +++++++++++++++++++++++++++++ include/dt-bindings/clock/r8a7795-clock.h | 6 + 2 files changed, 115 insertions(+)
arch/arm64/boot/dts/renesas/r8a7795.dtsi +106 -0
@@ -231,6 +231,11 @@ }; cpg_clocks: cpg_clocks@e6150000 { + #address-cells = <2>; + #size-cells = <2>; + #clock-cells = <1>; + ranges; + compatible = "renesas,r8a7795-cpg-clocks", "renesas,rcar-gen3-cpg-clocks"; reg = <0 0xe6150000 0 0x1000>;
@@ -243,6 +248,38 @@ clock-output-names = "main", "pll0", "pll1", "pll2", "pll3", "pll4"; #power-domain-cells = <0>; + + /* Module Standby and Software Reset */ + mssr: mssr@e6150130 { + compatible + "renesas,r8a7795-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + #clock-cells = <1>; + clocks + /* MSTP2 */ + <&s3d4_clk>, <&s3d4_clk>, + <&s3d4_clk>, <&s3d4_clk>, + <&s3d4_clk>, + /* MSTP3 */ + <&s3d4_clk>; + clock-indices = < + /* MSTP2 */ + R8A7795_CLK_SCIF5 + R8A7795_CLK_SCIF4 + R8A7795_CLK_SCIF3 + R8A7795_CLK_SCIF1 + R8A7795_CLK_SCIF0 + /* MSTP3 */ + R8A7795_CLK_SCIF2 + >; + clock-output-names + /* MSTP2 */ + "scif5", "scif4", "scif3", + "scif1", "scif0", + /* MSTP3 */ + "scif2"; + #reset-cells = <1>; + }; }; };
@@ -257,5 +294,77 @@ dmac2: dma-controller@e7310000 { /* Empty node for now */ }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mssr R8A7795_CLK_SCIF0>; + clock-names = "sci_ick"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mssr R8A7795_CLK_SCIF1>; + clock-names = "sci_ick"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mssr R8A7795_CLK_SCIF2>; + clock-names = "sci_ick"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mssr R8A7795_CLK_SCIF3>; + clock-names = "sci_ick"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mssr R8A7795_CLK_SCIF4>; + clock-names = "sci_ick"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mssr R8A7795_CLK_SCIF5>; + clock-names = "sci_ick"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; }; };
include/dt-bindings/clock/r8a7795-clock.h +6 -0
@@ -22,8 +22,14 @@/* MSTP1 */ /* MSTP2 */ +#define R8A7795_CLK_SCIF5 202 +#define R8A7795_CLK_SCIF4 203 +#define R8A7795_CLK_SCIF3 204 +#define R8A7795_CLK_SCIF1 206 +#define R8A7795_CLK_SCIF0 207/* MSTP3 */ +#define R8A7795_CLK_SCIF2 210/* MSTP5 */
Quoted 4 lines · Magnus Damm
include/dt-bindings/clock/r8a7795-clock.h 2015-10-01 19:24:51.200513000 +0900 renamed from include/dt-bindings/clock/r8a7795-clock.h +0
-0@@ -22,8 +22,14 @@ /* MSTP1 */
include/dt-bindings/clock/r8a7795-clock.h 2015-10-01 19:24:51.200513000 +0900 line 32
Quoted 10 lines
include/dt-bindings/clock/r8a7795-clock.h 2015-10-01 19:24:51.200513000 +0900 renamed from include/dt-bindings/clock/r8a7795-clock.h +6
-0/* MSTP2 */ +#define R8A7795_CLK_SCIF5 202 +#define R8A7795_CLK_SCIF4 203 +#define R8A7795_CLK_SCIF3 204 +#define R8A7795_CLK_SCIF1 206 +#define R8A7795_CLK_SCIF0 207 /* MSTP3 */ +#define R8A7795_CLK_SCIF2 210
310
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Quoted 13 lines · Geert Uytterhoeven
Quoted 12 lines · Magnus Damm
include/dt-bindings/clock/r8a7795-clock.h 2015-10-01 19:24:51.200513000 +0900 renamed from include/dt-bindings/clock/r8a7795-clock.h +5
-0@@ -22,8 +22,14 @@ /* MSTP1 */ /* MSTP2 */ +#define R8A7795_CLK_SCIF5 202 +#define R8A7795_CLK_SCIF4 203 +#define R8A7795_CLK_SCIF3 204 +#define R8A7795_CLK_SCIF1 206 +#define R8A7795_CLK_SCIF0 207
Quoted 4 lines
include/dt-bindings/clock/r8a7795-clock.h 2015-10-01 19:24:51.200513000 +0900 line 32
Quoted 2 lines
include/dt-bindings/clock/r8a7795-clock.h 2015-10-01 19:24:51.200513000 +0900 renamed from include/dt-bindings/clock/r8a7795-clock.h +1
-0/* MSTP3 */ +#define R8A7795_CLK_SCIF2 210310
Thanks, I will fix that.
I plan to wait a little to accumulate more changes. But if for some reason you need this in a hurry I can push an updated topic branch ASAP.
Hi Simon,
Quoted 19 lines · Simon Horman
Quoted 13 lines · Geert Uytterhoeven
Quoted 12 lines · Magnus Damm
include/dt-bindings/clock/r8a7795-clock.h 2015-10-01 19:24:51.200513000 +0900 renamed from include/dt-bindings/clock/r8a7795-clock.h +5
-0@@ -22,8 +22,14 @@ /* MSTP1 */ /* MSTP2 */ +#define R8A7795_CLK_SCIF5 202 +#define R8A7795_CLK_SCIF4 203 +#define R8A7795_CLK_SCIF3 204 +#define R8A7795_CLK_SCIF1 206 +#define R8A7795_CLK_SCIF0 207Quoted 4 lines
include/dt-bindings/clock/r8a7795-clock.h 2015-10-01 19:24:51.200513000 +0900 line 32
Quoted 2 lines
include/dt-bindings/clock/r8a7795-clock.h 2015-10-01 19:24:51.200513000 +0900 renamed from include/dt-bindings/clock/r8a7795-clock.h +1
-0/* MSTP3 */ +#define R8A7795_CLK_SCIF2 210310
Quoted 5 lines
Thanks, I will fix that.
I plan to wait a little to accumulate more changes. But if for some reason you need this in a hurry I can push an updated topic branch ASAP.
Given how close we are to leaving for ELCE, I think we can live with it.
The correct clock will have been enabled by the boot loader anyway. MSTP210 is MSIOF1, so no animals will be hurt by accidentally touching that clock.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Quoted 22 lines · Geert Uytterhoeven
Hi Simon,
Quoted 19 lines · Simon Horman
Quoted 17 lines · Geert Uytterhoeven
Quoted 4 lines · Magnus Damm
include/dt-bindings/clock/r8a7795-clock.h 2015-10-01 19:24:51.200513000 +0900 renamed from include/dt-bindings/clock/r8a7795-clock.h +0
-0@@ -22,8 +22,14 @@ /* MSTP1 */include/dt-bindings/clock/r8a7795-clock.h 2015-10-01 19:24:51.200513000 +0900 line 32
Quoted 10 lines
include/dt-bindings/clock/r8a7795-clock.h 2015-10-01 19:24:51.200513000 +0900 renamed from include/dt-bindings/clock/r8a7795-clock.h +6
-0/* MSTP2 */ +#define R8A7795_CLK_SCIF5 202 +#define R8A7795_CLK_SCIF4 203 +#define R8A7795_CLK_SCIF3 204 +#define R8A7795_CLK_SCIF1 206 +#define R8A7795_CLK_SCIF0 207 /* MSTP3 */ +#define R8A7795_CLK_SCIF2 210310
Quoted 7 lines
Quoted 5 lines
Thanks, I will fix that.
I plan to wait a little to accumulate more changes. But if for some reason you need this in a hurry I can push an updated topic branch ASAP.
Given how close we are to leaving for ELCE, I think we can live with it.
As I am rebasing other branches I have pushed the above in topic/arm64-rcar-gen3-v10.1.
Quoted 3 lines
The correct clock will have been enabled by the boot loader anyway. MSTP210 is MSIOF1, so no animals will be hurt by accidentally touching that clock.
:)