DRA7 Timer12 Support

Hi Tony,

The DRA7 Timer12 is completely missing from the kernel. This series adds the support for it, so that all the Timers on DRA7 are represented in the kernel. Timer12 is a special Timer, and is not available for kernel on HS devices, very much similar to the equivalent timer on OMAP3.

Patch 1 is a bit debatable, as I am not entirely sure if the clk API used are acceptable outside the drivers/clk folders. It keeps intact the omap_dm_timer_set_source() API though, and allows it to handle the non-configurability of Timer12 parent within that API. The need for this API is questionable, I am not a big fan as the dmtimer code blindly tries to set the source of every requested API to OMAP_TIMER_SRC_32_KHZ, and then the requestors would have to reset the proper parent source again. It also supports configuring only one of 3 parents (which are valid when added originally for the then SoCs), requiring specific clock aliases to work across different SoCs, but the DRA7 SoC does have more than 3 configurable clock parents, and the indexes may not necessarily match for different timers on different SoCs. Patch 1 won't be needed if we can kill the omap_dm_timer_set_source() API.

Patches baselined on 4.3-rc3, but should apply just fine on -rc1 as well.

regards
Suman

Suman Anna (4):
ARM: OMAP: dmtimer: check for fixed timers during config
ARM: OMAP2+: timer: Remove secure timer for DRA7xx devices
ARM: dts: DRA7: Add timer12 node
ARM: DRA7: hwmod: Add data for GPTimer 12

 arch/arm/boot/dts/dra7.dtsi               | 10 +++++++++
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 36 +++++++++++++++++++++++++++++--
 arch/arm/mach-omap2/timer.c               |  6 +++---
 arch/arm/plat-omap/dmtimer.c              |  5 +++++
 4 files changed, 52 insertions(+), 5 deletions(-)

2.6.0

The omap_dm_timer_set_source() function provides a means for client users to configure the mux parent for a GPTimer's functional clock. However, not all timers are configurable (Eg: Timer12 on DRA7 is fed by an internal 32k oscillator clock, and does not have configurable parent clocks). So, check for such cases and proceed with out throwing an error.

---
 arch/arm/plat-omap/dmtimer.c | 5 +++++
 1 file changed, 5 insertions(+)

index 8ca94d379bc3..25693e722f1f 100644
@@ -36,6 +36,7 @@
  */
 
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/device.h>

@@ -504,6 +505,10 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 	if (IS_ERR(timer->fclk))
 		return -EINVAL;
 
+	/* Check if the clock has parents if not no point checking */
+	if (!clk_hw_get_num_parents(__clk_get_hw(timer->fclk)))
+		return 0;
+
 	switch (source) {
 	case OMAP_TIMER_SRC_SYS_CLK:
 		parent_name = "timer_sys_ck";

2.6.0

Tony,

CONFIG_COMMON_CLK is not defined for OMAP1. So, are you ok if I enclose this within #ifdef CONFIG_COMMON_CLK?

regards
Suman

Yes, or maybe you can just clk_get_rate() on the 32k oscillator?

Boards with no 32k oscillator should set the rate for that 0 zero.

Regards,

Tony

Well, this API is about setting the timer clk's mux source, and not really dealing with the clk rate or just setting it to the 32k oscillator. A 32k is usually one of the mux parents (if the timer has them). If there is a way to find if the clk is a mux clock, then that check would be ideal. But since no such thing exists, so I will go ahead and fix this by adding the #ifdef check.

regards
Suman

Timer 12 on DRA7 SoCs is reserved for secure usage on high-secure (HS) devices. The timer cannot be used by the kernel on HS devices, but is available on regular general purpose (GP) devices. This is similar to the behavior on OMAP3 devices, so extend the logic used in commit ad24bde8f102 ("ARM: OMAP3: Dynamically disable secure timer nodes for secure devices") to remove the secure timer on DRA7xx SoCs at run-time based on the SoC device type.

---
 arch/arm/mach-omap2/timer.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

index a55655127ef2..1e346aa0a687 100644
@@ -193,8 +193,8 @@ static struct device_node * __init omap_get_timer_dt(const struct of_device_id *
 /**
  * omap_dmtimer_init - initialisation function when device tree is used
  *
- * For secure OMAP3 devices, timers with device type "timer-secure" cannot
- * be used by the kernel as they are reserved. Therefore, to prevent the
+ * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure"
+ * cannot be used by the kernel as they are reserved. Therefore, to prevent the
  * kernel registering these devices remove them dynamically from the device
  * tree on boot.
  */

@@ -202,7 +202,7 @@ static void __init omap_dmtimer_init(void)
 {
 	struct device_node *np;
 
-	if (!cpu_is_omap34xx())
+	if (!cpu_is_omap34xx() && !soc_is_dra7xx())
 		return;
 
 	/* If we are a secure device, remove any secure timer nodes */

2.6.0

Add the DT node for Timer12 present on DRA7 family of SoCs. Timer12 is present in PD_WKUPAON power domain, and has the same capabilities as the other timers, except for the fact that it serves as a secure timer on HS devices and is clocked only from the secure 32K clock.

The node is marked disabled for now, and the kernel should refrain from using this secure timer on HS devices.

---
 arch/arm/boot/dts/dra7.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

index e289c706d27d..37d632dad576 100644
@@ -762,6 +762,16 @@
 			ti,hwmods = "timer11";
 		};
 
+		timer12: timer at 4ae20000 {
+			compatible = "ti,omap5430-timer";
+			reg = <0x4ae20000 0x80>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "timer12";
+			ti,timer-alwon;
+			ti,timer-secure;
+			status = "disabled";
+		};
+
 		timer13: timer at 48828000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48828000 0x80>;

2.6.0

Add the hwmod data for GPTimer 12. GPTimer 12 is present in WKUPAON power domain and is clocked from a secure 32K clock. GPTimer 12 serves as a secure timer on HS devices, but is available for kernel on regular GP devices.

The hwmod link is registered only on GP devices. The hwmod data also reused the existing timer class instead of reintroducing the identical dra7xx_timer_secure_sysc class which was dropped in commit edec17863362 ("ARM: DRA7: hwmod: Fix the hwmod class for GPTimer4").

---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 36 +++++++++++++++++++++++++++++--
 1 file changed, 34 insertions(+), 2 deletions(-)

index 562247bced49..37a10f87fbcd 100644
@@ -1929,6 +1929,20 @@ static struct omap_hwmod dra7xx_timer11_hwmod = {
 	},
 };
 
+/* timer12 */
+static struct omap_hwmod dra7xx_timer12_hwmod = {
+	.name		= "timer12",
+	.class		= &dra7xx_timer_hwmod_class,
+	.clkdm_name	= "wkupaon_clkdm",
+	.main_clk	= "secure_32k_clk_src_ck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
+		},
+	},
+};
+
 /* timer13 */
 static struct omap_hwmod dra7xx_timer13_hwmod = {
 	.name		= "timer13",

@@ -3135,6 +3149,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_wkup -> timer12 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
+	.master		= &dra7xx_l4_wkup_hwmod,
+	.slave		= &dra7xx_timer12_hwmod,
+	.clk		= "wkupaon_iclk_mux",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l4_per3 -> timer13 */
 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
 	.master		= &dra7xx_l4_per3_hwmod,

@@ -3429,6 +3451,13 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
 	NULL,
 };
 
+/* GP-only hwmod links */
+static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
+	&dra7xx_l4_wkup__timer12,
+	NULL,
+};
+
+/* SoC variant specific hwmod links */
 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
 	&dra7xx_l4_per3__usb_otg_ss4,
 	NULL,

@@ -3446,9 +3475,12 @@ int __init dra7xx_hwmod_init(void)
 	ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
 
 	if (!ret && soc_is_dra74x())
-		return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
+		ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
 	else if (!ret && soc_is_dra72x())
-		return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
+		ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
+
+	if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
+		ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
 
 	return ret;
 }

2.6.0