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arm64: perf: heterogeneous PMU support

PATCH Superseded Mark Rutland 4 participants 11 messages Oct 2, 2015 – Oct 8, 2015

Subsystems (5)
Device tree bindings perf events arm64 Arm/versatile express platform +1 more subsystems
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Mark Rutland

author maintainer
#0 lore raw

v4 cover arm64: perf: heterogeneous PMU support

This patch series moves the arm64 code over to the librified perf code now used by 32-bit arm, in the process gaining support for heterogeneous PMUs. Tailored support is then added for Cortex-A53 and Cortex-A57 as used in Juno systems.

With this series applied, perf can be used to monitor 64-bit systems with heterogeneous PMUs in an identical fashion to 32-bit systems, e.g.

$ perf stat -e armv8_cortex_a53/config=0x11/ -e armv8_cortex_a57/config=0x11/ ./a.out

Performance counter stats for './a.out':

         185250238 armv8_cortex_a53/config=0x11/                                    [55.34%]
         225006550 armv8_cortex_a57/config=0x11/                                    [43.96%]

       0.213953840 seconds time elapsed
$ perf stat -e cycles ./a.out

Performance counter stats for './a.out':

         830917902 cycles                    [64.60%]

       1.023141420 seconds time elapsed

Since v2 [1]:
* Rebase to v4.2-rc1
* Split MAINTAINERS changes
* Add arm64 perf code to MAINTAINERS entry
Since v3 [2]
* Drop patches which made it for v4.3-rc1
* Don't bother with pmuv3 renaming

Thanks,
Mark.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/350109.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/354287.html

Mark Rutland (6):
arm64: perf: move to shared arm_pmu framework
arm64: perf: add Cortex-A53 support
arm64: perf: add Cortex-A57 support
arm64: dts: juno: describe PMUs separately
MAINTAINERS: update ARM PMU profiling and debugging for arm64
MAINTAINERS: add myself as arm perf reviewer

 Documentation/devicetree/bindings/arm/pmu.txt |    2 +
 MAINTAINERS                                   |    9 +-
 arch/arm64/Kconfig                            |    8 +-
 arch/arm64/boot/dts/arm/juno-r1.dts           |   18 +-
 arch/arm64/boot/dts/arm/juno.dts              |   18 +-
 arch/arm64/include/asm/pmu.h                  |   83 --
 arch/arm64/kernel/perf_event.c                | 1068 +++++--------------------
 drivers/perf/Kconfig                          |    2 +-
 8 files changed, 241 insertions(+), 967 deletions(-)
 delete mode 100644 arch/arm64/include/asm/pmu.h
Signature · 1 line
1.9.1
author maintainer
#1 lore raw

PATCH v4 1/6 arm64: perf: move to shared arm_pmu framework

Now that the arm_pmu framework has been factored out to drivers/perf we can make use of it for arm64, gaining support for heterogeneous PMUs and unifying the two codebases before they diverge further.

The as yet unused PMU name for PMUv3 is changed to armv8_pmuv3, matching the style previously applied to the 32-bit PMUs.

Signed-off-by Mark Rutland <[email protected]>
Cc will Deacon <[email protected]>
---
 arch/arm64/Kconfig             |   8 +-
 arch/arm64/include/asm/pmu.h   |  83 ----
 arch/arm64/kernel/perf_event.c | 953 ++++-------------------------------------
 drivers/perf/Kconfig           |   2 +-
 4 files changed, 94 insertions(+), 952 deletions(-)
 delete mode 100644 arch/arm64/include/asm/pmu.h
arch/arm64/Kconfig +2 -6
index 7d95663..210d1143 100644
@@ -437,12 +437,8 @@ config HAVE_ARCH_PFN_VALID
 	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
 
 config HW_PERF_EVENTS
-	bool "Enable hardware performance counter support for perf events"
-	depends on PERF_EVENTS
-	default y
-	help
-	  Enable hardware performance counter support for perf events. If
-	  disabled, perf events will use software events only.
+	def_bool y
+	depends on ARM_PMU
 
 config SYS_SUPPORTS_HUGETLBFS
 	def_bool y
arch/arm64/include/asm/pmu.h deleted +0 -83

83 lines not on this page · raw message

arch/arm64/kernel/perf_event.c +91 -862

1,130 lines not on this page · raw message

drivers/perf/Kconfig +1 -1
index d9de36e..04e2653 100644
@@ -5,7 +5,7 @@
 menu "Performance monitor support"
 
 config ARM_PMU
-	depends on PERF_EVENTS && ARM
+	depends on PERF_EVENTS && (ARM || ARM64)
 	bool "ARM PMU framework"
 	default y
 	help
Signature · 1 line
1.9.1
author maintainer
#2 lore raw

PATCH v4 2/6 arm64: perf: add Cortex-A53 support

In reply to Mark Rutland

The Cortex-A53 PMU supports a few events outside of the required PMUv3 set that are rather useful.

This patch adds the event map data for said events.

Signed-off-by Mark Rutland <[email protected]>
Cc Will Deacon <[email protected]>
---
 Documentation/devicetree/bindings/arm/pmu.txt |  1 +
 arch/arm64/kernel/perf_event.c                | 64 ++++++++++++++++++++++++++-
 2 files changed, 63 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/arm/pmu.txt +1 -0
index 435251f..2e6737b 100644
@@ -8,6 +8,7 @@ Required properties:
 
 - compatible : should be one of
 	"arm,armv8-pmuv3"
+	"arm.cortex-a53-pmu"
 	"arm,cortex-a17-pmu"
 	"arm,cortex-a15-pmu"
 	"arm,cortex-a12-pmu"
arch/arm64/kernel/perf_event.c +62 -2

107 lines not on this page · raw message

Signature · 1 line
1.9.1
author maintainer
#3 lore raw

PATCH v4 3/6 arm64: perf: add Cortex-A57 support

In reply to Mark Rutland

The Cortex-A57 PMU supports a few events outside of the required PMUv3 set that are rather useful.

This patch adds the event map data for said events.

Signed-off-by Mark Rutland <[email protected]>
Cc Will Deacon <[email protected]>
---
 Documentation/devicetree/bindings/arm/pmu.txt |  1 +
 arch/arm64/kernel/perf_event.c                | 61 +++++++++++++++++++++++++++
 2 files changed, 62 insertions(+)
Documentation/devicetree/bindings/arm/pmu.txt +1 -0
index 2e6737b..4b7c3d9 100644
@@ -8,6 +8,7 @@ Required properties:
 
 - compatible : should be one of
 	"arm,armv8-pmuv3"
+	"arm.cortex-a57-pmu"
 	"arm.cortex-a53-pmu"
 	"arm,cortex-a17-pmu"
 	"arm,cortex-a15-pmu"
arch/arm64/kernel/perf_event.c +61 -0

94 lines not on this page · raw message

Signature · 1 line
1.9.1
author maintainer
#4 lore raw

PATCH v4 4/6 arm64: dts: juno: describe PMUs separately

In reply to Mark Rutland

The A57 and A53 PMUs in Juno support different events, so describe them separately in both the Juno and Juno R1 DTs.

Signed-off-by Mark Rutland <[email protected]>
Cc Liviu Dudau <[email protected]>
Cc Will Deacon <[email protected]>
---
 arch/arm64/boot/dts/arm/juno-r1.dts | 18 +++++++++++-------
 arch/arm64/boot/dts/arm/juno.dts    | 18 +++++++++++-------
 2 files changed, 22 insertions(+), 14 deletions(-)

Note: as older kernels don't handle multiple PMUs being listed in the DT, this should be applied after the core changes.

arch/arm64/boot/dts/arm/juno-r1.dts +11 -7
index c627511..734e127 100644
@@ -91,17 +91,21 @@
 		};
 	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
+	pmu_a57 {
+		compatible = "arm,cortex-a57-pmu";
 		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&A57_0>,
+				     <&A57_1>;
+	};
+
+	pmu_a53 {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&A57_0>,
-				     <&A57_1>,
-				     <&A53_0>,
+		interrupt-affinity = <&A53_0>,
 				     <&A53_1>,
 				     <&A53_2>,
 				     <&A53_3>;
arch/arm64/boot/dts/arm/juno.dts +11 -7
index d7cbdd4..ffa05ae 100644
@@ -91,17 +91,21 @@
 		};
 	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
+	pmu_a57 {
+		compatible = "arm,cortex-a57-pmu";
 		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&A57_0>,
+				     <&A57_1>;
+	};
+
+	pmu_a53 {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&A57_0>,
-				     <&A57_1>,
-				     <&A53_0>,
+		interrupt-affinity = <&A53_0>,
 				     <&A53_1>,
 				     <&A53_2>,
 				     <&A53_3>;
Signature · 1 line
1.9.1
#5 lore raw

PATCH v4 4/6 arm64: dts: juno: describe PMUs separately

Quoted 5 lines · Mark Rutland

The A57 and A53 PMUs in Juno support different events, so describe them separately in both the Juno and Juno R1 DTs.

Signed-off-by Mark Rutland <[email protected]>
Cc Liviu Dudau <[email protected]>

I'm sending this from my personal account as the corporate one is having hickups with external mailing lists.

Acked-by Liviu Dudau <[email protected]>

Best regards,
Liviu

Quoted 83 lines
Cc Will Deacon <[email protected]>
---
 arch/arm64/boot/dts/arm/juno-r1.dts | 18 +++++++++++-------
 arch/arm64/boot/dts/arm/juno.dts    | 18 +++++++++++-------
 2 files changed, 22 insertions(+), 14 deletions(-)

Note: as older kernels don't handle multiple PMUs being listed in the DT, this should be applied after the core changes.

arch/arm64/boot/dts/arm/juno-r1.dts +11 -7
index c627511..734e127 100644
@@ -91,17 +91,21 @@
 		};
 	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
+	pmu_a57 {
+		compatible = "arm,cortex-a57-pmu";
 		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&A57_0>,
+				     <&A57_1>;
+	};
+
+	pmu_a53 {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&A57_0>,
-				     <&A57_1>,
-				     <&A53_0>,
+		interrupt-affinity = <&A53_0>,
 				     <&A53_1>,
 				     <&A53_2>,
 				     <&A53_3>;
arch/arm64/boot/dts/arm/juno.dts +11 -7
index d7cbdd4..ffa05ae 100644
@@ -91,17 +91,21 @@
 		};
 	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
+	pmu_a57 {
+		compatible = "arm,cortex-a57-pmu";
 		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&A57_0>,
+				     <&A57_1>;
+	};
+
+	pmu_a53 {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&A57_0>,
-				     <&A57_1>,
-				     <&A53_0>,
+		interrupt-affinity = <&A53_0>,
 				     <&A53_1>,
 				     <&A53_2>,
 				     <&A53_3>;
Signature · 7 lines
1.9.1


_______________________________________________
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linux-arm-kernel at lists.infradead.org
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Signature · 10 lines
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author maintainer
#6 lore raw

PATCH v4 5/6 MAINTAINERS: update ARM PMU profiling and debugging for arm64

In reply to Mark Rutland

Will Deacon maintains the profiling and debugging code under both arch/arm and arch/arm64. Update MAINTAINERS to reflect this, in preparation for adding myself as a reviewer of said code.

Signed-off-by Mark Rutland <[email protected]>
Cc Catalin Marinas <[email protected]>
Cc Will Deacon <[email protected]>
---
 MAINTAINERS | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
MAINTAINERS +4 -4
index 7ba7ab7..236465e 100644
@@ -817,11 +817,11 @@ F:	arch/arm/include/asm/floppy.h
 ARM PMU PROFILING AND DEBUGGING
 M:	Will Deacon <[email protected]>
 S:	Maintained
-F:	arch/arm/kernel/perf_*
+F:	arch/arm*/kernel/perf_*
 F:	arch/arm/oprofile/common.c
-F:	arch/arm/kernel/hw_breakpoint.c
-F:	arch/arm/include/asm/hw_breakpoint.h
-F:	arch/arm/include/asm/perf_event.h
+F:	arch/arm*/kernel/hw_breakpoint.c
+F:	arch/arm*/include/asm/hw_breakpoint.h
+F:	arch/arm*/include/asm/perf_event.h
 F:	drivers/perf/arm_pmu.c
 F:	include/linux/perf/arm_pmu.h
Signature · 1 line
1.9.1
author maintainer
#7 lore raw

PATCH v4 6/6 MAINTAINERS: add myself as arm perf reviewer

In reply to Mark Rutland

As suggested by Will Deacon, add myself as a reviewer of the ARM PMU profiling and debugging code.

Signed-off-by Mark Rutland <[email protected]>
Cc Will Deacon <[email protected]>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)
MAINTAINERS +1 -0
index 236465e..74673aa 100644
@@ -816,6 +816,7 @@ F:	arch/arm/include/asm/floppy.h
 
 ARM PMU PROFILING AND DEBUGGING
 M:	Will Deacon <[email protected]>
+R:	Mark Rutland <[email protected]>
 S:	Maintained
 F:	arch/arm*/kernel/perf_*
 F:	arch/arm/oprofile/common.c
Signature · 1 line
1.9.1
#8 lore raw

v4 cover arm64: perf: heterogeneous PMU support

In reply to Mark Rutland
Quoted 6 lines · Mark Rutland

This patch series moves the arm64 code over to the librified perf code now used by 32-bit arm, in the process gaining support for heterogeneous PMUs. Tailored support is then added for Cortex-A53 and Cortex-A57 as used in Juno systems.

With this series applied, perf can be used to monitor 64-bit systems with heterogeneous PMUs in an identical fashion to 32-bit systems, e.g.

For the series:

Acked-by Will Deacon <[email protected]>

There's a trailing whitespace error in the first patch, but Catalin can probably fix that up.

Will

maintainer
#9 lore raw

v4 cover arm64: perf: heterogeneous PMU support

Quoted 11 lines · Will Deacon
Quoted 6 lines · Mark Rutland

This patch series moves the arm64 code over to the librified perf code now used by 32-bit arm, in the process gaining support for heterogeneous PMUs. Tailored support is then added for Cortex-A53 and Cortex-A57 as used in Juno systems.

With this series applied, perf can be used to monitor 64-bit systems with heterogeneous PMUs in an identical fashion to 32-bit systems, e.g.

For the series:

Acked-by Will Deacon <[email protected]>

Thanks.

Quoted 2 lines

There's a trailing whitespace error in the first patch, but Catalin can probably fix that up.

I fixed this as well. Queued.

Signature · 1 line
Catalin
author maintainer
#10 lore raw

v4 cover arm64: perf: heterogeneous PMU support

Quoted 11 lines · Catalin Marinas
Quoted 10 lines · Will Deacon
Quoted 6 lines · Mark Rutland

This patch series moves the arm64 code over to the librified perf code now used by 32-bit arm, in the process gaining support for heterogeneous PMUs. Tailored support is then added for Cortex-A53 and Cortex-A57 as used in Juno systems.

With this series applied, perf can be used to monitor 64-bit systems with heterogeneous PMUs in an identical fashion to 32-bit systems, e.g.

For the series:

Quoted 8 lines
Quoted 1 line
Acked-by Will Deacon <[email protected]>

Thanks.

Quoted 2 lines

There's a trailing whitespace error in the first patch, but Catalin can probably fix that up.

I fixed this as well. Queued.

Thanks to you both, sorry about the whitespace.

Mark.