Skip to contentSkip to conversation

pci: pcie_imx: Fix hang on mx6qp

PATCH Superseded Fabio Estevam 4 participants 5 messages Oct 8, 2015

Subsystems (3)
Arm (32-bit) Arm i.MX and Layerscape PCI

v1 of 4 Superseded Latest is v4 →

lore
Share & tools
lore

Fabio Estevam

author
#0 lore raw

PATCH 1/1 pci: pcie_imx: Fix hang on mx6qp

PCI driver currently hangs on mx6qp.

Toggle the reset bit with the appropriate timings to fix the issue.

Based on the FSL kernel driver implementation.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/include/asm/arch-mx6/iomux.h |  2 ++
 drivers/pci/pcie_imx.c                | 14 ++++++++++++++
 2 files changed, 16 insertions(+)
arch/arm/include/asm/arch-mx6/iomux.h +2 -0
index 9b3a91f..e3ef59f 100644
@@ -18,6 +18,8 @@
 #define IOMUXC_GPR1_REF_SSP_EN			(1 << 16)
 #define IOMUXC_GPR1_TEST_POWERDOWN		(1 << 18)
 
+#define IOMUXC_GPR1_PCIE_SW_RST 		(1 << 29)
+
 /*
  * IOMUXC_GPR5 bit fields
  */
drivers/pci/pcie_imx.c +14 -0
index 1568f20..ddfe389 100644
@@ -19,6 +19,7 @@
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <errno.h>
+#include <asm/arch/sys_proto.h>
 
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1

@@ -430,6 +431,10 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
 static int imx6_pcie_assert_core_reset(void)
 {
 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	if (is_mx6dqp())
+		setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
+
 #if defined(CONFIG_MX6SX)
 	struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
 

@@ -542,6 +547,15 @@ static int imx6_pcie_deassert_core_reset(void)
 	 */
 	mdelay(50);
 
+	if (is_mx6dqp()) {
+		clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
+		/*
+		 * some delay is required by 6qp, after the SW_RST is
+		 * cleared and before accessing the cfg register.
+		 */
+		udelay(200);
+	}
+
 #if defined(CONFIG_MX6SX)
 	/* SSP_EN is not used on MX6SX anymore */
 	clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
Signature · 1 line
1.9.1
#1 lore raw

PATCH 1/1 pci: pcie_imx: Fix hang on mx6qp

Quoted 65 lines · Fabio Estevam

PCI driver currently hangs on mx6qp.

Toggle the reset bit with the appropriate timings to fix the issue.

Based on the FSL kernel driver implementation.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/include/asm/arch-mx6/iomux.h |  2 ++
 drivers/pci/pcie_imx.c                | 14 ++++++++++++++
 2 files changed, 16 insertions(+)
arch/arm/include/asm/arch-mx6/iomux.h +2 -0
index 9b3a91f..e3ef59f 100644
@@ -18,6 +18,8 @@
 #define IOMUXC_GPR1_REF_SSP_EN                 (1 << 16)
 #define IOMUXC_GPR1_TEST_POWERDOWN             (1 << 18)
 
+#define IOMUXC_GPR1_PCIE_SW_RST                (1 << 29)
+
 /*
  * IOMUXC_GPR5 bit fields
  */
drivers/pci/pcie_imx.c +14 -1
index 1568f20..ddfe389 100644
@@ -19,6 +19,7 @@
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <errno.h>
+#include <asm/arch/sys_proto.h>
 
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1

@@ -430,6 +431,10 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
 static int imx6_pcie_assert_core_reset(void)
 {
        struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+       if (is_mx6dqp())
+               setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
+
 #if defined(CONFIG_MX6SX)
        struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
 

@@ -542,6 +547,15 @@ static int imx6_pcie_deassert_core_reset(void)
         */
        mdelay(50);
 
+       if (is_mx6dqp()) {
+               clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
+               /*
+                * some delay is required by 6qp, after the SW_RST is
+                * cleared and before accessing the cfg register.
+                */
+               udelay(200);
+       }
+
 #if defined(CONFIG_MX6SX)
        /* SSP_EN is not used on MX6SX anymore */
        clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
--
Quoted 2 lines

1.9.1

Fabio,

So Freescale finally connected a usable reset to the PCIe core but only on the QuadPlus? GPR1.29 is marked as 'reserved' in the IMX6DQRM and I'm unable to find a RM for the QP. Is this something that will be rolled into a silicon revision of the IMX6DQ and IMX6SDL?

Regards,

Tim

reviewer
#2 lore raw

PATCH 1/1 pci: pcie_imx: Fix hang on mx6qp

Hi Tim,

Quoted 6 lines · Tim Harvey

Fabio,

So Freescale finally connected a usable reset to the PCIe core but only on the QuadPlus? GPR1.29 is marked as 'reserved' in the IMX6DQRM and I'm unable to find a RM for the QP. Is this something that will be rolled into a silicon revision of the IMX6DQ and IMX6SDL?

Only the newer SoCs have the PCI reset: mx6sx, mx7d, mx6qp.

Regards,

Fabio Estevam

#3 lore raw

PATCH 1/1 pci: pcie_imx: Fix hang on mx6qp

In reply to Fabio Estevam
Quoted 49 lines · Fabio Estevam

PCI driver currently hangs on mx6qp.

Toggle the reset bit with the appropriate timings to fix the issue.

Based on the FSL kernel driver implementation.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/include/asm/arch-mx6/iomux.h |  2 ++
 drivers/pci/pcie_imx.c                | 14 ++++++++++++++
 2 files changed, 16 insertions(+)
(quoted diff) +0 -0

b/arch/arm/include/asm/arch-mx6/iomux.h index 9b3a91f..e3ef59f 100644

arch/arm/include/asm/arch-mx6/iomux.h +2 -0
@@ -18,6 +18,8 @@
 #define IOMUXC_GPR1_REF_SSP_EN			(1 << 16)
 #define IOMUXC_GPR1_TEST_POWERDOWN		(1 << 18)
 
+#define IOMUXC_GPR1_PCIE_SW_RST 		(1 << 29)
+
 /*
  * IOMUXC_GPR5 bit fields
  */
drivers/pci/pcie_imx.c +5 -0
index 1568f20..ddfe389 100644
@@ -19,6 +19,7 @@
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <errno.h>
+#include <asm/arch/sys_proto.h>
 
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1

@@ -430,6 +431,10 @@ static int imx_pcie_write_config(struct pci_controller
 *hose, pci_dev_t d, static int imx6_pcie_assert_core_reset(void)
 {
 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	if (is_mx6dqp())
+		setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
+
 #if defined(CONFIG_MX6SX)
 	struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;

drivers/pci/pcie_imx.c static int imx6_pcie_deassert_core_reset(void) · line 551

Quoted 5 lines
drivers/pci/pcie_imx.c +2 -0
@@ -542,6 +547,15 @@ static int imx6_pcie_deassert_core_reset(void)
 	 */
 	mdelay(50);
 
+	if (is_mx6dqp()) {
+		clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);

Why don't you put this section before the mdelay(50) above ? This should produce the same effect as adding additional delay, as you do below, no?

drivers/pci/pcie_imx.c static int imx6_pcie_deassert_core_reset(void) · line 553

Quoted 2 lines
drivers/pci/pcie_imx.c +2 -0
+		/*
+		 * some delay is required by 6qp, after the SW_RST is

The sentence should start with capital letter.

drivers/pci/pcie_imx.c static int imx6_pcie_deassert_core_reset(void) · line 561

Quoted 8 lines
drivers/pci/pcie_imx.c +5 -0
+		 * cleared and before accessing the cfg register.
+		 */
+		udelay(200);
+	}
+
 #if defined(CONFIG_MX6SX)
 	/* SSP_EN is not used on MX6SX anymore */
 	clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);

Best regards,
Marek Vasut

reviewer
#4 lore raw

PATCH 1/1 pci: pcie_imx: Fix hang on mx6qp

Quoted 7 lines · Marek Vasut

drivers/pci/pcie_imx.c static int imx6_pcie_deassert_core_reset(void) · line 551

Quoted 4 lines
      mdelay(50);
drivers/pci/pcie_imx.c +2 -0
+     if (is_mx6dqp()) {
+             clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);

Why don't you put this section before the mdelay(50) above ? This should produce the same effect as adding additional delay, as you do below, no?

Good idea. Will do as suggested in v2, thanks.