Add DRA7 sub-mailboxes for 4.4
cover Add DRA7 sub-mailboxes for 4.4
Hi Tony,
This series adds the sub-mailbox nodes and enable them for each of the TI DRA7 boards. These are the basic mailbox configuration nodes required by client users (remoteproc) to communicate with the various IPU and DSP processor devices on DRA74x and DRA72x SoCs using the TI IPC 3.x software foundation on the remote processor firmwares. The mailboxes used are unfortunately hardcoded in the TI IPC 3.x software, and hence the weird usage of Mailbox 5 and 6 rather than starting from Mailbox 1.
Any third-party or derived boards can use their own configuration if running their own IPC stack, and that can be done by overwriting the properties or by using different sub-mailbox nodes altogether. The actual enablement of nodes is therefore done in the respective board DTS files.
Patches are based on 4.3-rc1 and are intended for the 4.4 merge window.
regards
Suman
Suman Anna (5):
ARM: dts: DRA74x: Add IPC sub-mailbox nodes for all IPUs & DSPs
ARM: dts: DRA72x: Add IPC sub-mailbox nodes for IPU1, IPU2 & DSP1
ARM: dts: dra7-evm: Enable the system mailboxes 5 and 6
ARM: dts: dra72-evm: Enable the system mailboxes 5 and 6
ARM: dts: beagle-x15: Enable the system mailboxes 5 and 6
arch/arm/boot/dts/am57xx-beagle-x15.dts | 20 ++++++++++++++++++++ arch/arm/boot/dts/dra7-evm.dts | 20 ++++++++++++++++++++ arch/arm/boot/dts/dra72-evm.dts | 17 +++++++++++++++++ arch/arm/boot/dts/dra72x.dtsi | 21 +++++++++++++++++++++ arch/arm/boot/dts/dra74x.dtsi | 26 ++++++++++++++++++++++++++ 5 files changed, 104 insertions(+)
Signature · 1 line
2.5.0
PATCH 1/5 ARM: dts: DRA74x: Add IPC sub-mailbox nodes for all IPUs & DSPs
Add the sub-mailbox nodes that are used to communicate between MPU and the remote processors IPU1, IPU2, DSP1 and DSP2.
The sub-mailbox nodes utilize the System Mailbox instances 5 and 6. These sub-mailbox nodes are added to match the hard-coded mailbox configuration used within the TI IPC 3.x software package. The Dual-Cortex M4 IPU1 and IPU2 processor sub-systems are assumed to be running in SMP-mode, and hence only a single sub-mailbox node is added for each.
All these sub-mailbox nodes are left in disabled state, and should be enabled (and modified if needed) as per the individual product configuration in the corresponding board dts files.
--- arch/arm/boot/dts/dra74x.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)
arch/arm/boot/dts/dra74x.dtsi +26 -0
@@ -93,3 +93,29 @@ <&dss_video2_clk>; clock-names = "fck", "video1_clk", "video2_clk"; }; + +&mailbox5 { + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + ti,mbox-tx = <6 2 2>; + ti,mbox-rx = <4 2 2>; + status = "disabled"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + ti,mbox-tx = <5 2 2>; + ti,mbox-rx = <1 2 2>; + status = "disabled"; + }; +}; + +&mailbox6 { + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + ti,mbox-tx = <6 2 2>; + ti,mbox-rx = <4 2 2>; + status = "disabled"; + }; + mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + ti,mbox-tx = <5 2 2>; + ti,mbox-rx = <1 2 2>; + status = "disabled"; + }; +};
Signature · 1 line
2.5.0
PATCH 2/5 ARM: dts: DRA72x: Add IPC sub-mailbox nodes for IPU1, IPU2 & DSP1
In reply to Suman AnnaAdd the sub-mailbox nodes that are used to communicate between MPU and the remote processors IPU1, IPU2 and DSP1. These match the respective node definitions on DRA74x to maintain compatibility for the equivalent remote processors. There is no DSP2 on DRA72x, and so the corresponding sub-mailbox node is not added.
These sub-mailbox nodes are added to match the hard-coded mailbox configuration used within the TI IPC 3.x software package. The Dual-Cortex M4 IPU1 and IPU2 processor sub-systems are assumed to be running in SMP-mode, and hence only a single sub-mailbox node is added for each.
All these sub-mailbox nodes are left in disabled state, and should be enabled (and modified if needed) as per the individual product configuration in the corresponding board dts files.
--- arch/arm/boot/dts/dra72x.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
arch/arm/boot/dts/dra72x.dtsi +21 -0
@@ -45,3 +45,24 @@ <&dss_video1_clk>; clock-names = "fck", "video1_clk"; }; + +&mailbox5 { + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + ti,mbox-tx = <6 2 2>; + ti,mbox-rx = <4 2 2>; + status = "disabled"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + ti,mbox-tx = <5 2 2>; + ti,mbox-rx = <1 2 2>; + status = "disabled"; + }; +}; + +&mailbox6 { + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + ti,mbox-tx = <6 2 2>; + ti,mbox-rx = <4 2 2>; + status = "disabled"; + }; +};
Signature · 1 line
2.5.0
PATCH 3/5 ARM: dts: dra7-evm: Enable the system mailboxes 5 and 6
In reply to Suman AnnaEnable the System Mailboxes 5 and 6 and the corresponding child sub-mailbox (IPC 3.x) nodes for the DRA7 EVM board. This is needed to enable communication with the respective remote processors IPU1, IPU2, DSP1 and DSP2 from the MPU.
--- arch/arm/boot/dts/dra7-evm.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
arch/arm/boot/dts/dra7-evm.dts +20 -0
@@ -707,3 +707,23 @@ pinctrl-1 = <&dcan1_pins_sleep>; pinctrl-2 = <&dcan1_pins_default>; }; + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; + mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + status = "okay"; + }; +};
Signature · 1 line
2.5.0
PATCH 4/5 ARM: dts: dra72-evm: Enable the system mailboxes 5 and 6
In reply to Suman AnnaEnable the System Mailboxes 5 and 6 and the corresponding child sub-mailbox (IPC 3.x) nodes for the DRA72 EVM board. This is needed to enable communication with the respective remote processors IPU1, IPU2, and DSP1 from the MPU.
--- arch/arm/boot/dts/dra72-evm.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
arch/arm/boot/dts/dra72-evm.dts +17 -0
@@ -695,3 +695,20 @@ }; }; }; + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; +};
Signature · 1 line
2.5.0
PATCH 5/5 ARM: dts: beagle-x15: Enable the system mailboxes 5 and 6
In reply to Suman AnnaEnable the System Mailboxes 5 and 6 and the corresponding child sub-mailbox (IPC 3.x) nodes for the Beagle X15 EVM boards. This is needed to enable communication with the respective remote processors IPU1, IPU2, DSP1 and DSP2 from the MPU.
--- arch/arm/boot/dts/am57xx-beagle-x15.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
arch/arm/boot/dts/am57xx-beagle-x15.dts +20 -0
@@ -696,3 +696,23 @@ &pcie1 { gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; }; + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; + mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + status = "okay"; + }; +};
Signature · 1 line
2.5.0
cover Add DRA7 sub-mailboxes for 4.4
In reply to Suman AnnaQuoted 11 lines · Suman Anna
Hi Tony,
This series adds the sub-mailbox nodes and enable them for each of the TI DRA7 boards. These are the basic mailbox configuration nodes required by client users (remoteproc) to communicate with the various IPU and DSP processor devices on DRA74x and DRA72x SoCs using the TI IPC 3.x software foundation on the remote processor firmwares. The mailboxes used are unfortunately hardcoded in the TI IPC 3.x software, and hence the weird usage of Mailbox 5 and 6 rather than starting from Mailbox 1.
Quoted 8 lines
Any third-party or derived boards can use their own configuration if running their own IPC stack, and that can be done by overwriting the properties or by using different sub-mailbox nodes altogether. The actual enablement of nodes is therefore done in the respective board DTS files.
Patches are based on 4.3-rc1 and are intended for the 4.4 merge window.
Thanks applying all into omap-for-v4.4/dt.
Tony