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iommu/arm-smmu: Add support for MSI on SMMUv3

PATCH New Marc Zyngier 2 participants 2 messages Oct 13, 2015

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Device tree bindings IOMMU Arm SMMU drivers
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Marc Zyngier

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PATCH v4 1/1 iommu/arm-smmu: Add support for MSI on SMMUv3

Despite being a platform device, the SMMUv3 is capable of signaling interrupts using MSIs. Hook it into the platform MSI framework and enjoy faults being reported in a new and exciting way.

Signed-off-by Marc Zyngier <[email protected]>

---
* From v3:
- Pass the device as a parameter to the MSI destructor (instead of the smmu structure)
- Select CONFIG_GENERIC_MSI_IRQ
- Update binding documentation (and add an example)

* From v2:
- MSI indexes as an enum
- Fixed stupid 16bit writes instead of 32bit
- Added devm callback to release MSIs on teardown
- Moved all the MSI setup to its own function

 .../devicetree/bindings/iommu/arm,smmu-v3.txt      |  20 ++++
 drivers/iommu/Kconfig                              |   1 +
 drivers/iommu/arm-smmu-v3.c                        | 106 +++++++++++++++++++--
 3 files changed, 119 insertions(+), 8 deletions(-)
Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt +20 -0
index 3443e0f..9f5958e 100644
@@ -36,5 +36,25 @@ the PCIe specification.
                       NOTE: this only applies to the SMMU itself, not
                       masters connected upstream of the SMMU.
 
+- msi-parent	    : phandles (and potential Device IDs) of MSI controllers
+		      the SMMU can send MSIs to (instead of wired interrupts).
+		      See devicetree/bindings.interrupt-controller/msi.txt
+		      for a description of the msi-parent property.
+
 - hisilicon,broken-prefetch-cmd
                     : Avoid sending CMD_PREFETCH_* commands to the SMMU.
+
+** Example
+
+        smmu at 2b400000 {
+                compatible = "arm,smmu-v3";
+                reg = <0x0 0x2b400000 0x0 0x20000>;
+                interrupts = <0x0 0x4a 0x1>,
+			     <0x0 0x4b 0x1>,
+			     <0x0 0x4d 0x1>,
+			     <0x0 0x4f 0x1>;
+                interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
+                dma-coherent;
+                #iommu-cells = <0x0>;
+                msi-parent = <&its 0x13210>;
+        };
drivers/iommu/Kconfig +1 -0
index 4664c2a..722ec85 100644
@@ -362,6 +362,7 @@ config ARM_SMMU_V3
 	depends on ARM64 && PCI
 	select IOMMU_API
 	select IOMMU_IO_PGTABLE_LPAE
+	select GENERIC_MSI_IRQ_DOMAIN
 	help
 	  Support for implementations of the ARM System MMU architecture
 	  version 3 providing translation support to a PCIe root complex.
drivers/iommu/arm-smmu-v3.c +98 -8

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2.1.4
#1 lore raw

PATCH v4 1/1 iommu/arm-smmu: Add support for MSI on SMMUv3

Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt the PCIe specification. · line 39

Quoted 6 lines

+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt

Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt +1 -0
@@ -36,5 +36,25 @@ the PCIe specification.
                       NOTE: this only applies to the SMMU itself, not
                       masters connected upstream of the SMMU.
 
+- msi-parent	    : phandles (and potential Device IDs) of MSI controllers

For correct terminology, I'd prefer to replace this line with:

- msi-parent: a list of phandle + msi-specifier pairs for MSI controllers

An msi-specifier may be zero cells, per Documentation/devicetree/bindings/interrupt-controller/msi.txt, much like other *-specifiers.

Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt the PCIe specification. · line 42

Quoted 3 lines
Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt +3 -0
+		      the SMMU can send MSIs to (instead of wired interrupts).
+		      See devicetree/bindings.interrupt-controller/msi.txt
+		      for a description of the msi-parent property.

The rest of this is fine, modulo the '.' which should be a '/'. in the path.

With those changes:

Acked-by Mark Rutland <[email protected]>

Thanks,
Mark.