i2c: Add i2c support to Freescale Layerscape platforms
Subsystems (5)
PATCH v4 1/6 i2c: Add i2c support to Freescale Layerscape platforms
From: Shaohui Xie <[email protected]>
Modify the I2C_IMX config to support to Layerscape platforms.
---
V4: V3 V2
- No change.
drivers/i2c/busses/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/i2c/busses/Kconfig +2 -2
@@ -582,10 +582,10 @@ config I2C_IMG config I2C_IMX tristate "IMX I2C interface" - depends on ARCH_MXC + depends on ARCH_MXC || ARCH_LAYERSCAPE help Say Y here if you want to use the IIC bus controller on - the Freescale i.MX/MXC processors. + the Freescale i.MX/MXC or Layerscape processors. This driver can also be built as a module. If so, the module will be called i2c-imx.
Signature · 1 line
2.1.0.27.g96db324
PATCH v4 2/6 watchdog: Add support for Freescale Layerscape platforms
From: Shaohui Xie <[email protected]>
Modify watchdog/Kconfig file to support Layerscape platforms.
---
This patch has been acked in V3 by Guenter Roeck [linux at roeck-us.net].
V4: V3 V2
- No change.
drivers/watchdog/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/watchdog/Kconfig +1 -1
@@ -446,7 +446,7 @@ config MAX63XX_WATCHDOG config IMX2_WDT tristate "IMX2+ Watchdog" - depends on ARCH_MXC + depends on ARCH_MXC || ARCH_LAYERSCAPE select REGMAP_MMIO select WATCHDOG_CORE help
Signature · 1 line
2.1.0.27.g96db324
Guenter Roeck
maintainerPATCH v4 2/6 watchdog: Add support for Freescale Layerscape platforms
Quoted 10 lines · Zhiqiang Hou
From: Shaohui Xie <[email protected]>
Modify watchdog/Kconfig file to support Layerscape platforms.
Signed-off-by Shaohui Xie <[email protected]>Signed-off-by Wenbin Song <[email protected]>Signed-off-by Hou Zhiqiang <[email protected]>---
This patch has been acked in V3 by Guenter Roeck [linux at roeck-us.net].
Here it is again, but if there is no change, please just add the Ack to subsequent versions of the patch.
Quoted 20 lines
V4: V3 V2
- No change.drivers/watchdog/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/watchdog/Kconfig +1
-1@@ -446,7 +446,7 @@ config MAX63XX_WATCHDOG config IMX2_WDT tristate "IMX2+ Watchdog" - depends on ARCH_MXC + depends on ARCH_MXC || ARCH_LAYERSCAPE select REGMAP_MMIO select WATCHDOG_CORE help
PATCH v4 2/6 watchdog: Add support for Freescale Layerscape platforms
Quoted 21 lines
-----Original Message-----
From: Guenter Roeck [mailto:linux at roeck-us.net]
Sent: 2015?10?15? 22:25
To: Hou Zhiqiang-B48286; linux-arm-kernel at lists.infradead.org; catalin.marinas at arm.com; will.deacon at arm.com; linux-i2c at vger.kernel.org; linux-watchdog at vger.kernel.org; linux-doc at vger.kernel.org; linux- clk at vger.kernel.org
Cc: mark.rutland at arm.com; wsa at the-dreams.de; wim at iguana.be; corbet at lwn.net; mturquette at baylibre.com; sboyd at codeaurora.org; Hu Mingkai-B21284; Xie Shaohui-B21989; Wood Scott-B07421; Sharma Bhupesh- B45370; Song Wenbin-B53747
Subject: Re: [PATCH V4 2/6] watchdog: Add support for Freescale Layerscape platformsQuoted 4 lines · Zhiqiang Hou
From: Shaohui Xie <[email protected]>
Modify watchdog/Kconfig file to support Layerscape platforms.
Quoted 9 lines
Quoted 6 lines
Signed-off-by Shaohui Xie <[email protected]>Signed-off-by Wenbin Song <[email protected]>Signed-off-by Hou Zhiqiang <[email protected]>---
This patch has been acked in V3 by Guenter Roeck [linux at roeck-us.net].Here it is again, but if there is no change, please just add the Ack to subsequent versions of the patch.
Ok, thanks.
Quoted 15 lines
Acked-by Guenter Roeck <[email protected]>Quoted 12 lines
V4: V3 V2
- No change.drivers/watchdog/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/watchdog/Kconfig index renamed from drivers/watchdog/Kconfig +0
-079e1aa1..448dbaf 100644
drivers/watchdog/Kconfig +0
-0@@ -446,7 +446,7 @@ config MAX63XX_WATCHDOG
Quoted 8 lines
drivers/watchdog/Kconfig config MAX63XX_WATCHDOG · line 452
Quoted 8 lines
drivers/watchdog/Kconfig +1
-1config IMX2_WDT tristate "IMX2+ Watchdog" - depends on ARCH_MXC + depends on ARCH_MXC || ARCH_LAYERSCAPE select REGMAP_MMIO select WATCHDOG_CORE help
Thanks,
Zhiqiang
PATCH v4 3/6 Documentation: DT: Add entry for FSL LS1043ARDB board
In reply to Zhiqiang HouFrom: Mingkai Hu <[email protected]>
---
V4: V3 V2
- No change.
Documentation/devicetree/bindings/arm/fsl.txt | 4 ++++ 1 file changed, 4 insertions(+)
Documentation/devicetree/bindings/arm/fsl.txt +4 -0
@@ -131,6 +131,10 @@ Example: Freescale ARMv8 based Layerscape SoC family Device Tree Bindings ---------------------------------------------------------------- +LS1043A ARMv8 based RDB Board +Required root node properties: + - compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; + LS2080A ARMv8 based Simulator model Required root node properties: - compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
Signature · 1 line
2.1.0.27.g96db324
PATCH v4 4/6 arm64/ls1043a: add DTS for Freescale LS1043A SoC
In reply to Zhiqiang HouFrom: Mingkai Hu <[email protected]>
LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks similar to LS1021a which complies to Chassis 2.1 spec.
Following levels of DTSI/DTS files have been created for the LS1043A SoC family:
- fsl-ls1043a.dtsi:
DTS-Include file for FSL LS1043A SoC.
---
V4:
- Add soc node with simple-bus compatible.
- Add property interrupt-affinity for armv8 pmuv3 node.
V3:
- Add device tree node for SATA.
- Remove properity enable-method for all cpu node. Remove reserved memory region for spin-table.
V2:
- Add secondary core boot method.
- Move out the sysclk node from the clockgen node.
- Correct the reg size of GICC.
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 525 +++++++++++++++++++++++++ 1 file changed, 525 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +525 -0
@@ -0,0 +1,525 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright 2014-2015, Freescale Semiconductor + * + * Mingkai Hu <[email protected]> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + compatible = "fsl,ls1043a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* + * We expect the enable-method for cpu's to be "psci", but this + * is dependent on the SoC FW, which will fill this in. + * + * Currently supported enable-method is psci v0.2 + */ + cpu0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + clocks = <&clockgen 1 0>; + }; + + cpu1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + clocks = <&clockgen 1 0>; + }; + + cpu2: cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + clocks = <&clockgen 1 0>; + }; + + cpu3: cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + clocks = <&clockgen 1 0>; + }; + }; + + memory at 80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + /* DRAM space 1, size: 2GiB DRAM */ + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clockgen: clocking at 1ee1000 { + compatible = "fsl,ls1043a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x1>, /* Physical Secure PPI */ + <1 14 0x1>, /* Physical Non-Secure PPI */ + <1 11 0x1>, /* Virtual PPI */ + <1 10 0x1>; /* Hypervisor PPI */ + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 106 0x4>, + <0 107 0x4>, + <0 95 0x4>, + <0 97 0x4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + gic: interrupt-controller at 1400000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0 0x1000>, /* GICD */ + <0x0 0x1402000 0 0x2000>, /* GICC */ + <0x0 0x1404000 0 0x2000>, /* GICH */ + <0x0 0x1406000 0 0x2000>; /* GICV */ + interrupts = <1 9 0xf08>; + }; + + scfg: scfg at 1570000 { + compatible = "fsl,ls1043a-scfg", "syscon"; + reg = <0x0 0x1570000 0x0 0x10000>; + big-endian; + }; + + dcfg: dcfg at 1ee0000 { + compatible = "fsl,ls1043a-dcfg", "syscon"; + reg = <0x0 0x1ee0000 0x0 0x10000>; + }; + + ifc: ifc at 1530000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x0 0x1530000 0x0 0x10000>; + interrupts = <0 43 0x4>; + }; + + esdhc: esdhc at 1560000 { + compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; + reg = <0x0 0x1560000 0x0 0x10000>; + interrupts = <0 62 0x4>; + clock-frequency = <0>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + big-endian; + bus-width = <4>; + }; + + dspi0: dspi at 2100000 { + compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 64 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + spi-num-chipselects = <5>; + big-endian; + status = "disabled"; + }; + + dspi1: dspi at 2110000 { + compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <0 65 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + spi-num-chipselects = <5>; + big-endian; + status = "disabled"; + }; + + i2c0: i2c at 2180000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = <0 56 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + dmas = <&edma0 1 39>, + <&edma0 1 38>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c1: i2c at 2190000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = <0 57 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c2: i2c at 21a0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21a0000 0x0 0x10000>; + interrupts = <0 58 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c3: i2c at 21b0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21b0000 0x0 0x10000>; + interrupts = <0 59 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + duart0: serial at 21c0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0500 0x0 0x100>; + interrupts = <0 54 0x4>; + clocks = <&clockgen 4 0>; + }; + + duart1: serial at 21c0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0600 0x0 0x100>; + interrupts = <0 54 0x4>; + clocks = <&clockgen 4 0>; + }; + + duart2: serial at 21d0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21d0500 0x0 0x100>; + interrupts = <0 55 0x4>; + clocks = <&clockgen 4 0>; + }; + + duart3: serial at 21d0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21d0600 0x0 0x100>; + interrupts = <0 55 0x4>; + clocks = <&clockgen 4 0>; + }; + + gpio1: gpio at 2300000 { + compatible = "fsl,ls1043a-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 66 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio at 2310000 { + compatible = "fsl,ls1043a-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 67 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio at 2320000 { + compatible = "fsl,ls1043a-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 68 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio at 2330000 { + compatible = "fsl,ls1043a-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 134 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + lpuart0: serial at 2950000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2950000 0x0 0x1000>; + interrupts = <0 48 0x4>; + clocks = <&clockgen 0 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart1: serial at 2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2960000 0x0 0x1000>; + interrupts = <0 49 0x4>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial at 2970000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2970000 0x0 0x1000>; + interrupts = <0 50 0x4>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart3: serial at 2980000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2980000 0x0 0x1000>; + interrupts = <0 51 0x4>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial at 2990000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2990000 0x0 0x1000>; + interrupts = <0 52 0x4>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial at 29a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x29a0000 0x0 0x1000>; + interrupts = <0 53 0x4>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + wdog0: wdog at 2ad0000 { + compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; + reg = <0x0 0x2ad0000 0x0 0x10000>; + interrupts = <0 83 0x4>; + clocks = <&clockgen 4 0>; + clock-names = "wdog"; + big-endian; + }; + + edma0: edma at 2c00000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x0 0x2c00000 0x0 0x10000>, + <0x0 0x2c10000 0x0 0x10000>, + <0x0 0x2c20000 0x0 0x10000>; + interrupts = <0 103 0x4>, + <0 103 0x4>; + interrupt-names = "edma-tx", "edma-err"; + dma-channels = <32>; + big-endian; + clock-names = "dmamux0", "dmamux1"; + clocks = <&clockgen 4 0>, + <&clockgen 4 0>; + }; + + usb0: usb3 at 2f00000 { + compatible = "snps,dwc3"; + reg = <0x0 0x2f00000 0x0 0x10000>; + interrupts = <0 60 0x4>; + dr_mode = "host"; + }; + + usb1: usb3 at 3000000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3000000 0x0 0x10000>; + interrupts = <0 61 0x4>; + dr_mode = "host"; + }; + + usb2: usb3 at 3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 63 0x4>; + dr_mode = "host"; + }; + + sata: sata at 3200000 { + compatible = "fsl,ls1043a-ahci", "fsl,ls1021a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 69 0x4>; + clocks = <&clockgen 4 0>; + }; + + msi1: msi-controller1 at 1571000 { + compatible = "fsl,1s1043a-msi"; + reg = <0x0 0x1571000 0x0 0x4>, + <0x0 0x1571004 0x0 0x4>; + reg-names = "msiir", "msir"; + msi-controller; + interrupts = <0 116 0x4>; + }; + + msi2: msi-controller2 at 1572000 { + compatible = "fsl,1s1043a-msi"; + reg = <0x0 0x1572000 0x0 0x4>, + <0x0 0x1572004 0x0 0x4>; + reg-names = "msiir", "msir"; + msi-controller; + interrupts = <0 126 0x4>; + }; + + msi3: msi-controller3 at 1573000 { + compatible = "fsl,1s1043a-msi"; + reg = <0x0 0x1573000 0x0 0x4>, + <0x0 0x1573004 0x0 0x4>; + reg-names = "msiir", "msir"; + msi-controller; + interrupts = <0 160 0x4>; + }; + + pcie at 3400000 { + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 118 0x4>, /* controller interrupt */ + <0 117 0x4>; /* PME interrupt */ + interrupt-names = "intr", "pme"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&msi1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, + <0000 0 0 2 &gic 0 111 0x4>, + <0000 0 0 3 &gic 0 112 0x4>, + <0000 0 0 4 &gic 0 113 0x4>; + }; + + pcie at 3500000 { + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 128 0x4>, + <0 127 0x4>; + interrupt-names = "intr", "pme"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <2>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&msi2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, + <0000 0 0 2 &gic 0 121 0x4>, + <0000 0 0 3 &gic 0 122 0x4>, + <0000 0 0 4 &gic 0 123 0x4>; + }; + + pcie at 3600000 { + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 162 0x4>, + <0 161 0x4>; + interrupt-names = "intr", "pme"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <2>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&msi3>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, + <0000 0 0 2 &gic 0 155 0x4>, + <0000 0 0 3 &gic 0 156 0x4>, + <0000 0 0 4 &gic 0 157 0x4>; + }; + }; + +};
Signature · 1 line
2.1.0.27.g96db324
PATCH v4 4/6 arm64/ls1043a: add DTS for Freescale LS1043A SoC
Quoted 179 lines · Zhiqiang Hou
From: Mingkai Hu <[email protected]>
LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks similar to LS1021a which complies to Chassis 2.1 spec.
Following levels of DTSI/DTS files have been created for the LS1043A SoC family:
-
fsl-ls1043a.dtsi:
DTS-Include file for FSL LS1043A SoC.Signed-off-by Li Yang <[email protected]>Signed-off-by Hou Zhiqiang <[email protected]>Signed-off-by Mingkai Hu <[email protected]>Signed-off-by Wenbin Song <[email protected]>---
V4:
- Add soc node with simple-bus compatible.
- Add property interrupt-affinity for armv8 pmuv3 node.V3:
- Add device tree node for SATA.
- Remove properity enable-method for all cpu node. Remove reserved memory region for spin-table.V2:
- Add secondary core boot method.
- Move out the sysclk node from the clockgen node.
- Correct the reg size of GICC.arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 525 +++++++++++++++++++++++++ 1 file changed, 525 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsiarch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +137
-0@@ -0,0 +1,525 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright 2014-2015, Freescale Semiconductor + * + * Mingkai Hu <[email protected]> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + compatible = "fsl,ls1043a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* + * We expect the enable-method for cpu's to be "psci", but this + * is dependent on the SoC FW, which will fill this in. + * + * Currently supported enable-method is psci v0.2 + */ + cpu0: cpu at 0{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + clocks = <&clockgen 1 0>; + }; + + cpu1: cpu at 1{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + clocks = <&clockgen 1 0>; + }; + + cpu2: cpu at 2{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + clocks = <&clockgen 1 0>; + }; + + cpu3: cpu at 3{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + clocks = <&clockgen 1 0>; + }; + }; + + memory at 80000000{ + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + /* DRAM space 1, size: 2GiB DRAM */ + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clockgen: clocking at 1ee1000{ + compatible = "fsl,ls1043a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x1>, /* Physical Secure PPI */ + <1 14 0x1>, /* Physical Non-Secure PPI */ + <1 11 0x1>, /* Virtual PPI */ + <1 10 0x1>; /* Hypervisor PPI */ + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 106 0x4>, + <0 107 0x4>, + <0 95 0x4>, + <0 97 0x4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; +
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 147
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +10
-0+ gic: interrupt-controller at 1400000{ + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0 0x1000>, /* GICD */ + <0x0 0x1402000 0 0x2000>, /* GICC */ + <0x0 0x1404000 0 0x2000>, /* GICH */ + <0x0 0x1406000 0 0x2000>; /* GICV */ + interrupts = <1 9 0xf08>; + };
The recently posted ls2080 device tree patch puts pmu, gic, etc. under the root node rather than the soc node. Where should they go? At least it should be consistent...
-Scott
PATCH v4 4/6 arm64/ls1043a: add DTS for Freescale LS1043A SoC
Quoted 208 lines
-----Original Message-----
From: Wood Scott-B07421
Sent: Friday, October 16, 2015 4:46 AM
To: Hou Zhiqiang-B48286
Cc: linux-arm-kernel at lists.infradead.org; catalin.marinas at arm.com; will.deacon at arm.com; linux-i2c at vger.kernel.org; linux-
watchdog at vger.kernel.org; linux-doc at vger.kernel.org; linux-
clk at vger.kernel.org; mark.rutland at arm.com; linux at roeck-us.net; wsa at the- dreams.de; wim at iguana.be; corbet at lwn.net; mturquette at baylibre.com; sboyd at codeaurora.org; Hu Mingkai-B21284; Xie Shaohui-B21989; Sharma Bhupesh-B45370; Song Wenbin-B53747; Li Yang-Leo-R58472; Sharma Bhupesh- B45370
Subject: Re: [PATCH V4 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoCQuoted 48 lines · Zhiqiang Hou
From: Mingkai Hu <[email protected]>
LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks similar to LS1021a which complies to Chassis 2.1 spec.
Following levels of DTSI/DTS files have been created for the LS1043A SoC family:
-
fsl-ls1043a.dtsi:
DTS-Include file for FSL LS1043A SoC.Signed-off-by Li Yang <[email protected]>Signed-off-by Hou Zhiqiang <[email protected]>Signed-off-by Mingkai Hu <[email protected]>Signed-off-by Wenbin Song <[email protected]>---
V4:
- Add soc node with simple-bus compatible.
- Add property interrupt-affinity for armv8 pmuv3 node.V3:
- Add device tree node for SATA.
- Remove properity enable-method for all cpu node. Remove reserved memory region for spin-table.V2:
- Add secondary core boot method.
- Move out the sysclk node from the clockgen node.
- Correct the reg size of GICC.arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 525 +++++++++++++++++++++++++ 1 file changed, 525 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsiarch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +6
-0@@ -0,0 +1,525 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright 2014-2015, Freescale Semiconductor + * + * Mingkai Hu <[email protected]>arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 16
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +10
-0+ * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this +dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 ofthe
Quoted 33 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +33
-0+ * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + compatible = "fsl,ls1043a";arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +10
-0+ interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* + * We expect the enable-method for cpu's to be "psci",but this
Quoted 52 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +52
-0+ * is dependent on the SoC FW, which will fill this in. + * + * Currently supported enable-method is psci v0.2 + */ + cpu0: cpu at 0{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + clocks = <&clockgen 1 0>; + }; + + cpu1: cpu at 1{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + clocks = <&clockgen 1 0>; + }; + + cpu2: cpu at 2{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + clocks = <&clockgen 1 0>; + }; + + cpu3: cpu at 3{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + clocks = <&clockgen 1 0>; + }; + }; + + memory at 80000000{ + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + /* DRAM space 1, size: 2GiB DRAM */ + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; +arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +10
-0+ clockgen: clocking at 1ee1000{ + compatible = "fsl,ls1043a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x1>, /* Physical Secure PPI*/
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 122
Quoted 1 line
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +1
-0+ <1 14 0x1>, /* Physical Non-SecurePPI */
Quoted 22 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +22
-0+ <1 11 0x1>, /* Virtual PPI */ + <1 10 0x1>; /* Hypervisor PPI */ + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 106 0x4>, + <0 107 0x4>, + <0 95 0x4>, + <0 97 0x4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + gic: interrupt-controller at 1400000{ + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0 0x1000>, /* GICD */ + <0x0 0x1402000 0 0x2000>, /* GICC */
Quoted 9 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 147
Quoted 4 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +4
-0+ <0x0 0x1404000 0 0x2000>, /* GICH */ + <0x0 0x1406000 0 0x2000>; /* GICV */ + interrupts = <1 9 0xf08>; + };The recently posted ls2080 device tree patch puts pmu, gic, etc. under the root node rather than the soc node. Where should they go? At least it should be consistent...
There is also discussion between Ron and Stuart about this, but no conclusion about where to put pmu, gic node. Is there any specific reason to put them out of the SoC?
Thanks,
Mingkai
PATCH v4 4/6 arm64/ls1043a: add DTS for Freescale LS1043A SoC
In reply to Scott WoodQuoted 208 lines
-----Original Message-----
From: Wood Scott-B07421
Sent: 2015?10?16? 4:46
To: Hou Zhiqiang-B48286
Cc: linux-arm-kernel at lists.infradead.org; catalin.marinas at arm.com; will.deacon at arm.com; linux-i2c at vger.kernel.org; linux-
watchdog at vger.kernel.org; linux-doc at vger.kernel.org; linux-
clk at vger.kernel.org; mark.rutland at arm.com; linux at roeck-us.net; wsa at the- dreams.de; wim at iguana.be; corbet at lwn.net; mturquette at baylibre.com; sboyd at codeaurora.org; Hu Mingkai-B21284; Xie Shaohui-B21989; Sharma Bhupesh-B45370; Song Wenbin-B53747; Li Yang-Leo-R58472; Sharma Bhupesh- B45370
Subject: Re: [PATCH V4 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoCQuoted 48 lines · Zhiqiang Hou
From: Mingkai Hu <[email protected]>
LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks similar to LS1021a which complies to Chassis 2.1 spec.
Following levels of DTSI/DTS files have been created for the LS1043A SoC family:
-
fsl-ls1043a.dtsi:
DTS-Include file for FSL LS1043A SoC.Signed-off-by Li Yang <[email protected]>Signed-off-by Hou Zhiqiang <[email protected]>Signed-off-by Mingkai Hu <[email protected]>Signed-off-by Wenbin Song <[email protected]>---
V4:
- Add soc node with simple-bus compatible.
- Add property interrupt-affinity for armv8 pmuv3 node.V3:
- Add device tree node for SATA.
- Remove properity enable-method for all cpu node. Remove reserved memory region for spin-table.V2:
- Add secondary core boot method.
- Move out the sysclk node from the clockgen node.
- Correct the reg size of GICC.arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 525 +++++++++++++++++++++++++ 1 file changed, 525 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsiarch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +6
-0@@ -0,0 +1,525 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright 2014-2015, Freescale Semiconductor + * + * Mingkai Hu <[email protected]>arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 16
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +10
-0+ * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this +dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 ofthe
Quoted 33 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +33
-0+ * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + compatible = "fsl,ls1043a";arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +10
-0+ interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* + * We expect the enable-method for cpu's to be "psci",but this
Quoted 52 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +52
-0+ * is dependent on the SoC FW, which will fill this in. + * + * Currently supported enable-method is psci v0.2 + */ + cpu0: cpu at 0{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + clocks = <&clockgen 1 0>; + }; + + cpu1: cpu at 1{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + clocks = <&clockgen 1 0>; + }; + + cpu2: cpu at 2{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + clocks = <&clockgen 1 0>; + }; + + cpu3: cpu at 3{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + clocks = <&clockgen 1 0>; + }; + }; + + memory at 80000000{ + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + /* DRAM space 1, size: 2GiB DRAM */ + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; +arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +10
-0+ clockgen: clocking at 1ee1000{ + compatible = "fsl,ls1043a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x1>, /* Physical Secure PPI*/
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 122
Quoted 1 line
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +1
-0+ <1 14 0x1>, /* Physical Non-SecurePPI */
Quoted 22 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +22
-0+ <1 11 0x1>, /* Virtual PPI */ + <1 10 0x1>; /* Hypervisor PPI */ + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 106 0x4>, + <0 107 0x4>, + <0 95 0x4>, + <0 97 0x4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + gic: interrupt-controller at 1400000{ + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0 0x1000>, /* GICD */ + <0x0 0x1402000 0 0x2000>, /* GICC */
Quoted 8 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 147
Quoted 4 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +4
-0+ <0x0 0x1404000 0 0x2000>, /* GICH */ + <0x0 0x1406000 0 0x2000>; /* GICV */ + interrupts = <1 9 0xf08>; + };The recently posted ls2080 device tree patch puts pmu, gic, etc. under the root node rather than the soc node. Where should they go? At least it should be consistent...
Why treat pmu, gic and timer as special? Who can explain it?
I find some venders put the gic and/or timer node under the soc node, such as arch/arm64/boot/dts/marvell/berlin4ct.dtsi, arch/arm64/boot/dts/mediatek/mt8173.dtsi and arch/arm64/boot/dts/qcom/msm8916.dtsi.
So I put them underneath the soc node.
Thanks,
Zhiqiang
PATCH v4 4/6 arm64/ls1043a: add DTS for Freescale LS1043A SoC
Quoted 234 lines
From: Hou Zhiqiang-B48286
Sent: Friday, October 16, 2015 9:07 AMQuoted 52 lines
-----Original Message-----
From: Wood Scott-B07421
Sent: 2015?10?16? 4:46
To: Hou Zhiqiang-B48286
Cc: linux-arm-kernel at lists.infradead.org; catalin.marinas at arm.com; will.deacon at arm.com; linux-i2c at vger.kernel.org; linux- watchdog at vger.kernel.org; linux-doc at vger.kernel.org; linux- clk at vger.kernel.org; mark.rutland at arm.com; linux at roeck-us.net; wsa at the- dreams.de; wim at iguana.be; corbet at lwn.net; mturquette at baylibre.com; sboyd at codeaurora.org; Hu Mingkai-B21284; Xie Shaohui-B21989; Sharma Bhupesh-B45370; Song Wenbin-B53747; Li Yang-Leo-R58472; Sharma Bhupesh-
B45370
Subject: Re: [PATCH V4 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoCQuoted 35 lines · Zhiqiang Hou
From: Mingkai Hu <[email protected]>
LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks similar to LS1021a which complies to Chassis 2.1 spec.
Following levels of DTSI/DTS files have been created for the LS1043A SoC family:
-
fsl-ls1043a.dtsi:
DTS-Include file for FSL LS1043A SoC.Signed-off-by Li Yang <[email protected]>Signed-off-by Hou Zhiqiang <[email protected]>Signed-off-by Mingkai Hu <[email protected]>Signed-off-by Wenbin Song <[email protected]>---
V4:
- Add soc node with simple-bus compatible.
- Add property interrupt-affinity for armv8 pmuv3 node.V3:
- Add device tree node for SATA.
- Remove properity enable-method for all cpu node. Remove reserved memory region for spin-table.V2:
- Add secondary core boot method.
- Move out the sysclk node from the clockgen node.
- Correct the reg size of GICC.arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 525 +++++++++++++++++++++++++ 1 file changed, 525 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsiQuoted 9 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 2
Quoted 9 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +2
-0@@ -0,0 +1,525 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A familySoC.
Quoted 6 lines
Quoted 6 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +6
-0+ * + * Copyright 2014-2015, Freescale Semiconductor + * + * Mingkai Hu <[email protected]> + * + * This file is dual-licensed: you can use it either under theQuoted 8 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
Quoted 8 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +8
-0+terms + * of the GPLv2 or the X11 license, at your option. Note that this +dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licenseas
Quoted 1 line
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 17
Quoted 1 line
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +1
-0+ * published by the Free Software Foundation; either version 2of
Quoted 4 lines
the
Quoted 3 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +3
-0+ * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will beuseful,
Quoted 1 line
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 21
Quoted 1 line
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +1
-0+ * but WITHOUT ANY WARRANTY; without even the implied warrantyof
Quoted 7 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
Quoted 7 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +7
-0+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associateddocumentation
Quoted 4 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +4
-0+ * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whomthe
Quoted 4 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +4
-0+ * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shallbe
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 37
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +1
-0+ * included in all copies or substantial portions of theSoftware.
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 39
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +2
-0+ * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANYKIND,
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 40
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +1
-0+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THEWARRANTIES
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +10
-0+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + compatible = "fsl,ls1043a";arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +10
-0+ interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* + * We expect the enable-method for cpu's to be "psci",but this
Quoted 53 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +53
-0+ * is dependent on the SoC FW, which will fill this in. + * + * Currently supported enable-method is psci v0.2 + */ + cpu0: cpu at 0{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + clocks = <&clockgen 1 0>; + }; + + cpu1: cpu at 1{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + clocks = <&clockgen 1 0>; + }; + + cpu2: cpu at 2{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + clocks = <&clockgen 1 0>; + }; + + cpu3: cpu at 3{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + clocks = <&clockgen 1 0>; + }; + }; + + memory at 80000000{ + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + /* DRAM space 1, size: 2GiB DRAM */ + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clockgen: clocking at 1ee1000{arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +10
-0+ compatible = "fsl,ls1043a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x1>, /* Physical Secure + PPI*/
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 125
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +2
-0+ <1 14 0x1>, /* Physical + Non-SecurePPI */
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +22
-0+ <1 11 0x1>, /* Virtual PPI */ + <1 10 0x1>; /* Hypervisor PPI */ + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 106 0x4>, + <0 107 0x4>, + <0 95 0x4>, + <0 97 0x4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + gic: interrupt-controller at 1400000{ + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0 0x1000>, /* GICD */ + <0x0 0x1402000 0 0x2000>, /* GICC */Quoted 8 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 147
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +4
-0+ <0x0 0x1404000 0 0x2000>, /* GICH */ + <0x0 0x1406000 0 0x2000>; /* GICV */ + interrupts = <1 9 0xf08>; + };The recently posted ls2080 device tree patch puts pmu, gic, etc. under the root node rather than the soc node. Where should they go? At least it should be consistent...
Quoted 6 lines
Why treat pmu, gic and timer as special? Who can explain it? I find some venders put the gic and/or timer node under the soc node, such as
arch/arm64/boot/dts/marvell/berlin4ct.dtsi,arch/arm64/boot/dts/mediatek/mt8173.dtsiandarch/arm64/boot/dts/qcom/msm8916.dtsi.
So I put them underneath the soc node.
As you said it depends on your SOC architecture and bus layout.
1. ARMv8 timer is a per-core timer with a global timebase, so it doesn't make much sense to place it under /soc node as we don't keep /cpus under the /soc node as well
2. Similarly for GIC and Timer.
However, your SoC bus layout might be different. So if you have exact idea of the bus layout for your SoC, better to use exact names like AHB, APB and AXI.
Refer to IMX28 bus organization example (slide 24/45) in 'device-tree for dummies pdf' [1]
[1] https://events.linuxfoundation.org/sites/events/files/slides/petazzoni-device-tree-dummies.pdf
PATCH v4 4/6 arm64/ls1043a: add DTS for Freescale LS1043A SoC
Quoted 270 lines
-----Original Message-----
From: Sharma Bhupesh-B45370
Sent: 2015?10?16? 13:12
To: Hou Zhiqiang-B48286; Wood Scott-B07421
Cc: linux-arm-kernel at lists.infradead.org; catalin.marinas at arm.com; will.deacon at arm.com; linux-i2c at vger.kernel.org; linux-
watchdog at vger.kernel.org; linux-doc at vger.kernel.org; linux-
clk at vger.kernel.org; mark.rutland at arm.com; linux at roeck-us.net; wsa at the- dreams.de; wim at iguana.be; corbet at lwn.net; mturquette at baylibre.com; sboyd at codeaurora.org; Hu Mingkai-B21284; Xie Shaohui-B21989; Song Wenbin- B53747; Li Yang-Leo-R58472
Subject: RE: [PATCH V4 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoCQuoted 66 lines
From: Hou Zhiqiang-B48286
Sent: Friday, October 16, 2015 9:07 AMQuoted 52 lines
-----Original Message-----
From: Wood Scott-B07421
Sent: 2015?10?16? 4:46
To: Hou Zhiqiang-B48286
Cc: linux-arm-kernel at lists.infradead.org; catalin.marinas at arm.com; will.deacon at arm.com; linux-i2c at vger.kernel.org; linux- watchdog at vger.kernel.org; linux-doc at vger.kernel.org; linux- clk at vger.kernel.org; mark.rutland at arm.com; linux at roeck-us.net; wsa at the- dreams.de; wim at iguana.be; corbet at lwn.net; mturquette at baylibre.com; sboyd at codeaurora.org; Hu Mingkai-B21284; Xie Shaohui-B21989; Sharma Bhupesh-B45370; Song Wenbin-B53747; Li Yang-Leo-R58472; Sharma Bhupesh-
B45370
Subject: Re: [PATCH V4 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoCQuoted 35 lines · Zhiqiang Hou
From: Mingkai Hu <[email protected]>
LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks similar to LS1021a which complies to Chassis 2.1 spec.
Following levels of DTSI/DTS files have been created for the LS1043A SoC family:
-
fsl-ls1043a.dtsi:
DTS-Include file for FSL LS1043A SoC.Signed-off-by Li Yang <[email protected]>Signed-off-by Hou Zhiqiang <[email protected]>Signed-off-by Mingkai Hu <[email protected]>Signed-off-by Wenbin Song <[email protected]>---
V4:
- Add soc node with simple-bus compatible.
- Add property interrupt-affinity for armv8 pmuv3 node.V3:
- Add device tree node for SATA.
- Remove properity enable-method for all cpu node. Remove reserved memory region for spin-table.V2:
- Add secondary core boot method.
- Move out the sysclk node from the clockgen node.
- Correct the reg size of GICC.arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 525 +++++++++++++++++++++++++ 1 file changed, 525 insertions(+) create mode 100644
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsiQuoted 9 lines
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +2
-0@@ -0,0 +1,525 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A familySoC.
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +5
-0+ * + * Copyright 2014-2015, Freescale Semiconductor + * + * Mingkai Hu <[email protected]> + *Quoted 8 lines
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +8
-0+ * This file is dual-licensed: you can use it either under the +terms + * of the GPLv2 or the X11 license, at your option. Note that +this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute itand/or
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +1
-0+ * modify it under the terms of the GNU General Public Licenseas
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +1
-0+ * published by the Free Software Foundation; either version 2of
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the
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +3
-0+ * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will beuseful,
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +1
-0+ * but WITHOUT ANY WARRANTY; without even the implied warrantyof
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +1
-0+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. Seethe
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +6
-0+ * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associateddocumentation
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +3
-0+ * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense,and/or
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 32
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +1
-0+ * sell copies of the Software, and to permit persons to whomthe
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +4
-0+ * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shallQuoted 12 lines
be
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 37
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +1
-0+ * included in all copies or substantial portions of theSoftware.
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +2
-0+ * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANYKIND,
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 40
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +1
-0+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THEWARRANTIES
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +4
-0+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,ARISING
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 45
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +1
-0+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USEOR
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +6
-0+ * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + compatible = "fsl,ls1043a"; + interrupt-parent = <&gic>;arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +10
-0+ #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* + * We expect the enable-method for cpu's to be + "psci",but this
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 62
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +1
-0+ * is dependent on the SoC FW, which will fill thisin.
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +52
-0+ * + * Currently supported enable-method is psci v0.2 + */ + cpu0: cpu at 0{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + clocks = <&clockgen 1 0>; + }; + + cpu1: cpu at 1{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + clocks = <&clockgen 1 0>; + }; + + cpu2: cpu at 2{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + clocks = <&clockgen 1 0>; + }; + + cpu3: cpu at 3{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + clocks = <&clockgen 1 0>; + }; + }; + + memory at 80000000{ + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + /* DRAM space 1, size: 2GiB DRAM */ + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clockgen: clocking at 1ee1000{arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +10
-0+ compatible = "fsl,ls1043a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x1>, /* Physical Secure + PPI*/
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 126
Quoted 2 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +2
-0+ <1 14 0x1>, /* Physical + Non-SecurePPI */
Quoted 22 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +22
-0+ <1 11 0x1>, /* Virtual PPI */ + <1 10 0x1>; /* Hypervisor PPI */ + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 106 0x4>, + <0 107 0x4>, + <0 95 0x4>, + <0 97 0x4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + gic: interrupt-controller at 1400000{ + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0 0x1000>, /* GICD */ + <0x0 0x1402000 0 0x2000>, /* GICC */Quoted 8 lines
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi line 147
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file +4
-0+ <0x0 0x1404000 0 0x2000>, /* GICH */ + <0x0 0x1406000 0 0x2000>; /* GICV */ + interrupts = <1 9 0xf08>; + };The recently posted ls2080 device tree patch puts pmu, gic, etc. under the root node rather than the soc node. Where should they go? At least it should be consistent...
Quoted 6 lines
Why treat pmu, gic and timer as special? Who can explain it? I find some venders put the gic and/or timer node under the soc node, such as
arch/arm64/boot/dts/marvell/berlin4ct.dtsi,arch/arm64/boot/dts/mediatek/mt8173.dtsiandarch/arm64/boot/dts/qcom/msm8916.dtsi.
So I put them underneath the soc node.As you said it depends on your SOC architecture and bus layout.
1. ARMv8 timer is a per-core timer with a global timebase, so it doesn't make much sense to place it under /soc node as we don't keep /cpus under the /soc node as well
Quoted 6 lines
2. Similarly for GIC and Timer.
However, your SoC bus layout might be different. So if you have exact idea of the bus layout for your SoC, better to use exact names like AHB, APB and AXI.
Thanks for your clarify.
Quoted 6 lines
Refer to IMX28 bus organization example (slide 24/45) in 'device-tree for dummies pdf' [1]
[1]
https://events.linuxfoundation.org/sites/events/files/slides/petazzoni-
device-tree-dummies.pdf
Thanks,
Zhiqiang
PATCH v4 5/6 clk: qoriq: Add ls1043a support.
In reply to Zhiqiang HouFrom: Hou Zhiqiang <[email protected]>
---
This patch has been acked in V3 by Stephen Boyd [sboyd at codeaurora.org].
V4: V3 V2
- No change.
drivers/clk/clk-qoriq.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+)
drivers/clk/clk-qoriq.c +38 -0
@@ -244,6 +244,28 @@ static const struct clockgen_muxinfo clockgen2_cmux_cgb = { }, }; +static const struct clockgen_muxinfo ls1043a_hwa1 = { + { + {}, + {}, + {CLKSEL_VALID ,CGA_PLL1 ,PLL_DIV2 }, + {CLKSEL_VALID ,CGA_PLL1 ,PLL_DIV3 }, + {}, + {}, + {CLKSEL_VALID ,CGA_PLL2 ,PLL_DIV2 }, + {CLKSEL_VALID ,CGA_PLL2 ,PLL_DIV3 }, + }, +}; + +static const struct clockgen_muxinfo ls1043a_hwa2 = { + { + {}, + {CLKSEL_VALID ,CGA_PLL2 ,PLL_DIV1 }, + {}, + {CLKSEL_VALID ,CGA_PLL2 ,PLL_DIV3 }, + }, +}; +static const struct clockgen_muxinfo t1023_hwa1 = { { {},
@@ -452,6 +474,21 @@ static const struct clockgen_chipinfo chipinfo[] = { .pll_mask = 0x03, }, { + .compat = "fsl,ls1043a-clockgen", + .init_periph = t2080_init_periph, + .cmux_groups = { + &t1040_cmux + }, + .hwaccel = { + &ls1043a_hwa1, &ls1043a_hwa2 + }, + .cmux_to_group = { +0 ,-1 + }, + .pll_mask = 0x07, + .flags = CG_PLL_8BIT, + }, + { .compat ="fsl,ls2080a-clockgen" , .cmux_groups = { &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
@@ -1227,6 +1264,7 @@ err:CLK_OF_DECLARE (qoriq_clockgen_1,"fsl,qoriq-clockgen-1.0" , clockgen_init);CLK_OF_DECLARE (qoriq_clockgen_2,"fsl,qoriq-clockgen-2.0" , clockgen_init);CLK_OF_DECLARE (qoriq_clockgen_ls1021a,"fsl,ls1021a-clockgen" , clockgen_init); +CLK_OF_DECLARE (qoriq_clockgen_ls1043a,"fsl,ls1043a-clockgen" , clockgen_init);CLK_OF_DECLARE (qoriq_clockgen_ls2080a,"fsl,ls2080a-clockgen" , clockgen_init);/* Legacy nodes */
Signature · 1 line
2.1.0.27.g96db324
PATCH v4 5/6 clk: qoriq: Add ls1043a support.
Quoted 5 lines · Zhiqiang Hou
From: Hou Zhiqiang <[email protected]>
Signed-off-by Hou Zhiqiang <[email protected]>---
This patch has been acked in V3 by Stephen Boyd [sboyd at codeaurora.org].
Yes, please add it into the patches that you send instead of putting it below the --- line.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v4 5/6 clk: qoriq: Add ls1043a support.
Quoted 16 lines
-----Original Message-----
From: Stephen Boyd [mailto:sboyd at codeaurora.org]
Sent: 2015?10?16? 2:02
To: Hou Zhiqiang-B48286
Cc: linux-arm-kernel at lists.infradead.org; catalin.marinas at arm.com; will.deacon at arm.com; linux-i2c at vger.kernel.org; linux-
watchdog at vger.kernel.org; linux-doc at vger.kernel.org; linux-
clk at vger.kernel.org; mark.rutland at arm.com; linux at roeck-us.net; wsa at the- dreams.de; wim at iguana.be; corbet at lwn.net; mturquette at baylibre.com; Hu Mingkai-B21284; Xie Shaohui-B21989; Wood Scott-B07421; Sharma Bhupesh- B45370; Song Wenbin-B53747
Subject: Re: [PATCH V4 5/6] clk: qoriq: Add ls1043a support.On 10/15, Zhiqiang Hou wrote:
Quoted 8 lines
Quoted 5 lines
From: Hou Zhiqiang <[email protected]>
Signed-off-by Hou Zhiqiang <[email protected]>---
This patch has been acked in V3 by Stephen Boyd [sboyd at codeaurora.org].Yes, please add it into the patches that you send instead of putting it below the --- line.
Ok, thanks.
Zhiqiang
PATCH v4 6/6 dts/ls1043a: add LS1043ARDB board support
In reply to Zhiqiang HouFrom: Shaohui Xie <[email protected]>
---
V4: V3
- No change.
V2:
- Remove the useless compatible "simple-bus" from cpld node.
arch/arm64/boot/dts/freescale/Makefile | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 116 ++++++++++++++++++++++ 2 files changed, 117 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
arch/arm64/boot/dts/freescale/Makefile +1 -1
@@ -1,4 +1,4 @@ -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb fsl-ls2080a-rdb.dtb fsl-ls2080a-simu.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb fsl-ls2080a-rdb.dtb fsl-ls2080a-simu.dtb fsl-ls1043a-rdb.dtb always := $(dtb-y) subdir-y := $(dts-dirs)
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts new file +116 -0
116 lines not on this page · raw message
Signature · 1 line
2.1.0.27.g96db324