nios2: convert cache flush to use dm cpu data

PATCH Superseded Thomas Chou 2 participants 5 messages Oct 14, 2015 – Oct 18, 2015 1 message not in the archive NIOS2 architecture

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Thomas Chou

author

2015-10-14 01:38 UTC #1 lore raw

PATCH v3 1/1 nios2: convert cache flush to use dm cpu data

Convert cache flush to use dm cpu data.

The original cache flush functions are written in assembly and use CONFIG_SYS_{I,D}CACHE_SIZE... macros. It is difficult to convert to use cache configuration in dm cpu data which is extracted from device tree.

The cacheflush.c of Linux nios2 arch uses cpuinfo structure, which is very close to our dm cpu data. So we copy and modify it to arch/nios2/lib/cache.c to replace the old cache.S.

Signed-off-by Thomas Chou <[email protected]>

---
v2
change commit message.
v3
check initda instruction support.
add invalidate_dcache_range().

 arch/nios2/include/asm/cache.h |  13 ++---
 arch/nios2/lib/bootm.c         |   6 +--
 arch/nios2/lib/cache.S         |  68 ------------------------
 arch/nios2/lib/cache.c         | 114 +++++++++++++++++++++++++++++++++++++++++
 4 files changed, 118 insertions(+), 83 deletions(-)
 delete mode 100644 arch/nios2/lib/cache.S
 create mode 100644 arch/nios2/lib/cache.c

arch/nios2/include/asm/cache.h +3 ~~-10~~

index 9b87c9f..dde43cd 100644
@@ -8,18 +8,11 @@
 #ifndef __ASM_NIOS2_CACHE_H_
 #define __ASM_NIOS2_CACHE_H_
 
-extern void flush_dcache (unsigned long start, unsigned long size);
-extern void flush_icache (unsigned long start, unsigned long size);
-
 /*
- * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16, and 32
- * bytes.  If the board configuration has not specified one we default to the
- * largest of these values for alignment of DMA buffers.
+ * Valid L1 data cache line sizes for the NIOS2 architecture are 4,
+ * 16, and 32 bytes. We default to the largest of these values for
+ * alignment of DMA buffers.
  */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
-#else
 #define ARCH_DMA_MINALIGN	32
-#endif
 
 #endif /* __ASM_NIOS2_CACHE_H_ */

arch/nios2/lib/bootm.c +1 -5

index c730a3f..4e5c269 100644
@@ -6,9 +6,6 @@
  */
 
 #include <common.h>
-#include <command.h>
-#include <asm/byteorder.h>
-#include <asm/cache.h>
 
 #define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */

@@ -40,8 +37,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
 
 	/* flushes data and instruction caches before calling the kernel */
 	disable_interrupts();
-	flush_dcache((ulong)kernel, CONFIG_SYS_DCACHE_SIZE);
-	flush_icache((ulong)kernel, CONFIG_SYS_ICACHE_SIZE);
+	flush_dcache_all();
 
 	debug("bootargs=%s @ 0x%lx\n", commandline, (ulong)&commandline);
 	debug("initrd=0x%lx-0x%lx\n", (ulong)initrd_start, (ulong)initrd_end);

arch/nios2/lib/cache.S deleted +0 ~~-68~~

68 lines not on this page · raw message

arch/nios2/lib/cache.c new file +114 -0

114 lines not on this page · raw message

Signature · 1 line

2.1.4

Marek Vasut

2015-10-16 23:00 UTC #2 lore raw

PATCH v3 1/1 nios2: convert cache flush to use dm cpu data

Quoted 7 lines · Thomas Chou

Convert cache flush to use dm cpu data.
The original cache flush functions are written in assembly and use CONFIG_SYS_{I,D}CACHE_SIZE... macros. It is difficult to convert to use cache configuration in dm cpu data which is extracted from device tree.

Quoted 5 lines

The cacheflush.c of Linux nios2 arch uses cpuinfo structure, which is very close to our dm cpu data. So we copy and modify it to arch/nios2/lib/cache.c to replace the old cache.S.
Signed-off-by Thomas Chou <[email protected]>

Hi!

[...]

arch/nios2/lib/cache.c line 20

Quoted 7 lines

arch/nios2/lib/cache.c new file +7 -0

+static void __flush_dcache(unsigned long start, unsigned long end)
+{
+	unsigned long addr;
+
+	start &= ~(gd->arch.dcache_line_size - 1);
+	end += (gd->arch.dcache_line_size - 1);
+	end &= ~(gd->arch.dcache_line_size - 1);

I really don't think we should do this alignment here :-(

arch/nios2/lib/cache.c line 28

Quoted 7 lines

arch/nios2/lib/cache.c new file +7 -0

+	for (addr = start; addr < end; addr += gd->arch.dcache_line_size) {
+		__asm__ __volatile__ ("   flushda 0(%0)\n"
+					: /* Outputs */
+					: /* Inputs  */ "r"(addr)
+					/* : No clobber */);
+	}
+}

[...]

Best regards,
Marek Vasut

Thomas Chou

author

2015-10-17 06:54 UTC #3 lore raw

PATCH v3 1/1 nios2: convert cache flush to use dm cpu data

Hi Marek,

Quoted 9 lines · Marek Vasut

arch/nios2/lib/cache.c line 20
Quoted 7 lines
arch/nios2/lib/cache.c new file +7 -0
+static void __flush_dcache(unsigned long start, unsigned long end)
+{
+	unsigned long addr;
+
+	start &= ~(gd->arch.dcache_line_size - 1);
+	end += (gd->arch.dcache_line_size - 1);
+	end &= ~(gd->arch.dcache_line_size - 1);
I really don't think we should do this alignment here :-(

The rounding to get flush range is necessary to keep it confirm to the interface defined in linux/Documentation/cachetlb.txt.

Removing the rounding and adding "range check and keep" is a violation to the common interface.

You cannot agree to the common interface and, at the same time, insist on changing the definition by your own.

Best regards,
Thomas

Marek Vasut

2015-10-17 11:52 UTC #4 lore raw

PATCH v3 1/1 nios2: convert cache flush to use dm cpu data

Quoted 1 line · Thomas Chou

Hi Marek,

Hi!

Quoted 11 lines · Marek Vasut

Quoted 9 lines
arch/nios2/lib/cache.c line 20
Quoted 7 lines
arch/nios2/lib/cache.c new file +7 -0
+static void __flush_dcache(unsigned long start, unsigned long end)
+{
+	unsigned long addr;
+
+	start &= ~(gd->arch.dcache_line_size - 1);
+	end += (gd->arch.dcache_line_size - 1);
+	end &= ~(gd->arch.dcache_line_size - 1);
I really don't think we should do this alignment here :-(

Quoted 8 lines

The rounding to get flush range is necessary to keep it confirm to the interface defined in linux/Documentation/cachetlb.txt.
Removing the rounding and adding "range check and keep" is a violation to the common interface.
You cannot agree to the common interface and, at the same time, insist on changing the definition by your own.

I agree we should strive for such an interface, but it's not in place yet and there are many nasty places in U-Boot where such an interface is not directly applicable yet. That's why we need some sort of detection of the incorrect addresses used in cache ops, since if I am tracking down some sort of DMA issues and I find that my cache code is hiding them, I'll be really unhappy.

btw. I think most of the U-Boot code has been already fixed, so if you add the cache range checks, they shouldn't trigger too much.

Best regards,
Marek Vasut

Thomas Chou

author

2015-10-18 23:48 UTC #5 lore raw

PATCH v3 1/1 nios2: convert cache flush to use dm cpu data

In reply to Thomas Chou

Quoted 19 lines · Thomas Chou

Convert cache flush to use dm cpu data.
The original cache flush functions are written in assembly and use CONFIG_SYS_{I,D}CACHE_SIZE... macros. It is difficult to convert to use cache configuration in dm cpu data which is extracted from device tree.
The cacheflush.c of Linux nios2 arch uses cpuinfo structure, which is very close to our dm cpu data. So we copy and modify it to arch/nios2/lib/cache.c to replace the old cache.S.
Signed-off-by Thomas Chou <[email protected]>
---
v2
change commit message.
v3
check initda instruction support.
add invalidate_dcache_range().

Quoted 8 lines

  arch/nios2/include/asm/cache.h |  13 ++---
  arch/nios2/lib/bootm.c         |   6 +--
  arch/nios2/lib/cache.S         |  68 ------------------------
  arch/nios2/lib/cache.c         | 114 +++++++++++++++++++++++++++++++++++++++++
  4 files changed, 118 insertions(+), 83 deletions(-)

delete mode 100644 arch/nios2/lib/cache.S
create mode 100644 arch/nios2/lib/cache.c

Applied to u-boot-nios.