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ARM: dts: sun7i: Enable USB DRC on pcDuino v3 Nano

PATCH New Adam Sampson 3 participants 3 messages Oct 17, 2015 – Oct 19, 2015

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Adam Sampson

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#0 lore raw

PATCH 1/1 ARM: dts: sun7i: Enable USB DRC on pcDuino v3 Nano

The OTG arrangement on the LinkSprite pcDuino v3 Nano is the same as the pcDuino 1/2/3: the OTG port's 5V line is connected directly to the 5V bus (it's not switchable), and the OTG port's ID pin is connected to PH4 on the A20.

Tested successfully in both host and device modes.

Signed-off-by Adam Sampson <[email protected]>
---
 arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts +19 -0
index beac431..1757a6a 100644
@@ -142,6 +142,10 @@
 	status = "okay";
 };
 
+&otg_sram {
+	status = "okay";
+};
+
 &pio {
 	ahci_pwr_pin_pcduino3_nano: ahci_pwr_pin at 0 {
 		allwinner,pins = "PH2";

@@ -157,6 +161,13 @@
 		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 	};
 
+	usb0_id_detect_pin: usb0_id_detect_pin at 0 {
+		allwinner,pins = "PH4";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+
 	usb1_vbus_pin_pcduino3_nano: usb1_vbus_pin at 0 {
 		allwinner,pins = "PD2";
 		allwinner,function = "gpio_out";

@@ -211,7 +222,15 @@
 	status = "okay";
 };
 
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
 &usbphy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_id_detect_pin>;
+	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	usb2_vbus-supply = <&reg_usb1_vbus>;
 	status = "okay";
Signature · 1 line
2.1.4
#1 lore raw

PATCH 1/1 ARM: dts: sun7i: Enable USB DRC on pcDuino v3 Nano

Hi,

Quoted 8 lines · Adam Sampson

The OTG arrangement on the LinkSprite pcDuino v3 Nano is the same as the pcDuino 1/2/3: the OTG port's 5V line is connected directly to the 5V bus (it's not switchable), and the OTG port's ID pin is connected to PH4 on the A20.

Tested successfully in both host and device modes.

Signed-off-by Adam Sampson <[email protected]>

Looks good: Acked-by: Hans de Goede <[email protected]>

Regards,

Hans

Quoted 50 lines
---
  arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 19 +++++++++++++++++++
  1 file changed, 19 insertions(+)
arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts +19 -0
index beac431..1757a6a 100644
@@ -142,6 +142,10 @@
  	status = "okay";
  };
 
+&otg_sram {
+	status = "okay";
+};
+
  &pio {
  	ahci_pwr_pin_pcduino3_nano: ahci_pwr_pin at 0 {
  		allwinner,pins = "PH2";

@@ -157,6 +161,13 @@
  		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  	};
 
+	usb0_id_detect_pin: usb0_id_detect_pin at 0 {
+		allwinner,pins = "PH4";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+
  	usb1_vbus_pin_pcduino3_nano: usb1_vbus_pin at 0 {
  		allwinner,pins = "PD2";
  		allwinner,function = "gpio_out";

@@ -211,7 +222,15 @@
  	status = "okay";
  };
 
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
  &usbphy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_id_detect_pin>;
+	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
  	usb1_vbus-supply = <&reg_usb1_vbus>;
  	usb2_vbus-supply = <&reg_usb1_vbus>;
  	status = "okay";
Applied
#2 lore raw

PATCH 1/1 ARM: dts: sun7i: Enable USB DRC on pcDuino v3 Nano

In reply to Adam Sampson
Quoted 8 lines · Adam Sampson

The OTG arrangement on the LinkSprite pcDuino v3 Nano is the same as the pcDuino 1/2/3: the OTG port's 5V line is connected directly to the 5V bus (it's not switchable), and the OTG port's ID pin is connected to PH4 on the A20.

Tested successfully in both host and device modes.

Signed-off-by Adam Sampson <[email protected]>

Applied, thanks!
Maxime

Signature · 10 lines
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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