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igep00x0: Use BCH8 ECC

PATCH In review Ladislav Michl 3 participants 3 messages Oct 12, 2015 – Oct 20, 2015

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Ladislav Michl

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#0 lore raw

PATCH 1/1 igep00x0: Use BCH8 ECC

Used NAND chips requires at least 4-bit error correction, so use BCH8 as it is what kernel uses.

Signed-off-by Ladislav Michl <[email protected]>
---
 omap3_igep00x0.h |   18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)
include/configs/omap3_igep00x0.h +13 -5
index 4409103..cf2bc3e 100644
@@ -160,12 +160,20 @@
 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
 #define CONFIG_SYS_NAND_OOBSIZE		64
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
-#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
-						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2,  3,  4,  5,  6,  7,  8,  9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
 #define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_BCH
+
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 /* NAND: SPL falcon mode configs */
 #ifdef CONFIG_SPL_OS_BOOT
#2 lore raw
In reply to Ladislav Michl
Quoted 5 lines · Ladislav Michl

Used NAND chips requires at least 4-bit error correction, so use BCH8 as it is what kernel uses.

Signed-off-by Ladislav Michl <[email protected]>
Acked-by Javier Martinez Canillas <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines
Tom
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