Add board detection for Odroid XU3 / XU3Lite / XU4

The CPU name for Exynos was concatenated with cpu id, but for new Exynos platforms, like Chromebook Peach Pi based on Exynos5800, the name of SoC variant does not include the real SoC cpu id (0x5422).

For such case, the CPU name should be defined by the config file.

This commit introduces new config:
- CONFIG_CPU_NAME - with cpu name string

If defined, then the cpu id is not printed.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
 arch/arm/cpu/armv7/s5p-common/cpu_info.c | 5 +++++
 1 file changed, 5 insertions(+)

arch/arm/cpu/armv7/s5p-common/cpu_info.c +0 -0

index 154d674..9b125a3 100644

arch/arm/cpu/armv7/s5p-common/cpu_info.c +0 -1

        print_freq(get_arm_clk(), "\n");
 
        return 0;
--

1.9.1

Hi Przemyslaw,

Quoted 27 lines · Przemyslaw Marczak

The CPU name for Exynos was concatenated with cpu id, but for new Exynos platforms, like Chromebook Peach Pi based on Exynos5800, the name of SoC variant does not include the real SoC cpu id (0x5422).

For such case, the CPU name should be defined by the config file.

This commit introduces new config:
- CONFIG_CPU_NAME - with cpu name string

If defined, then the cpu id is not printed.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
  arch/arm/cpu/armv7/s5p-common/cpu_info.c | 5 +++++
  1 file changed, 5 insertions(+)

arch/arm/cpu/armv7/s5p-common/cpu_info.c +1 -0

index 154d674..9b125a3 100644
@@ -30,7 +30,12 @@ u32 get_device_type(void)
  #ifdef CONFIG_DISPLAY_CPUINFO
  int print_cpuinfo(void)
  {
+/* For SoC with no real CPU ID in naming convention. */

arch/arm/cpu/armv7/s5p-common/cpu_info.c u32 get_device_type(void) · line 38

Quoted 5 lines

arch/arm/cpu/armv7/s5p-common/cpu_info.c +4 -0

+#ifdef CONFIG_CPU_NAME
+       printf("CPU:   %s @ ", CONFIG_CPU_NAME);
+#else
         printf("CPU:   %s%X @ ", s5p_get_cpu_name(), s5p_cpu_id);
+#endif

This adds a new CONFIG option - we should be trying to keep the code common. Does it print 5422 instead of 5800?

I'd suggest, either:

a) we don't care, 5422 is fine
b) we grab it from the device tree model or compatible string

Quoted 6 lines

arch/arm/cpu/armv7/s5p-common/cpu_info.c +0 -1

         print_freq(get_arm_clk(), "\n");
 
         return 0;
--

1.9.1

Regards,
Simon

The proper CPU ID for those Exynos variants is 0x5422, but before the 0x5800 was set. This commit fix this back.

Changes:
- set cpu id to 0x5422 instead of 0x5800
- remove macro proid_is_exynos5800()
- add macro proid_is_exynos5422()
- change the calls to proid_is_exynos5800() with new macro

Signed-off-by Przemyslaw Marczak <[email protected]>

---
 arch/arm/mach-exynos/clock.c              | 16 ++++++++--------
 arch/arm/mach-exynos/clock_init_exynos5.c |  2 +-
 arch/arm/mach-exynos/common_setup.h       |  4 ++--
 arch/arm/mach-exynos/include/mach/cpu.h   |  6 +++---
 arch/arm/mach-exynos/include/mach/gpio.h  |  4 ++--
 arch/arm/mach-exynos/pinmux.c             |  2 +-
 arch/arm/mach-exynos/power.c              |  2 +-
 7 files changed, 18 insertions(+), 18 deletions(-)

This driver allows I/O operations on the Samsung S2MPS11 PMIC, which provides lots of LDO/BUCK outputs.

To enable it, update defconfig with:
- CONFIG_DM_PMIC_S2MPS11
and additional, if were not defined:
- CONFIG_CMD_PMIC
- CONFIG_ERRNO_STR

The binding info: doc/device-tree-bindings/pmic/s2mps11.txt

Signed-off-by Przemyslaw Marczak <[email protected]>

---
 doc/device-tree-bindings/pmic/s2mps11.txt |  17 +++++
 drivers/power/pmic/Kconfig                |  14 ++++
 drivers/power/pmic/Makefile               |   1 +
 drivers/power/pmic/s2mps11.c              |  60 ++++++++++++++++
 include/power/s2mps11.h                   | 109 ++++++++++++++++++++++++++++++
 5 files changed, 201 insertions(+)
 create mode 100644 doc/device-tree-bindings/pmic/s2mps11.txt
 create mode 100644 drivers/power/pmic/s2mps11.c
 create mode 100644 include/power/s2mps11.h

doc/device-tree-bindings/pmic/s2mps11.txt new file +17 -0

new file mode 100644
index 0000000..db8d624
@@ -0,0 +1,17 @@
+SAMSUBNG, S2MPS11 PMIC
+
+This file describes the binding info for the PMIC driver:
+- drivers/power/pmic/s2mps11.c
+
+Required properties:
+- compatible: "samsung,s2mps11-pmic"
+- reg = 0x66
+
+With those two properties, the pmic device can be used for read/write only.
+
+Example:
+
+s2mps11 at 66 {
+       compatible = "samsung,s2mps11-pmic";
+       reg = <0x66>;
+};

drivers/power/pmic/Kconfig +0 -0

index fc6a374..c66b352 100644

drivers/power/pmic/Kconfig +13 -0

+       bool "Enable Driver Model for PMIC Samsung S2MPS11"
+       depends on DM_PMIC
+       ---help---
+       The Samsung S2MPS11 PMIC provides:
+        - 38 adjustable LDO regulators
+        - 9 High-Efficiency Buck Converters
+        - 1 BuckBoost Converter
+        - RTC with two alarms
+        - Backup battery charger
+        - I2C Configuration Interface
+       This driver provides access to I/O interface only.
+       Binding info: doc/device-tree-bindings/pmic/s2mps11.txt
+
 config DM_PMIC_SANDBOX
        bool "Enable Driver Model for emulated Sandbox PMIC "
        depends on DM_PMIC

drivers/power/pmic/Makefile +1 -0

index 99c5778..1b58d98 100644
@@ -8,6 +8,7 @@
 obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
 obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
 obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
+obj-$(CONFIG_DM_PMIC_S2MPS11) += s2mps11.o
 obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
 obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
 obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o

drivers/power/pmic/s2mps11.c new file +60 -0

new file mode 100644
index 0000000..7e28402
@@ -0,0 +1,60 @@
+/*
+ *  Copyright (C) 2015 Samsung Electronics
+ *  Przemyslaw Marczak  <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/s2mps11.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int s2mps11_reg_count(struct udevice *dev)
+{
+       return S2MPS11_REG_COUNT;
+}
+
+static int s2mps11_write(struct udevice *dev, uint reg, const uint8_t *buff,
+                        int len)
+{
+       if (dm_i2c_write(dev, reg, buff, len)) {
+               error("write error to device: %p register: %#x!", dev, reg);
+               return -EIO;
+       }
+
+       return 0;
+}
+
+static int s2mps11_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+       if (dm_i2c_read(dev, reg, buff, len)) {
+               error("read error from device: %p register: %#x!", dev, reg);
+               return -EIO;
+       }
+
+       return 0;
+}
+
+static struct dm_pmic_ops s2mps11_ops = {
+       .reg_count = s2mps11_reg_count,
+       .read = s2mps11_read,
+       .write = s2mps11_write,
+};
+
+static const struct udevice_id s2mps11_ids[] = {
+       { .compatible = "samsung,s2mps11-pmic" },
+       { }
+};
+
+U_BOOT_DRIVER(pmic_s2mps11) = {
+       .name = "s2mps11_pmic",
+       .id = UCLASS_PMIC,
+       .of_match = s2mps11_ids,
+       .ops = &s2mps11_ops,
+};

include/power/s2mps11.h new file +0 -0

new file mode 100644
index 0000000..885a816

include/power/s2mps11.h new file +108 -1

+#define __INCLUDE__S2MPS11__H__
+
+enum s2mps11_reg {
+       S2MPS11_REG_ID = 0,
+       S2MPS11_REG_INT1,
+       S2MPS11_REG_INT2,
+       S2MPS11_REG_INT3,
+       S2MPS11_REG_INT1M,
+       S2MPS11_REG_INT2M,
+       S2MPS11_REG_INT3M,
+       S2MPS11_REG_STATUS1,
+       S2MPS11_REG_STATUS2,
+       S2MPS11_REG_OFFSRC,
+       S2MPS11_REG_PWRONSRC,
+       S2MPS11_REG_RTC_CTRL,
+       S2MPS11_REG_CTRL1,
+       S2MPS11_REG_ETC_TEST,
+       S2MPS11_REG_RSVD3,
+       S2MPS11_REG_BU_CHG,
+       S2MPS11_REG_RAMP,
+       S2MPS11_REG_RAMP_BUCK,
+       S2MPS11_REG_LDO1_8,
+       S2MPS11_REG_LDO9_16,
+       S2MPS11_REG_LDO17_24,
+       S2MPS11_REG_LDO25_32,
+       S2MPS11_REG_LDO33_38,
+       S2MPS11_REG_LDO1_8_OVC,
+       S2MPS11_REG_LDO9_16_OVC,
+       S2MPS11_REG_LDO17_24_OVC,
+       S2MPS11_REG_LDO25_32_OVC,
+       S2MPS11_REG_LDO33_38_OVC,
+       S2MPS11_REG_RESERVED1,
+       S2MPS11_REG_RESERVED2,
+       S2MPS11_REG_RESERVED3,
+       S2MPS11_REG_RESERVED4,
+       S2MPS11_REG_RESERVED5,
+       S2MPS11_REG_RESERVED6,
+       S2MPS11_REG_RESERVED7,
+       S2MPS11_REG_RESERVED8,
+       S2MPS11_REG_WDRSTEN_CTRL,
+       S2MPS11_REG_B1CTRL1,
+       S2MPS11_REG_B1CTRL2,
+       S2MPS11_REG_B2CTRL1,
+       S2MPS11_REG_B2CTRL2,
+       S2MPS11_REG_B3CTRL1,
+       S2MPS11_REG_B3CTRL2,
+       S2MPS11_REG_B4CTRL1,
+       S2MPS11_REG_B4CTRL2,
+       S2MPS11_REG_B5CTRL1,
+       S2MPS11_REG_BUCK5_SW,
+       S2MPS11_REG_B5CTRL2,
+       S2MPS11_REG_B5CTRL3,
+       S2MPS11_REG_B5CTRL4,
+       S2MPS11_REG_B5CTRL5,
+       S2MPS11_REG_B6CTRL1,
+       S2MPS11_REG_B6CTRL2,
+       S2MPS11_REG_B7CTRL1,
+       S2MPS11_REG_B7CTRL2,
+       S2MPS11_REG_B8CTRL1,
+       S2MPS11_REG_B8CTRL2,
+       S2MPS11_REG_B9CTRL1,
+       S2MPS11_REG_B9CTRL2,
+       S2MPS11_REG_B10CTRL1,
+       S2MPS11_REG_B10CTRL2,
+       S2MPS11_REG_L1CTRL,
+       S2MPS11_REG_L2CTRL,
+       S2MPS11_REG_L3CTRL,
+       S2MPS11_REG_L4CTRL,
+       S2MPS11_REG_L5CTRL,
+       S2MPS11_REG_L6CTRL,
+       S2MPS11_REG_L7CTRL,
+       S2MPS11_REG_L8CTRL,
+       S2MPS11_REG_L9CTRL,
+       S2MPS11_REG_L10CTRL,
+       S2MPS11_REG_L11CTRL,
+       S2MPS11_REG_L12CTRL,
+       S2MPS11_REG_L13CTRL,
+       S2MPS11_REG_L14CTRL,
+       S2MPS11_REG_L15CTRL,
+       S2MPS11_REG_L16CTRL,
+       S2MPS11_REG_L17CTRL,
+       S2MPS11_REG_L18CTRL,
+       S2MPS11_REG_L19CTRL,
+       S2MPS11_REG_L20CTRL,
+       S2MPS11_REG_L21CTRL,
+       S2MPS11_REG_L22CTRL,
+       S2MPS11_REG_L23CTRL,
+       S2MPS11_REG_L24CTRL,
+       S2MPS11_REG_L25CTRL,
+       S2MPS11_REG_L26CTRL,
+       S2MPS11_REG_L27CTRL,
+       S2MPS11_REG_L28CTRL,
+       S2MPS11_REG_L29CTRL,
+       S2MPS11_REG_L30CTRL,
+       S2MPS11_REG_L31CTRL,
+       S2MPS11_REG_L32CTRL,
+       S2MPS11_REG_L33CTRL,
+       S2MPS11_REG_L34CTRL,
+       S2MPS11_REG_L35CTRL,
+       S2MPS11_REG_L36CTRL,
+       S2MPS11_REG_L37CTRL,
+       S2MPS11_REG_L38CTRL,
+       S2MPS11_REG_COUNT,
+};
+
+#define S2MPS11_LDO26_ENABLE   0xec
+
+#endif
--

1.9.1

Quoted 19 lines · Przemyslaw Marczak

This driver allows I/O operations on the Samsung S2MPS11 PMIC, which provides lots of LDO/BUCK outputs.

To enable it, update defconfig with:
- CONFIG_DM_PMIC_S2MPS11
and additional, if were not defined:
- CONFIG_CMD_PMIC
- CONFIG_ERRNO_STR

The binding info: doc/device-tree-bindings/pmic/s2mps11.txt

Signed-off-by Przemyslaw Marczak <[email protected]>

---
  doc/device-tree-bindings/pmic/s2mps11.txt |  17 +++++
  drivers/power/pmic/Kconfig                |  14 ++++
  drivers/power/pmic/Makefile               |   1 +
  drivers/power/pmic/s2mps11.c              |  60 ++++++++++++++++
  include/power/s2mps11.h                   | 109 ++++++++++++++++++++++++++++++
  5 files changed, 201 insertions(+)

Quoted 3 lines

create mode 100644 doc/device-tree-bindings/pmic/s2mps11.txt create mode 100644 drivers/power/pmic/s2mps11.c create mode 100644 include/power/s2mps11.h

Reviewed-by Simon Glass <[email protected]>

(2 nits below)

Quoted 32 lines

doc/device-tree-bindings/pmic/s2mps11.txt new file +17 -0

new file mode 100644
index 0000000..db8d624
@@ -0,0 +1,17 @@
+SAMSUBNG, S2MPS11 PMIC
+
+This file describes the binding info for the PMIC driver:
+- drivers/power/pmic/s2mps11.c
+
+Required properties:
+- compatible: "samsung,s2mps11-pmic"
+- reg = 0x66
+
+With those two properties, the pmic device can be used for read/write only.
+
+Example:
+
+s2mps11 at 66 {
+       compatible = "samsung,s2mps11-pmic";
+       reg = <0x66>;
+};

drivers/power/pmic/Kconfig +0 -0

index fc6a374..c66b352 100644
@@ -24,6 +24,20 @@ config DM_PMIC_MAX77686
         This config enables implementation of driver-model pmic uclass features
         for PMIC MAX77686. The driver implements read/write operations.
 

drivers/power/pmic/Kconfig config DM_PMIC_MAX77686 · line 27

Quoted 1 line

drivers/power/pmic/Kconfig +1 -0

+config DM_PMIC_S2MPS11

nit: I don't think this should have a DM_ prefix. Remember that all the CONFIG_DM_... options are going to be removed one day. It is intended to select the DM version of a subsystem. In your case you only have a DM version of the driver, so just CONFIG_PMIC_S2MPS11 seems fine.

Quoted 95 lines

drivers/power/pmic/Kconfig +13 -0

+       bool "Enable Driver Model for PMIC Samsung S2MPS11"
+       depends on DM_PMIC
+       ---help---
+       The Samsung S2MPS11 PMIC provides:
+        - 38 adjustable LDO regulators
+        - 9 High-Efficiency Buck Converters
+        - 1 BuckBoost Converter
+        - RTC with two alarms
+        - Backup battery charger
+        - I2C Configuration Interface
+       This driver provides access to I/O interface only.
+       Binding info: doc/device-tree-bindings/pmic/s2mps11.txt
+
  config DM_PMIC_SANDBOX
         bool "Enable Driver Model for emulated Sandbox PMIC "
         depends on DM_PMIC

drivers/power/pmic/Makefile +1 -0

index 99c5778..1b58d98 100644
@@ -8,6 +8,7 @@
  obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
  obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
  obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
+obj-$(CONFIG_DM_PMIC_S2MPS11) += s2mps11.o
  obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
  obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
  obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o

drivers/power/pmic/s2mps11.c new file +60 -0

new file mode 100644
index 0000000..7e28402
@@ -0,0 +1,60 @@
+/*
+ *  Copyright (C) 2015 Samsung Electronics
+ *  Przemyslaw Marczak  <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/s2mps11.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int s2mps11_reg_count(struct udevice *dev)
+{
+       return S2MPS11_REG_COUNT;
+}
+
+static int s2mps11_write(struct udevice *dev, uint reg, const uint8_t *buff,
+                        int len)
+{
+       if (dm_i2c_write(dev, reg, buff, len)) {
+               error("write error to device: %p register: %#x!", dev, reg);
+               return -EIO;
+       }
+
+       return 0;
+}
+
+static int s2mps11_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+       if (dm_i2c_read(dev, reg, buff, len)) {
+               error("read error from device: %p register: %#x!", dev, reg);
+               return -EIO;
+       }
+
+       return 0;
+}
+
+static struct dm_pmic_ops s2mps11_ops = {
+       .reg_count = s2mps11_reg_count,
+       .read = s2mps11_read,
+       .write = s2mps11_write,
+};
+
+static const struct udevice_id s2mps11_ids[] = {
+       { .compatible = "samsung,s2mps11-pmic" },
+       { }
+};
+
+U_BOOT_DRIVER(pmic_s2mps11) = {
+       .name = "s2mps11_pmic",
+       .id = UCLASS_PMIC,
+       .of_match = s2mps11_ids,
+       .ops = &s2mps11_ops,
+};

include/power/s2mps11.h +0 -0

include/power/s2mps11.h line 1

Quoted 6 lines

new file mode 100644
index 0000000..885a816

include/power/s2mps11.h new file +1 -0

@@ -0,0 +1,109 @@
+#ifndef __INCLUDE__S2MPS11__H__

nit: I don't think you need __INCLUDE__ here

Quoted 106 lines

include/power/s2mps11.h new file +106 -0

+#define __INCLUDE__S2MPS11__H__
+
+enum s2mps11_reg {
+       S2MPS11_REG_ID = 0,
+       S2MPS11_REG_INT1,
+       S2MPS11_REG_INT2,
+       S2MPS11_REG_INT3,
+       S2MPS11_REG_INT1M,
+       S2MPS11_REG_INT2M,
+       S2MPS11_REG_INT3M,
+       S2MPS11_REG_STATUS1,
+       S2MPS11_REG_STATUS2,
+       S2MPS11_REG_OFFSRC,
+       S2MPS11_REG_PWRONSRC,
+       S2MPS11_REG_RTC_CTRL,
+       S2MPS11_REG_CTRL1,
+       S2MPS11_REG_ETC_TEST,
+       S2MPS11_REG_RSVD3,
+       S2MPS11_REG_BU_CHG,
+       S2MPS11_REG_RAMP,
+       S2MPS11_REG_RAMP_BUCK,
+       S2MPS11_REG_LDO1_8,
+       S2MPS11_REG_LDO9_16,
+       S2MPS11_REG_LDO17_24,
+       S2MPS11_REG_LDO25_32,
+       S2MPS11_REG_LDO33_38,
+       S2MPS11_REG_LDO1_8_OVC,
+       S2MPS11_REG_LDO9_16_OVC,
+       S2MPS11_REG_LDO17_24_OVC,
+       S2MPS11_REG_LDO25_32_OVC,
+       S2MPS11_REG_LDO33_38_OVC,
+       S2MPS11_REG_RESERVED1,
+       S2MPS11_REG_RESERVED2,
+       S2MPS11_REG_RESERVED3,
+       S2MPS11_REG_RESERVED4,
+       S2MPS11_REG_RESERVED5,
+       S2MPS11_REG_RESERVED6,
+       S2MPS11_REG_RESERVED7,
+       S2MPS11_REG_RESERVED8,
+       S2MPS11_REG_WDRSTEN_CTRL,
+       S2MPS11_REG_B1CTRL1,
+       S2MPS11_REG_B1CTRL2,
+       S2MPS11_REG_B2CTRL1,
+       S2MPS11_REG_B2CTRL2,
+       S2MPS11_REG_B3CTRL1,
+       S2MPS11_REG_B3CTRL2,
+       S2MPS11_REG_B4CTRL1,
+       S2MPS11_REG_B4CTRL2,
+       S2MPS11_REG_B5CTRL1,
+       S2MPS11_REG_BUCK5_SW,
+       S2MPS11_REG_B5CTRL2,
+       S2MPS11_REG_B5CTRL3,
+       S2MPS11_REG_B5CTRL4,
+       S2MPS11_REG_B5CTRL5,
+       S2MPS11_REG_B6CTRL1,
+       S2MPS11_REG_B6CTRL2,
+       S2MPS11_REG_B7CTRL1,
+       S2MPS11_REG_B7CTRL2,
+       S2MPS11_REG_B8CTRL1,
+       S2MPS11_REG_B8CTRL2,
+       S2MPS11_REG_B9CTRL1,
+       S2MPS11_REG_B9CTRL2,
+       S2MPS11_REG_B10CTRL1,
+       S2MPS11_REG_B10CTRL2,
+       S2MPS11_REG_L1CTRL,
+       S2MPS11_REG_L2CTRL,
+       S2MPS11_REG_L3CTRL,
+       S2MPS11_REG_L4CTRL,
+       S2MPS11_REG_L5CTRL,
+       S2MPS11_REG_L6CTRL,
+       S2MPS11_REG_L7CTRL,
+       S2MPS11_REG_L8CTRL,
+       S2MPS11_REG_L9CTRL,
+       S2MPS11_REG_L10CTRL,
+       S2MPS11_REG_L11CTRL,
+       S2MPS11_REG_L12CTRL,
+       S2MPS11_REG_L13CTRL,
+       S2MPS11_REG_L14CTRL,
+       S2MPS11_REG_L15CTRL,
+       S2MPS11_REG_L16CTRL,
+       S2MPS11_REG_L17CTRL,
+       S2MPS11_REG_L18CTRL,
+       S2MPS11_REG_L19CTRL,
+       S2MPS11_REG_L20CTRL,
+       S2MPS11_REG_L21CTRL,
+       S2MPS11_REG_L22CTRL,
+       S2MPS11_REG_L23CTRL,
+       S2MPS11_REG_L24CTRL,
+       S2MPS11_REG_L25CTRL,
+       S2MPS11_REG_L26CTRL,
+       S2MPS11_REG_L27CTRL,
+       S2MPS11_REG_L28CTRL,
+       S2MPS11_REG_L29CTRL,
+       S2MPS11_REG_L30CTRL,
+       S2MPS11_REG_L31CTRL,
+       S2MPS11_REG_L32CTRL,
+       S2MPS11_REG_L33CTRL,
+       S2MPS11_REG_L34CTRL,
+       S2MPS11_REG_L35CTRL,
+       S2MPS11_REG_L36CTRL,
+       S2MPS11_REG_L37CTRL,
+       S2MPS11_REG_L38CTRL,
+       S2MPS11_REG_COUNT,
+};
+
+#define S2MPS11_LDO26_ENABLE   0xec

Quoted 5 lines

include/power/s2mps11.h new file +2 -1

+
+#endif
--

1.9.1

Regards,
Simon

This driver allows I/O operations on the Samsung S2MPS11 PMIC, which provides lots of LDO/BUCK outputs.

To enable it, update defconfig with:
- CONFIG_DM_PMIC_S2MPS11
and additional, if were not defined:
- CONFIG_CMD_PMIC
- CONFIG_ERRNO_STR

The binding info: doc/device-tree-bindings/pmic/s2mps11.txt

Signed-off-by Przemyslaw Marczak <[email protected]>

---
 doc/device-tree-bindings/pmic/s2mps11.txt |  17 +++++
 drivers/power/pmic/Kconfig                |  14 ++++
 drivers/power/pmic/Makefile               |   1 +
 drivers/power/pmic/s2mps11.c              |  60 ++++++++++++++++
 include/power/s2mps11.h                   | 109 ++++++++++++++++++++++++++++++
 5 files changed, 201 insertions(+)
 create mode 100644 doc/device-tree-bindings/pmic/s2mps11.txt
 create mode 100644 drivers/power/pmic/s2mps11.c
 create mode 100644 include/power/s2mps11.h

doc/device-tree-bindings/pmic/s2mps11.txt new file +0 -0

new file mode 100644
index 0000000..db8d624

doc/device-tree-bindings/pmic/s2mps11.txt new file +16 -0

+
+This file describes the binding info for the PMIC driver:
+- drivers/power/pmic/s2mps11.c
+
+Required properties:
+- compatible: "samsung,s2mps11-pmic"
+- reg = 0x66
+
+With those two properties, the pmic device can be used for read/write only.
+
+Example:
+
+s2mps11 at 66 {
+	compatible = "samsung,s2mps11-pmic";
+	reg = <0x66>;
+};

drivers/power/pmic/Kconfig +14 -0

index fc6a374..c66b352 100644
@@ -24,6 +24,20 @@ config DM_PMIC_MAX77686
 	This config enables implementation of driver-model pmic uclass features
 	for PMIC MAX77686. The driver implements read/write operations.
 
+config DM_PMIC_S2MPS11
+	bool "Enable Driver Model for PMIC Samsung S2MPS11"
+	depends on DM_PMIC
+	---help---
+	The Samsung S2MPS11 PMIC provides:
+	 - 38 adjustable LDO regulators
+	 - 9 High-Efficiency Buck Converters
+	 - 1 BuckBoost Converter
+	 - RTC with two alarms
+	 - Backup battery charger
+	 - I2C Configuration Interface
+	This driver provides access to I/O interface only.
+	Binding info: doc/device-tree-bindings/pmic/s2mps11.txt
+
 config DM_PMIC_SANDBOX
 	bool "Enable Driver Model for emulated Sandbox PMIC "
 	depends on DM_PMIC

drivers/power/pmic/Makefile +1 -0

index 99c5778..1b58d98 100644
@@ -8,6 +8,7 @@
 obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
 obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
 obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
+obj-$(CONFIG_DM_PMIC_S2MPS11) += s2mps11.o
 obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
 obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
 obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o

drivers/power/pmic/s2mps11.c new file +60 -0

new file mode 100644
index 0000000..7e28402
@@ -0,0 +1,60 @@
+/*
+ *  Copyright (C) 2015 Samsung Electronics
+ *  Przemyslaw Marczak  <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/s2mps11.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int s2mps11_reg_count(struct udevice *dev)
+{
+	return S2MPS11_REG_COUNT;
+}
+
+static int s2mps11_write(struct udevice *dev, uint reg, const uint8_t *buff,
+			 int len)
+{
+	if (dm_i2c_write(dev, reg, buff, len)) {
+		error("write error to device: %p register: %#x!", dev, reg);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int s2mps11_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+	if (dm_i2c_read(dev, reg, buff, len)) {
+		error("read error from device: %p register: %#x!", dev, reg);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static struct dm_pmic_ops s2mps11_ops = {
+	.reg_count = s2mps11_reg_count,
+	.read = s2mps11_read,
+	.write = s2mps11_write,
+};
+
+static const struct udevice_id s2mps11_ids[] = {
+	{ .compatible = "samsung,s2mps11-pmic" },
+	{ }
+};
+
+U_BOOT_DRIVER(pmic_s2mps11) = {
+	.name = "s2mps11_pmic",
+	.id = UCLASS_PMIC,
+	.of_match = s2mps11_ids,
+	.ops = &s2mps11_ops,
+};

include/power/s2mps11.h new file +99 -0

new file mode 100644
index 0000000..885a816
@@ -0,0 +1,109 @@
+#ifndef __INCLUDE__S2MPS11__H__
+#define __INCLUDE__S2MPS11__H__
+
+enum s2mps11_reg {
+	S2MPS11_REG_ID = 0,
+	S2MPS11_REG_INT1,
+	S2MPS11_REG_INT2,
+	S2MPS11_REG_INT3,
+	S2MPS11_REG_INT1M,
+	S2MPS11_REG_INT2M,
+	S2MPS11_REG_INT3M,
+	S2MPS11_REG_STATUS1,
+	S2MPS11_REG_STATUS2,
+	S2MPS11_REG_OFFSRC,
+	S2MPS11_REG_PWRONSRC,
+	S2MPS11_REG_RTC_CTRL,
+	S2MPS11_REG_CTRL1,
+	S2MPS11_REG_ETC_TEST,
+	S2MPS11_REG_RSVD3,
+	S2MPS11_REG_BU_CHG,
+	S2MPS11_REG_RAMP,
+	S2MPS11_REG_RAMP_BUCK,
+	S2MPS11_REG_LDO1_8,
+	S2MPS11_REG_LDO9_16,
+	S2MPS11_REG_LDO17_24,
+	S2MPS11_REG_LDO25_32,
+	S2MPS11_REG_LDO33_38,
+	S2MPS11_REG_LDO1_8_OVC,
+	S2MPS11_REG_LDO9_16_OVC,
+	S2MPS11_REG_LDO17_24_OVC,
+	S2MPS11_REG_LDO25_32_OVC,
+	S2MPS11_REG_LDO33_38_OVC,
+	S2MPS11_REG_RESERVED1,
+	S2MPS11_REG_RESERVED2,
+	S2MPS11_REG_RESERVED3,
+	S2MPS11_REG_RESERVED4,
+	S2MPS11_REG_RESERVED5,
+	S2MPS11_REG_RESERVED6,
+	S2MPS11_REG_RESERVED7,
+	S2MPS11_REG_RESERVED8,
+	S2MPS11_REG_WDRSTEN_CTRL,
+	S2MPS11_REG_B1CTRL1,
+	S2MPS11_REG_B1CTRL2,
+	S2MPS11_REG_B2CTRL1,
+	S2MPS11_REG_B2CTRL2,
+	S2MPS11_REG_B3CTRL1,
+	S2MPS11_REG_B3CTRL2,
+	S2MPS11_REG_B4CTRL1,
+	S2MPS11_REG_B4CTRL2,
+	S2MPS11_REG_B5CTRL1,
+	S2MPS11_REG_BUCK5_SW,
+	S2MPS11_REG_B5CTRL2,
+	S2MPS11_REG_B5CTRL3,
+	S2MPS11_REG_B5CTRL4,
+	S2MPS11_REG_B5CTRL5,
+	S2MPS11_REG_B6CTRL1,
+	S2MPS11_REG_B6CTRL2,
+	S2MPS11_REG_B7CTRL1,
+	S2MPS11_REG_B7CTRL2,
+	S2MPS11_REG_B8CTRL1,
+	S2MPS11_REG_B8CTRL2,
+	S2MPS11_REG_B9CTRL1,
+	S2MPS11_REG_B9CTRL2,
+	S2MPS11_REG_B10CTRL1,
+	S2MPS11_REG_B10CTRL2,
+	S2MPS11_REG_L1CTRL,
+	S2MPS11_REG_L2CTRL,
+	S2MPS11_REG_L3CTRL,
+	S2MPS11_REG_L4CTRL,
+	S2MPS11_REG_L5CTRL,
+	S2MPS11_REG_L6CTRL,
+	S2MPS11_REG_L7CTRL,
+	S2MPS11_REG_L8CTRL,
+	S2MPS11_REG_L9CTRL,
+	S2MPS11_REG_L10CTRL,
+	S2MPS11_REG_L11CTRL,
+	S2MPS11_REG_L12CTRL,
+	S2MPS11_REG_L13CTRL,
+	S2MPS11_REG_L14CTRL,
+	S2MPS11_REG_L15CTRL,
+	S2MPS11_REG_L16CTRL,
+	S2MPS11_REG_L17CTRL,
+	S2MPS11_REG_L18CTRL,
+	S2MPS11_REG_L19CTRL,
+	S2MPS11_REG_L20CTRL,
+	S2MPS11_REG_L21CTRL,
+	S2MPS11_REG_L22CTRL,
+	S2MPS11_REG_L23CTRL,
+	S2MPS11_REG_L24CTRL,
+	S2MPS11_REG_L25CTRL,
+	S2MPS11_REG_L26CTRL,
+	S2MPS11_REG_L27CTRL,
+	S2MPS11_REG_L28CTRL,
+	S2MPS11_REG_L29CTRL,
+	S2MPS11_REG_L30CTRL,
+	S2MPS11_REG_L31CTRL,
+	S2MPS11_REG_L32CTRL,
+	S2MPS11_REG_L33CTRL,
+	S2MPS11_REG_L34CTRL,

Dear Przemyslaw Marczak,

Just some minor comment,

Quoted 23 lines · Przemyslaw Marczak

This driver allows I/O operations on the Samsung S2MPS11 PMIC, which provides lots of LDO/BUCK outputs.

To enable it, update defconfig with:
- CONFIG_DM_PMIC_S2MPS11
and additional, if were not defined:
- CONFIG_CMD_PMIC
- CONFIG_ERRNO_STR

The binding info: doc/device-tree-bindings/pmic/s2mps11.txt

Signed-off-by Przemyslaw Marczak <[email protected]>

---
  doc/device-tree-bindings/pmic/s2mps11.txt |  17 +++++
  drivers/power/pmic/Kconfig                |  14 ++++
  drivers/power/pmic/Makefile               |   1 +
  drivers/power/pmic/s2mps11.c              |  60 ++++++++++++++++
  include/power/s2mps11.h                   | 109 ++++++++++++++++++++++++++++++
  5 files changed, 201 insertions(+)

create mode 100644 doc/device-tree-bindings/pmic/s2mps11.txt create mode 100644 drivers/power/pmic/s2mps11.c create mode 100644 include/power/s2mps11.h

doc/device-tree-bindings/pmic/s2mps11.txt line 1

Quoted 7 lines

doc/device-tree-bindings/pmic/s2mps11.txt new file +1 -0

new file mode 100644
index 0000000..db8d624
@@ -0,0 +1,17 @@
+SAMSUBNG, S2MPS11 PMIC

SAMSUNG?

Quoted 230 lines

doc/device-tree-bindings/pmic/s2mps11.txt new file +16 -0

+
+This file describes the binding info for the PMIC driver:
+- drivers/power/pmic/s2mps11.c
+
+Required properties:
+- compatible: "samsung,s2mps11-pmic"
+- reg = 0x66
+
+With those two properties, the pmic device can be used for read/write only.
+
+Example:
+
+s2mps11 at 66 {
+	compatible = "samsung,s2mps11-pmic";
+	reg = <0x66>;
+};

drivers/power/pmic/Kconfig +14 -0

index fc6a374..c66b352 100644
@@ -24,6 +24,20 @@ config DM_PMIC_MAX77686
  	This config enables implementation of driver-model pmic uclass features
  	for PMIC MAX77686. The driver implements read/write operations.
 
+config DM_PMIC_S2MPS11
+	bool "Enable Driver Model for PMIC Samsung S2MPS11"
+	depends on DM_PMIC
+	---help---
+	The Samsung S2MPS11 PMIC provides:
+	 - 38 adjustable LDO regulators
+	 - 9 High-Efficiency Buck Converters
+	 - 1 BuckBoost Converter
+	 - RTC with two alarms
+	 - Backup battery charger
+	 - I2C Configuration Interface
+	This driver provides access to I/O interface only.
+	Binding info: doc/device-tree-bindings/pmic/s2mps11.txt
+
  config DM_PMIC_SANDBOX
  	bool "Enable Driver Model for emulated Sandbox PMIC "
  	depends on DM_PMIC

drivers/power/pmic/Makefile +1 -0

index 99c5778..1b58d98 100644
@@ -8,6 +8,7 @@
  obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
  obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
  obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
+obj-$(CONFIG_DM_PMIC_S2MPS11) += s2mps11.o
  obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
  obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
  obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o

drivers/power/pmic/s2mps11.c new file +60 -0

new file mode 100644
index 0000000..7e28402
@@ -0,0 +1,60 @@
+/*
+ *  Copyright (C) 2015 Samsung Electronics
+ *  Przemyslaw Marczak  <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/s2mps11.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int s2mps11_reg_count(struct udevice *dev)
+{
+	return S2MPS11_REG_COUNT;
+}
+
+static int s2mps11_write(struct udevice *dev, uint reg, const uint8_t *buff,
+			 int len)
+{
+	if (dm_i2c_write(dev, reg, buff, len)) {
+		error("write error to device: %p register: %#x!", dev, reg);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int s2mps11_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+	if (dm_i2c_read(dev, reg, buff, len)) {
+		error("read error from device: %p register: %#x!", dev, reg);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static struct dm_pmic_ops s2mps11_ops = {
+	.reg_count = s2mps11_reg_count,
+	.read = s2mps11_read,
+	.write = s2mps11_write,
+};
+
+static const struct udevice_id s2mps11_ids[] = {
+	{ .compatible = "samsung,s2mps11-pmic" },
+	{ }
+};
+
+U_BOOT_DRIVER(pmic_s2mps11) = {
+	.name = "s2mps11_pmic",
+	.id = UCLASS_PMIC,
+	.of_match = s2mps11_ids,
+	.ops = &s2mps11_ops,
+};

include/power/s2mps11.h new file +105 -0

new file mode 100644
index 0000000..885a816
@@ -0,0 +1,109 @@
+#ifndef __INCLUDE__S2MPS11__H__
+#define __INCLUDE__S2MPS11__H__
+
+enum s2mps11_reg {
+	S2MPS11_REG_ID = 0,
+	S2MPS11_REG_INT1,
+	S2MPS11_REG_INT2,
+	S2MPS11_REG_INT3,
+	S2MPS11_REG_INT1M,
+	S2MPS11_REG_INT2M,
+	S2MPS11_REG_INT3M,
+	S2MPS11_REG_STATUS1,
+	S2MPS11_REG_STATUS2,
+	S2MPS11_REG_OFFSRC,
+	S2MPS11_REG_PWRONSRC,
+	S2MPS11_REG_RTC_CTRL,
+	S2MPS11_REG_CTRL1,
+	S2MPS11_REG_ETC_TEST,
+	S2MPS11_REG_RSVD3,
+	S2MPS11_REG_BU_CHG,
+	S2MPS11_REG_RAMP,
+	S2MPS11_REG_RAMP_BUCK,
+	S2MPS11_REG_LDO1_8,
+	S2MPS11_REG_LDO9_16,
+	S2MPS11_REG_LDO17_24,
+	S2MPS11_REG_LDO25_32,
+	S2MPS11_REG_LDO33_38,
+	S2MPS11_REG_LDO1_8_OVC,
+	S2MPS11_REG_LDO9_16_OVC,
+	S2MPS11_REG_LDO17_24_OVC,
+	S2MPS11_REG_LDO25_32_OVC,
+	S2MPS11_REG_LDO33_38_OVC,
+	S2MPS11_REG_RESERVED1,
+	S2MPS11_REG_RESERVED2,
+	S2MPS11_REG_RESERVED3,
+	S2MPS11_REG_RESERVED4,
+	S2MPS11_REG_RESERVED5,
+	S2MPS11_REG_RESERVED6,
+	S2MPS11_REG_RESERVED7,
+	S2MPS11_REG_RESERVED8,
+	S2MPS11_REG_WDRSTEN_CTRL,
+	S2MPS11_REG_B1CTRL1,
+	S2MPS11_REG_B1CTRL2,
+	S2MPS11_REG_B2CTRL1,
+	S2MPS11_REG_B2CTRL2,
+	S2MPS11_REG_B3CTRL1,
+	S2MPS11_REG_B3CTRL2,
+	S2MPS11_REG_B4CTRL1,
+	S2MPS11_REG_B4CTRL2,
+	S2MPS11_REG_B5CTRL1,
+	S2MPS11_REG_BUCK5_SW,
+	S2MPS11_REG_B5CTRL2,
+	S2MPS11_REG_B5CTRL3,
+	S2MPS11_REG_B5CTRL4,
+	S2MPS11_REG_B5CTRL5,
+	S2MPS11_REG_B6CTRL1,
+	S2MPS11_REG_B6CTRL2,
+	S2MPS11_REG_B7CTRL1,
+	S2MPS11_REG_B7CTRL2,
+	S2MPS11_REG_B8CTRL1,
+	S2MPS11_REG_B8CTRL2,
+	S2MPS11_REG_B9CTRL1,
+	S2MPS11_REG_B9CTRL2,
+	S2MPS11_REG_B10CTRL1,
+	S2MPS11_REG_B10CTRL2,
+	S2MPS11_REG_L1CTRL,
+	S2MPS11_REG_L2CTRL,
+	S2MPS11_REG_L3CTRL,
+	S2MPS11_REG_L4CTRL,
+	S2MPS11_REG_L5CTRL,
+	S2MPS11_REG_L6CTRL,
+	S2MPS11_REG_L7CTRL,
+	S2MPS11_REG_L8CTRL,
+	S2MPS11_REG_L9CTRL,
+	S2MPS11_REG_L10CTRL,
+	S2MPS11_REG_L11CTRL,
+	S2MPS11_REG_L12CTRL,
+	S2MPS11_REG_L13CTRL,
+	S2MPS11_REG_L14CTRL,
+	S2MPS11_REG_L15CTRL,
+	S2MPS11_REG_L16CTRL,
+	S2MPS11_REG_L17CTRL,
+	S2MPS11_REG_L18CTRL,
+	S2MPS11_REG_L19CTRL,
+	S2MPS11_REG_L20CTRL,
+	S2MPS11_REG_L21CTRL,
+	S2MPS11_REG_L22CTRL,
+	S2MPS11_REG_L23CTRL,
+	S2MPS11_REG_L24CTRL,
+	S2MPS11_REG_L25CTRL,
+	S2MPS11_REG_L26CTRL,
+	S2MPS11_REG_L27CTRL,
+	S2MPS11_REG_L28CTRL,
+	S2MPS11_REG_L29CTRL,
+	S2MPS11_REG_L30CTRL,
+	S2MPS11_REG_L31CTRL,
+	S2MPS11_REG_L32CTRL,
+	S2MPS11_REG_L33CTRL,
+	S2MPS11_REG_L34CTRL,
+	S2MPS11_REG_L35CTRL,
+	S2MPS11_REG_L36CTRL,
+	S2MPS11_REG_L37CTRL,
+	S2MPS11_REG_L38CTRL,
+	S2MPS11_REG_COUNT,
+};

include/power/s2mps11.h line 109

Quoted 5 lines

include/power/s2mps11.h new file +4 -0

+
+#define S2MPS11_LDO26_ENABLE	0xec
+
+#endif

Thanks,
Minkyu Kang.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
 arch/arm/dts/exynos5422-odroidxu3.dts | 7 +++++++
 configs/odroid-xu3_defconfig          | 3 +++
 2 files changed, 10 insertions(+)

This commit adds driver for Voltage Level Monitor based on 12-bit resolution internal ADC with 9-channel multiplexer.

New function:
- exynos_adc_read_channel(int channel) - returns an 12-bit average value after 8 time conversion, done by the hardware. The default sample rate is: 600kSPS. The channel range: 0-9.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
 arch/arm/mach-exynos/Makefile           |  1 +
 arch/arm/mach-exynos/adc.c              | 83 +++++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/adc.h | 45 ++++++++++++++++++
 arch/arm/mach-exynos/include/mach/cpu.h |  4 +-
 4 files changed, 131 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-exynos/adc.c

arch/arm/mach-exynos/Makefile +1 -0

index 8542f89..4b7f91f 100644
@@ -7,6 +7,7 @@
 
 obj-y  += clock.o power.o soc.o system.o pinmux.o tzpc.o
 
+obj-$(CONFIG_EXYNOS5420)       += adc.o
 obj-$(CONFIG_EXYNOS5420)       += sec_boot.o
 
 ifdef CONFIG_SPL_BUILD

arch/arm/mach-exynos/adc.c new file +83 -0

new file mode 100644
index 0000000..e8dd619
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2015 Samsung Electronics
+ * Przemyslaw Marczak <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/adc.h>
+#include <asm/arch/power.h>
+
+extern void sdelay(unsigned long loops);
+
+struct exynos_adc_v2 *exynos_adc_probe(void)
+{
+       struct exynos_adc_v2 *adc;
+
+       adc = (struct exynos_adc_v2 *)samsung_get_base_adc();
+       if (!adc) {
+               error("Invalid ADC base address!");
+               return NULL;
+       }
+
+       /* Check HW version */
+       if (readl(&adc->version) != ADC_V2_VERSION) {
+               error("This driver supports only ADC v2!");
+               return NULL;
+       }
+
+       /* ADC Reset */
+       writel(ADC_V2_CON1_SOFT_RESET, &adc->con1);
+
+       return adc;
+}
+
+static void exynos_adc_start_conversion(struct exynos_adc_v2 *adc, int channel)
+{
+       unsigned int cfg;
+
+       /* Disable INT - will read status only */
+       writel(0x0, &adc->int_en);
+
+       /* CON2 - set conversion parameters */
+       cfg = ADC_V2_CON2_C_TIME(3); /* Conversion times: (1 << 3) = 8 */
+       cfg |= ADC_V2_CON2_OSEL(OSEL_BINARY);
+       cfg |= ADC_V2_CON2_CHAN_SEL(channel);
+       cfg |= ADC_V2_CON2_ESEL(ESEL_ADC_EVAL_TIME_20CLK);
+       cfg |= ADC_V2_CON2_HIGHF(HIGHF_CONV_RATE_600KSPS);
+       writel(cfg, &adc->con2);
+
+       /* Start conversion */
+       cfg = readl(&adc->con1);
+       writel(cfg | ADC_V2_CON1_STC_EN, &adc->con1);
+}
+
+int exynos_adc_read_channel(int channel)
+{
+       struct exynos_adc_v2 *adc;
+       int timeout_us = ADC_V2_CONV_TIMEOUT_US;
+
+       adc = exynos_adc_probe();
+       if (!adc) {
+               error("Can't init ADC!");
+               return -ENODEV;
+       }
+
+       if (channel > ADC_V2_MAX_CHANNEL) {
+               error("ADC: max channel is: %d.", ADC_V2_MAX_CHANNEL);
+               return -ENODEV;
+       }
+
+       exynos_adc_start_conversion(adc, channel);
+
+       while (ADC_V2_GET_STATUS_FLAG(readl(&adc->status)) != FLAG_CONV_END) {
+               sdelay(4);
+               if (!timeout_us--) {
+                       error("ADC conversion timeout!");
+                       return -ETIME;
+               }
+       }
+
+       return readl(&adc->dat) & ADC_V2_DAT_MASK;
+}

arch/arm/mach-exynos/include/mach/adc.h +45 -0

index a0e26d7..228acf4 100644
@@ -9,6 +9,38 @@
 #ifndef __ASM_ARM_ARCH_ADC_H_
 #define __ASM_ARM_ARCH_ADC_H_
 
+#define ADC_V2_CON1_SOFT_RESET         (0x2 << 1)
+#define ADC_V2_CON1_STC_EN             (0x1)
+
+#define ADC_V2_CON2_OSEL(x)            (((x) & 0x1) << 10)
+#define OSEL_2S                                (0x0)
+#define OSEL_BINARY                    (0x1)
+#define ADC_V2_CON2_ESEL(x)            (((x) & 0x1) << 9)
+#define ESEL_ADC_EVAL_TIME_40CLK       (0x0)
+#define ESEL_ADC_EVAL_TIME_20CLK       (0x1)
+#define ADC_V2_CON2_HIGHF(x)           (((x) & 0x1) << 8)
+#define HIGHF_CONV_RATE_30KSPS         (0x0)
+#define HIGHF_CONV_RATE_600KSPS                (0x1)
+#define ADC_V2_CON2_C_TIME(x)          (((x) & 0x7) << 4)
+#define ADC_V2_CON2_CHAN_SEL(x)                ((x) & 0xf)
+
+#define ADC_V2_GET_STATUS_FLAG(x)      (((x) >> 2) & 0x1)
+#define FLAG_CONV_END                  (0x1)
+
+#define ADC_V2_INT_DISABLE             (0x0)
+#define ADC_V2_INT_ENABLE              (0x1)
+#define INT_NOT_GENERATED              (0x0)
+#define INT_GENERATED                  (0x1)
+
+#define ADC_V2_VERSION                 (0x80000008)
+
+#define ADC_V2_MAX_CHANNEL             (9)
+
+/* For default 8 time convertion with sample rate 600 kSPS - 15us timeout */
+#define ADC_V2_CONV_TIMEOUT_US         (15)
+
+#define ADC_V2_DAT_MASK                        (0xfff)
+
 #ifndef __ASSEMBLY__
 struct s5p_adc {
        unsigned int adccon;

@@ -21,6 +53,19 @@ struct s5p_adc {
        unsigned int adcmux;
        unsigned int adcclrintpndnup;
 };
+
+struct exynos_adc_v2 {
+       unsigned int con1;
+       unsigned int con2;
+       unsigned int status;
+       unsigned int dat;
+       unsigned int int_en;
+       unsigned int int_status;
+       unsigned int reserved[2];
+       unsigned int version;
+};
+
+int exynos_adc_read_channel(int channel);
 #endif
 
 #endif /* __ASM_ARM_ARCH_ADC_H_ */

arch/arm/mach-exynos/include/mach/cpu.h +0 -0

index 14a1692..75933e7 100644

arch/arm/mach-exynos/include/mach/cpu.h +0 -2

 #define EXYNOS5420_SPI_BASE            0x12D20000
 #define EXYNOS5420_I2S_BASE            0x12D60000
 #define EXYNOS5420_PWMTIMER_BASE       0x12DD0000

@@ -186,7 +187,6 @@
 #define EXYNOS5420_USBPHY_BASE         DEVICE_NOT_AVAILABLE
 #define EXYNOS5420_USBOTG_BASE         DEVICE_NOT_AVAILABLE
 #define EXYNOS5420_FIMD_BASE           DEVICE_NOT_AVAILABLE
-#define EXYNOS5420_ADC_BASE            DEVICE_NOT_AVAILABLE
 #define EXYNOS5420_MODEM_BASE          DEVICE_NOT_AVAILABLE
 #define EXYNOS5420_USB_HOST_XHCI_BASE  DEVICE_NOT_AVAILABLE
 
--

1.9.1

Hi Przemyslaw,

Quoted 8 lines · Przemyslaw Marczak

This commit adds driver for Voltage Level Monitor based on 12-bit resolution internal ADC with 9-channel multiplexer.

New function:
- exynos_adc_read_channel(int channel) - returns an 12-bit average value after 8 time conversion, done by the hardware. The default sample rate is: 600kSPS. The channel range: 0-9.

Quoted 8 lines

Signed-off-by Przemyslaw Marczak <[email protected]>

---
  arch/arm/mach-exynos/Makefile           |  1 +
  arch/arm/mach-exynos/adc.c              | 83 +++++++++++++++++++++++++++++++++
  arch/arm/mach-exynos/include/mach/adc.h | 45 ++++++++++++++++++
  arch/arm/mach-exynos/include/mach/cpu.h |  4 +-
  4 files changed, 131 insertions(+), 2 deletions(-)

create mode 100644 arch/arm/mach-exynos/adc.c

Can we add this to the device tree? Maybe we should even have a driver model uclass for ADC?

Quoted 164 lines

arch/arm/mach-exynos/Makefile +1 -0

index 8542f89..4b7f91f 100644
@@ -7,6 +7,7 @@
 
  obj-y  += clock.o power.o soc.o system.o pinmux.o tzpc.o
 
+obj-$(CONFIG_EXYNOS5420)       += adc.o
  obj-$(CONFIG_EXYNOS5420)       += sec_boot.o
 
  ifdef CONFIG_SPL_BUILD

arch/arm/mach-exynos/adc.c new file +83 -0

new file mode 100644
index 0000000..e8dd619
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2015 Samsung Electronics
+ * Przemyslaw Marczak <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/adc.h>
+#include <asm/arch/power.h>
+
+extern void sdelay(unsigned long loops);
+
+struct exynos_adc_v2 *exynos_adc_probe(void)
+{
+       struct exynos_adc_v2 *adc;
+
+       adc = (struct exynos_adc_v2 *)samsung_get_base_adc();
+       if (!adc) {
+               error("Invalid ADC base address!");
+               return NULL;
+       }
+
+       /* Check HW version */
+       if (readl(&adc->version) != ADC_V2_VERSION) {
+               error("This driver supports only ADC v2!");
+               return NULL;
+       }
+
+       /* ADC Reset */
+       writel(ADC_V2_CON1_SOFT_RESET, &adc->con1);
+
+       return adc;
+}
+
+static void exynos_adc_start_conversion(struct exynos_adc_v2 *adc, int channel)
+{
+       unsigned int cfg;
+
+       /* Disable INT - will read status only */
+       writel(0x0, &adc->int_en);
+
+       /* CON2 - set conversion parameters */
+       cfg = ADC_V2_CON2_C_TIME(3); /* Conversion times: (1 << 3) = 8 */
+       cfg |= ADC_V2_CON2_OSEL(OSEL_BINARY);
+       cfg |= ADC_V2_CON2_CHAN_SEL(channel);
+       cfg |= ADC_V2_CON2_ESEL(ESEL_ADC_EVAL_TIME_20CLK);
+       cfg |= ADC_V2_CON2_HIGHF(HIGHF_CONV_RATE_600KSPS);
+       writel(cfg, &adc->con2);
+
+       /* Start conversion */
+       cfg = readl(&adc->con1);
+       writel(cfg | ADC_V2_CON1_STC_EN, &adc->con1);
+}
+
+int exynos_adc_read_channel(int channel)
+{
+       struct exynos_adc_v2 *adc;
+       int timeout_us = ADC_V2_CONV_TIMEOUT_US;
+
+       adc = exynos_adc_probe();
+       if (!adc) {
+               error("Can't init ADC!");
+               return -ENODEV;
+       }
+
+       if (channel > ADC_V2_MAX_CHANNEL) {
+               error("ADC: max channel is: %d.", ADC_V2_MAX_CHANNEL);
+               return -ENODEV;
+       }
+
+       exynos_adc_start_conversion(adc, channel);
+
+       while (ADC_V2_GET_STATUS_FLAG(readl(&adc->status)) != FLAG_CONV_END) {
+               sdelay(4);
+               if (!timeout_us--) {
+                       error("ADC conversion timeout!");
+                       return -ETIME;
+               }
+       }
+
+       return readl(&adc->dat) & ADC_V2_DAT_MASK;
+}

arch/arm/mach-exynos/include/mach/adc.h +45 -0

index a0e26d7..228acf4 100644
@@ -9,6 +9,38 @@
  #ifndef __ASM_ARM_ARCH_ADC_H_
  #define __ASM_ARM_ARCH_ADC_H_
 
+#define ADC_V2_CON1_SOFT_RESET         (0x2 << 1)
+#define ADC_V2_CON1_STC_EN             (0x1)
+
+#define ADC_V2_CON2_OSEL(x)            (((x) & 0x1) << 10)
+#define OSEL_2S                                (0x0)
+#define OSEL_BINARY                    (0x1)
+#define ADC_V2_CON2_ESEL(x)            (((x) & 0x1) << 9)
+#define ESEL_ADC_EVAL_TIME_40CLK       (0x0)
+#define ESEL_ADC_EVAL_TIME_20CLK       (0x1)
+#define ADC_V2_CON2_HIGHF(x)           (((x) & 0x1) << 8)
+#define HIGHF_CONV_RATE_30KSPS         (0x0)
+#define HIGHF_CONV_RATE_600KSPS                (0x1)
+#define ADC_V2_CON2_C_TIME(x)          (((x) & 0x7) << 4)
+#define ADC_V2_CON2_CHAN_SEL(x)                ((x) & 0xf)
+
+#define ADC_V2_GET_STATUS_FLAG(x)      (((x) >> 2) & 0x1)
+#define FLAG_CONV_END                  (0x1)
+
+#define ADC_V2_INT_DISABLE             (0x0)
+#define ADC_V2_INT_ENABLE              (0x1)
+#define INT_NOT_GENERATED              (0x0)
+#define INT_GENERATED                  (0x1)
+
+#define ADC_V2_VERSION                 (0x80000008)
+
+#define ADC_V2_MAX_CHANNEL             (9)
+
+/* For default 8 time convertion with sample rate 600 kSPS - 15us timeout */
+#define ADC_V2_CONV_TIMEOUT_US         (15)
+
+#define ADC_V2_DAT_MASK                        (0xfff)
+
  #ifndef __ASSEMBLY__
  struct s5p_adc {
         unsigned int adccon;

@@ -21,6 +53,19 @@ struct s5p_adc {
         unsigned int adcmux;
         unsigned int adcclrintpndnup;
  };
+
+struct exynos_adc_v2 {
+       unsigned int con1;
+       unsigned int con2;
+       unsigned int status;
+       unsigned int dat;
+       unsigned int int_en;
+       unsigned int int_status;
+       unsigned int reserved[2];
+       unsigned int version;
+};
+
+int exynos_adc_read_channel(int channel);
  #endif
 

arch/arm/mach-exynos/include/mach/cpu.h line 170

Quoted 11 lines

arch/arm/mach-exynos/include/mach/adc.h +0 -0

  #endif /* __ASM_ARM_ARCH_ADC_H_ */

arch/arm/mach-exynos/include/mach/cpu.h +1 -1

index 14a1692..75933e7 100644
@@ -167,10 +167,11 @@
  #define EXYNOS5420_USB_HOST_EHCI_BASE  0x12110000
  #define EXYNOS5420_MMC_BASE            0x12200000
  #define EXYNOS5420_SROMC_BASE          0x12250000
-#define EXYNOS5420_USB3PHY_BASE        0x12500000
+#define EXYNOS5420_USB3PHY_BASE                0x12500000

unrelated change?

arch/arm/mach-exynos/include/mach/cpu.h line 174

Quoted 4 lines

arch/arm/mach-exynos/include/mach/cpu.h +1 -0

  #define EXYNOS5420_UART_BASE           0x12C00000
  #define EXYNOS5420_I2C_BASE            0x12C60000
  #define EXYNOS5420_I2C_8910_BASE       0x12E00000
+#define EXYNOS5420_ADC_BASE            0x12D10000

Then we can drop this.

Quoted 11 lines

arch/arm/mach-exynos/include/mach/cpu.h +0 -1

  #define EXYNOS5420_SPI_BASE            0x12D20000
  #define EXYNOS5420_I2S_BASE            0x12D60000
  #define EXYNOS5420_PWMTIMER_BASE       0x12DD0000

@@ -186,7 +187,6 @@
  #define EXYNOS5420_USBPHY_BASE         DEVICE_NOT_AVAILABLE
  #define EXYNOS5420_USBOTG_BASE         DEVICE_NOT_AVAILABLE
  #define EXYNOS5420_FIMD_BASE           DEVICE_NOT_AVAILABLE
-#define EXYNOS5420_ADC_BASE            DEVICE_NOT_AVAILABLE
  #define EXYNOS5420_MODEM_BASE          DEVICE_NOT_AVAILABLE
  #define EXYNOS5420_USB_HOST_XHCI_BASE  DEVICE_NOT_AVAILABLE
 

Quoted 3 lines

--
1.9.1

Regards,
Simon

There are few revisions of Odroid XU3/XU4:

 Rev   ADC   Board
 0.1     0   XU3 0.1
 0.2   372   XU3 0.2 | XU3L - no DISPLAYPORT
 0.3   739   XU4 0.1

This commit adds implementation of functions:
- set_board_type() - read ADC and set type
- get_board_rev() - returns board revision: 1..3
- board_is_odroidxu3() - returns bool
- board_is_odroidxu4() - returns bool
- get_board_type() - returns board type string

After I2C controller init, the last function can check if the board is "Lite" variant for XU3, by probing chip 0x40 on I2C0 (INA231 - exists only on non-lite). This is useful for setting fdt file name at misc_init_r().

The enabled configs:
- CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- CONFIG_ODROID_REV_AIN
- CONFIG_REVISION_TAG
- CONFIG_MISC_INIT_R
- CONFIG_BOARD_TYPES

This also redefines CONFIG_SYS_BOARD to "odroid".

Signed-off-by Przemyslaw Marczak <[email protected]>

---
 board/samsung/common/exynos5-dt.c | 114 ++++++++++++++++++++++++++++++++++++++
 include/configs/odroid_xu3.h      |  12 ++++
 2 files changed, 126 insertions(+)

board/samsung/common/exynos5-dt.c +2 -0

index 7d1b88a..41141df 100644
@@ -18,6 +18,7 @@
 #include <usb.h>
 #include <video_bridge.h>
 #include <asm/gpio.h>
+#include <asm/arch/adc.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/dwmmc.h>
 #include <asm/arch/mmc.h>

@@ -28,6 +29,7 @@
 #include <power/max77686_pmic.h>
 #include <power/regulator.h>
 #include <power/s5m8767.h>
+#include <power/s2mps11.h>
 #include <tmu.h>
 
 DECLARE_GLOBAL_DATA_PTR;

board/samsung/common/exynos5-dt.c +110 -0

+/**
+ * Odroix XU3/4 board revisions:
+ * Rev   ADC   Board
+ * 0.1     0   XU3 0.1
+ * 0.2   372   XU3 0.2 | XU3L - no DISPLAYPORT (probe I2C0:0x40 / INA231)
+ * 0.3   739   XU4 0.1
+ * Use +/-20 for ADC value tolerance.
+ */
+enum {
+       ODROID_XU3_REV01,
+       ODROID_XU3_REV02,
+       ODROID_XU4_REV01,
+       ODROID_UNKNOWN_REV,
+       ODROID_REV_COUNT,
+};
+
+struct odroid_type {
+       int board_type;
+       int rev;
+       int adc_val;
+       const char *name;
+};
+
+struct odroid_type odroid_type[] = {
+       { ODROID_XU3_REV01, 1, 0, "xu3" },
+       { ODROID_XU3_REV02, 2, 372, "xu3" },
+       { ODROID_XU4_REV01, 1, 739, "xu4" },
+       { ODROID_UNKNOWN_REV, 0, 4095, "unknown" },
+};
+
+bool board_is_odroidxu3(void)
+{
+       if (gd->board_type < ODROID_XU4_REV01)
+               return true;
+
+       return false;
+}
+
+bool board_is_odroidxu4(void)
+{
+       if (gd->board_type > ODROID_XU3_REV02)
+               return true;
+
+       return false;
+}
+
+int set_board_type(void)
+{
+       int adcval, i;
+
+       adcval = exynos_adc_read_channel(CONFIG_ODROID_REV_AIN);
+       if (adcval < 0)
+               return adcval;
+
+       for (i = 0; i < ODROID_REV_COUNT; i++) {
+               /* ADC tolerance: +20 */
+               if (adcval < odroid_type[i].adc_val + 20) {
+                       gd->board_type = i;
+                       return i;
+               }
+       }
+
+       return ODROID_UNKNOWN_REV;
+}
+
+int get_board_rev(void)
+{
+       return odroid_type[gd->board_type].rev;
+}
+
+/**
+ * get_board_type - returns pointer to one of the board type string.
+ * Board types: "xu3", "xu3-lite", "xu4". However the "xu3itel" can be
+ * detected only when the i2c controller is ready to use. Fortunately,
+ * XU3 and XU3L are compatible, and the information about board lite
+ * revision is needed before boot linux, to set proper environment
+ * variable: $fdtfile.
+ */
+const char *get_board_type(void)
+{
+       const char *type_xu3l = "xu3-lite";
+       struct udevice *dev, *chip;
+       int ret;
+
+       if (gd->board_type != ODROID_XU3_REV02)
+               goto exit;
+
+       ret = pmic_get("s2mps11", &dev);
+       if (ret)
+               goto exit;
+
+       /* Enable LDO26: 3.0V */
+       ret = pmic_reg_write(dev, S2MPS11_REG_L26CTRL,
+                            S2MPS11_LDO26_ENABLE);
+       if (ret)
+               goto exit;
+
+       /* Check XU3Lite by probe INA231 I2C0:0x40 */
+       ret = uclass_get_device(UCLASS_I2C, 0, &dev);
+       if (ret)
+               goto exit;
+
+       ret = dm_i2c_probe(dev, 0x40, 0x0, &chip);
+       if (ret)
+               return type_xu3l;
+
+exit:
+       return odroid_type[gd->board_type].name;
+}
+#endif

include/configs/odroid_xu3.h +12 -1

index 3c70158..648e48b 100644
@@ -94,6 +94,8 @@
        "boot.scr fat 0 1;"                 \
        "boot.cmd fat 0 1;"                 \
        "exynos5422-odroidxu3.dtb fat 0 1;" \
+       "exynos5422-odroidxu3-lite.dtb fat 0 1;" \
+       "exynos5422-odroidxu4.dtb fat 0 1;" \
        "boot part 0 1;"                    \
        "root part 0 2\0"
 

@@ -113,9 +115,19 @@
 
 /* Enable: board/samsung/common/misc.c to use set_dfu_alt_info() */
 #define CONFIG_MISC_COMMON
+#define CONFIG_MISC_INIT_R
 #define CONFIG_SET_DFU_ALT_INFO
 #define CONFIG_SET_DFU_ALT_BUF_LEN     (SZ_1K)
 
+/* Set soc_rev, soc_id, board_rev, boardname, fdtfile */
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_ODROID_REV_AIN                  9
+#define CONFIG_REVISION_TAG
+#define CONFIG_BOARD_TYPES
+
+#undef CONFIG_SYS_BOARD
+#define CONFIG_SYS_BOARD       "odroid"
+
 /* Define new extra env settings, including DFU settings */
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS \
--

1.9.1

Hi Przemyslaw,

Quoted 52 lines · Przemyslaw Marczak

There are few revisions of Odroid XU3/XU4:

  Rev   ADC   Board
  0.1     0   XU3 0.1
  0.2   372   XU3 0.2 | XU3L - no DISPLAYPORT
  0.3   739   XU4 0.1

This commit adds implementation of functions:
- set_board_type() - read ADC and set type
- get_board_rev() - returns board revision: 1..3
- board_is_odroidxu3() - returns bool
- board_is_odroidxu4() - returns bool
- get_board_type() - returns board type string

After I2C controller init, the last function can check if the board is "Lite" variant for XU3, by probing chip 0x40 on I2C0 (INA231 - exists only on non-lite). This is useful for setting fdt file name at misc_init_r().

The enabled configs:
- CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- CONFIG_ODROID_REV_AIN
- CONFIG_REVISION_TAG
- CONFIG_MISC_INIT_R
- CONFIG_BOARD_TYPES

This also redefines CONFIG_SYS_BOARD to "odroid".

Signed-off-by Przemyslaw Marczak <[email protected]>

---
  board/samsung/common/exynos5-dt.c | 114 ++++++++++++++++++++++++++++++++++++++
  include/configs/odroid_xu3.h      |  12 ++++
  2 files changed, 126 insertions(+)

board/samsung/common/exynos5-dt.c +2 -0

index 7d1b88a..41141df 100644
@@ -18,6 +18,7 @@
  #include <usb.h>
  #include <video_bridge.h>
  #include <asm/gpio.h>
+#include <asm/arch/adc.h>
  #include <asm/arch/cpu.h>
  #include <asm/arch/dwmmc.h>
  #include <asm/arch/mmc.h>

@@ -28,6 +29,7 @@
  #include <power/max77686_pmic.h>
  #include <power/regulator.h>
  #include <power/s5m8767.h>
+#include <power/s2mps11.h>
  #include <tmu.h>
 

board/samsung/common/exynos5-dt.c char *get_dfu_alt_boot(char *interface, char *devstr) · line 366

Quoted 7 lines

board/samsung/common/exynos5-dt.c +2 -0

  DECLARE_GLOBAL_DATA_PTR;

@@ -360,3 +362,115 @@ char *get_dfu_alt_boot(char *interface, char *devstr)
         return alt_boot;
  }
  #endif
+
+#ifdef CONFIG_REVISION_TAG

Can we check the compatible string instead? It would be good to avoid #ifdef in common code.

Quoted 141 lines

board/samsung/common/exynos5-dt.c +110 -0

+/**
+ * Odroix XU3/4 board revisions:
+ * Rev   ADC   Board
+ * 0.1     0   XU3 0.1
+ * 0.2   372   XU3 0.2 | XU3L - no DISPLAYPORT (probe I2C0:0x40 / INA231)
+ * 0.3   739   XU4 0.1
+ * Use +/-20 for ADC value tolerance.
+ */
+enum {
+       ODROID_XU3_REV01,
+       ODROID_XU3_REV02,
+       ODROID_XU4_REV01,
+       ODROID_UNKNOWN_REV,
+       ODROID_REV_COUNT,
+};
+
+struct odroid_type {
+       int board_type;
+       int rev;
+       int adc_val;
+       const char *name;
+};
+
+struct odroid_type odroid_type[] = {
+       { ODROID_XU3_REV01, 1, 0, "xu3" },
+       { ODROID_XU3_REV02, 2, 372, "xu3" },
+       { ODROID_XU4_REV01, 1, 739, "xu4" },
+       { ODROID_UNKNOWN_REV, 0, 4095, "unknown" },
+};
+
+bool board_is_odroidxu3(void)
+{
+       if (gd->board_type < ODROID_XU4_REV01)
+               return true;
+
+       return false;
+}
+
+bool board_is_odroidxu4(void)
+{
+       if (gd->board_type > ODROID_XU3_REV02)
+               return true;
+
+       return false;
+}
+
+int set_board_type(void)
+{
+       int adcval, i;
+
+       adcval = exynos_adc_read_channel(CONFIG_ODROID_REV_AIN);
+       if (adcval < 0)
+               return adcval;
+
+       for (i = 0; i < ODROID_REV_COUNT; i++) {
+               /* ADC tolerance: +20 */
+               if (adcval < odroid_type[i].adc_val + 20) {
+                       gd->board_type = i;
+                       return i;
+               }
+       }
+
+       return ODROID_UNKNOWN_REV;
+}
+
+int get_board_rev(void)
+{
+       return odroid_type[gd->board_type].rev;
+}
+
+/**
+ * get_board_type - returns pointer to one of the board type string.
+ * Board types: "xu3", "xu3-lite", "xu4". However the "xu3itel" can be
+ * detected only when the i2c controller is ready to use. Fortunately,
+ * XU3 and XU3L are compatible, and the information about board lite
+ * revision is needed before boot linux, to set proper environment
+ * variable: $fdtfile.
+ */
+const char *get_board_type(void)
+{
+       const char *type_xu3l = "xu3-lite";
+       struct udevice *dev, *chip;
+       int ret;
+
+       if (gd->board_type != ODROID_XU3_REV02)
+               goto exit;
+
+       ret = pmic_get("s2mps11", &dev);
+       if (ret)
+               goto exit;
+
+       /* Enable LDO26: 3.0V */
+       ret = pmic_reg_write(dev, S2MPS11_REG_L26CTRL,
+                            S2MPS11_LDO26_ENABLE);
+       if (ret)
+               goto exit;
+
+       /* Check XU3Lite by probe INA231 I2C0:0x40 */
+       ret = uclass_get_device(UCLASS_I2C, 0, &dev);
+       if (ret)
+               goto exit;
+
+       ret = dm_i2c_probe(dev, 0x40, 0x0, &chip);
+       if (ret)
+               return type_xu3l;
+
+exit:
+       return odroid_type[gd->board_type].name;
+}
+#endif

include/configs/odroid_xu3.h +12 -0

index 3c70158..648e48b 100644
@@ -94,6 +94,8 @@
         "boot.scr fat 0 1;"                 \
         "boot.cmd fat 0 1;"                 \
         "exynos5422-odroidxu3.dtb fat 0 1;" \
+       "exynos5422-odroidxu3-lite.dtb fat 0 1;" \
+       "exynos5422-odroidxu4.dtb fat 0 1;" \
         "boot part 0 1;"                    \
         "root part 0 2\0"
 

@@ -113,9 +115,19 @@
 
  /* Enable: board/samsung/common/misc.c to use set_dfu_alt_info() */
  #define CONFIG_MISC_COMMON
+#define CONFIG_MISC_INIT_R
  #define CONFIG_SET_DFU_ALT_INFO
  #define CONFIG_SET_DFU_ALT_BUF_LEN     (SZ_1K)
 
+/* Set soc_rev, soc_id, board_rev, boardname, fdtfile */
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_ODROID_REV_AIN                  9
+#define CONFIG_REVISION_TAG
+#define CONFIG_BOARD_TYPES
+
+#undef CONFIG_SYS_BOARD
+#define CONFIG_SYS_BOARD       "odroid"
+
  /* Define new extra env settings, including DFU settings */

Quoted 5 lines

include/configs/odroid_xu3.h +0 -1

  #undef CONFIG_EXTRA_ENV_SETTINGS
  #define CONFIG_EXTRA_ENV_SETTINGS \
--

1.9.1

Regards,
Simon

This patchset adds:
- define the CPU name for Chromebook Peach Pi as Exynos5800
- set the cpu id of Exynos5422 to 0x5422
- S2MPS11 PMIC I/O driver
- Exynos5420-compatible (9-channel, 12-bit) ADC driver
- board detection for Odroid XU3 / XU3lite / XU4

This was tested on Odroid XU3 and XU3 Lite, without the XU4, but I'm waiting for reply from the Odroid forum users.

Tested with buildman for samsung.

Available on github:
https://github.com/bobenstein/u-boot/tree/xu3-patchset-test

Przemyslaw Marczak (7):
s5p: cpu_info: use defined CPU name if available
peach-pi: define CPU name for SoC Exynos5800 Exynos5422/5800: set cpu id to 0x5422
dm: pmic: add s2mps11 PMIC I/O driver
odroid-xu3: enable s2mps11 PMIC support
Exynos: add internal ADC driver
exynos5-dt: add board detection for Odroid XU3/XU3L/XU4.

 arch/arm/cpu/armv7/s5p-common/cpu_info.c  |   5 ++
 arch/arm/dts/exynos5422-odroidxu3.dts     |   7 ++
 arch/arm/mach-exynos/Makefile             |   1 +
 arch/arm/mach-exynos/adc.c                |  83 ++++++++++++++++++++++
 arch/arm/mach-exynos/clock.c              |  16 ++---
 arch/arm/mach-exynos/clock_init_exynos5.c |   2 +-
 arch/arm/mach-exynos/common_setup.h       |   4 +-
 arch/arm/mach-exynos/include/mach/adc.h   |  45 ++++++++++++
 arch/arm/mach-exynos/include/mach/cpu.h   |  10 +--
 arch/arm/mach-exynos/include/mach/gpio.h  |   4 +-
 arch/arm/mach-exynos/pinmux.c             |   2 +-
 arch/arm/mach-exynos/power.c              |   2 +-
 board/samsung/common/exynos5-dt.c         | 114

 configs/odroid-xu3_defconfig              |   3 +
 doc/device-tree-bindings/pmic/s2mps11.txt |  17 +++++
 drivers/power/pmic/Kconfig                |  14 ++++
 drivers/power/pmic/Makefile               |   1 +
 drivers/power/pmic/s2mps11.c              |  60 ++++++++++++++++
 include/configs/odroid_xu3.h              |  12 ++++
 include/configs/peach-pi.h                |   2 +
 include/power/s2mps11.h                   | 109

 21 files changed, 493 insertions(+), 20 deletions(-)
 create mode 100644 arch/arm/mach-exynos/adc.c
 create mode 100644 doc/device-tree-bindings/pmic/s2mps11.txt
 create mode 100644 drivers/power/pmic/s2mps11.c
 create mode 100644 include/power/s2mps11.h

--
1.9.1

hi Przemyslaw,

Quoted 24 lines · On 28 August 2015 at 19:29, Przemyslaw Marczak <[email protected]…

This patchset adds:
- define the CPU name for Chromebook Peach Pi as Exynos5800
- set the cpu id of Exynos5422 to 0x5422
- S2MPS11 PMIC I/O driver
- Exynos5420-compatible (9-channel, 12-bit) ADC driver
- board detection for Odroid XU3 / XU3lite / XU4

This was tested on Odroid XU3 and XU3 Lite, without the XU4, but I'm waiting for reply from the Odroid forum users.

Tested with buildman for samsung.

Available on github:
https://github.com/bobenstein/u-boot/tree/xu3-patchset-test

Przemyslaw Marczak (7):
s5p: cpu_info: use defined CPU name if available
peach-pi: define CPU name for SoC Exynos5800 Exynos5422/5800: set cpu id to 0x5422
dm: pmic: add s2mps11 PMIC I/O driver
odroid-xu3: enable s2mps11 PMIC support
Exynos: add internal ADC driver
exynos5-dt: add board detection for Odroid XU3/XU3L/XU4.

Quoted 13 lines

 arch/arm/cpu/armv7/s5p-common/cpu_info.c  |   5 ++
 arch/arm/dts/exynos5422-odroidxu3.dts     |   7 ++
 arch/arm/mach-exynos/Makefile             |   1 +
 arch/arm/mach-exynos/adc.c                |  83 ++++++++++++++++++++++
 arch/arm/mach-exynos/clock.c              |  16 ++---
 arch/arm/mach-exynos/clock_init_exynos5.c |   2 +-
 arch/arm/mach-exynos/common_setup.h       |   4 +-
 arch/arm/mach-exynos/include/mach/adc.h   |  45 ++++++++++++
 arch/arm/mach-exynos/include/mach/cpu.h   |  10 +--
 arch/arm/mach-exynos/include/mach/gpio.h  |   4 +-
 arch/arm/mach-exynos/pinmux.c             |   2 +-
 arch/arm/mach-exynos/power.c              |   2 +-
 board/samsung/common/exynos5-dt.c         | 114

++++++++++++++++++++++++++++++

Quoted 8 lines

 configs/odroid-xu3_defconfig              |   3 +
 doc/device-tree-bindings/pmic/s2mps11.txt |  17 +++++
 drivers/power/pmic/Kconfig                |  14 ++++
 drivers/power/pmic/Makefile               |   1 +
 drivers/power/pmic/s2mps11.c              |  60 ++++++++++++++++
 include/configs/odroid_xu3.h              |  12 ++++
 include/configs/peach-pi.h                |   2 +
 include/power/s2mps11.h                   | 109

++++++++++++++++++++++++++++

Quoted 6 lines

 21 files changed, 493 insertions(+), 20 deletions(-)
 create mode 100644 arch/arm/mach-exynos/adc.c
 create mode 100644 doc/device-tree-bindings/pmic/s2mps11.txt
 create mode 100644 drivers/power/pmic/s2mps11.c
 create mode 100644 include/power/s2mps11.h

Thanks for these patches.
? ??

At the last moment I got this to work on my odroidxu3 board.

One problem I would like to address out is usb smsc95xx ethernet is not getting started at the boot.

# usb start                   /* command failed at the start */
------------------------------------------------------------------------------------------------------
U-Boot 2015.10-rc2-00226-g7dbe336 (Aug 30 2015 - 23:41:27 +0530) for
ODROID-XU3

CPU:   Exynos5422 @ 800 MHz
Model: Odroid XU3 based on EXYNOS5422
Board: Odroid XU3 based on EXYNOS5422
Model: xu3
DRAM:  2 GiB
MMC:   EXYNOS DWMMC: 0, EXYNOS DWMMC: 1

*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   No ethernet found.
Hit any key to stop autoboot:  0

switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
starting USB...

USB0:   USB EHCI 1.00
USB1:   Register 2000140 NbrPorts 2

Starting the controller
USB XHCI 1.00
USB2: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus 0 for devices... 1 USB Device(s) found
scanning bus 1 for devices... 1 USB Device(s) found
scanning bus 2 for devices... 1 USB Device(s) found
scanning usb for ethernet devices... 0 Ethernet Device(s) found
No ethernet found.
missing environment variable: pxeuuid
missing environment variable: bootfile
-----------------------------------------------------------------------------------------

I will give it a try with latest kernel and let you know how it worked on Odroid-XU4 / XU4.

-Anand Moon

Quoted 3 lines

--
1.9.1

At the last moment I got this to work on my odroidxu3 board.

One problem I would like to address out is usb smsc95xx ethernet is not getting started at the boot.

# usb start                   /* command failed at the start */
------------------------------------------------------------------------------------------------------
U-Boot 2015.10-rc2-00226-g7dbe336 (Aug 30 2015 - 23:41:27 +0530) for
ODROID-XU3

CPU:   Exynos5422 @ 800 MHz
Model: Odroid XU3 based on EXYNOS5422
Board: Odroid XU3 based on EXYNOS5422
Model: xu3
DRAM:  2 GiB
MMC:   EXYNOS DWMMC: 0, EXYNOS DWMMC: 1

*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   No ethernet found.
Hit any key to stop autoboot:  0

switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
starting USB...

USB0:   USB EHCI 1.00
USB1:   Register 2000140 NbrPorts 2

Starting the controller
USB XHCI 1.00
USB2: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus 0 for devices... 1 USB Device(s) found scanning bus 1 for devices... 1 USB Device(s) found scanning bus 2 for devices... 1 USB Device(s) found
scanning usb for ethernet devices... 0 Ethernet Device(s) found
No ethernet found.
missing environment variable: pxeuuid
missing environment variable: bootfile
-----------------------------------------------------------------------------------------

Quoted 29 lines · On Mon, 31 Aug 2015 00:33:16 +0530 Anand Moon <[email protected]> wrote:

At the last moment I got this to work on my odroidxu3 board.

One problem I would like to address out is usb smsc95xx ethernet is not getting started at the boot.

# usb start                   /* command failed at the start */
------------------------------------------------------------------------------------------------------
U-Boot 2015.10-rc2-00226-g7dbe336 (Aug 30 2015 - 23:41:27 +0530) for
ODROID-XU3

CPU:   Exynos5422 @ 800 MHz
Model: Odroid XU3 based on EXYNOS5422
Board: Odroid XU3 based on EXYNOS5422
Model: xu3
DRAM:  2 GiB
MMC:   EXYNOS DWMMC: 0, EXYNOS DWMMC: 1

*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   No ethernet found.
Hit any key to stop autoboot:  0

switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
starting USB...

USB0:   USB EHCI 1.00
USB1:   Register 2000140 NbrPorts 2

Quoted 13 lines

Starting the controller
USB XHCI 1.00
USB2: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus 0 for devices... 1 USB Device(s) found scanning bus 1 for devices... 1 USB Device(s) found scanning bus 2 for devices... 1 USB Device(s) found
scanning usb for ethernet devices... 0 Ethernet Device(s) found
No ethernet found.
missing environment variable: pxeuuid
missing environment variable: bootfile
-----------------------------------------------------------------------------------------

Hi Anand,

This looks like it might be the same problem as

    http://lists.denx.de/pipermail/u-boot/2015-October/230827.html

Simon Glass asked if this also happens on XU3, so maybe you could test the same workaround on your board and provide feedback?

--
Best regards,
Siarhei Siamashka

Quoted 29 lines · On Mon, 31 Aug 2015 00:33:16 +0530 Anand Moon <[email protected]> wrote:

At the last moment I got this to work on my odroidxu3 board.

One problem I would like to address out is usb smsc95xx ethernet is not getting started at the boot.

# usb start                   /* command failed at the start */
------------------------------------------------------------------------------------------------------
U-Boot 2015.10-rc2-00226-g7dbe336 (Aug 30 2015 - 23:41:27 +0530) for
ODROID-XU3

CPU:   Exynos5422 @ 800 MHz
Model: Odroid XU3 based on EXYNOS5422
Board: Odroid XU3 based on EXYNOS5422
Model: xu3
DRAM:  2 GiB
MMC:   EXYNOS DWMMC: 0, EXYNOS DWMMC: 1

*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   No ethernet found.
Hit any key to stop autoboot:  0

switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
starting USB...

USB0:   USB EHCI 1.00
USB1:   Register 2000140 NbrPorts 2

Quoted 13 lines

Starting the controller
USB XHCI 1.00
USB2: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus 0 for devices... 1 USB Device(s) found scanning bus 1 for devices... 1 USB Device(s) found scanning bus 2 for devices... 1 USB Device(s) found
scanning usb for ethernet devices... 0 Ethernet Device(s) found
No ethernet found.
missing environment variable: pxeuuid
missing environment variable: bootfile
-----------------------------------------------------------------------------------------

Hi Anand,

This looks like it might be the same problem as

    http://lists.denx.de/pipermail/u-boot/2015-October/230827.html

Simon Glass asked if this also happens on XU3, so maybe you could test the same workaround on your board and provide feedback?

--

Best regards,
Siarhei Siamashka

Hi Siarhei ,

Quoted 48 lines · Siarhei Siamashka

Quoted 29 lines · On Mon, 31 Aug 2015 00:33:16 +0530 Anand Moon <[email protected]> wrote:

At the last moment I got this to work on my odroidxu3 board.

One problem I would like to address out is usb smsc95xx ethernet is not getting started at the boot.

# usb start                   /* command failed at the start */
------------------------------------------------------------------------------------------------------
U-Boot 2015.10-rc2-00226-g7dbe336 (Aug 30 2015 - 23:41:27 +0530) for
ODROID-XU3

CPU:   Exynos5422 @ 800 MHz
Model: Odroid XU3 based on EXYNOS5422
Board: Odroid XU3 based on EXYNOS5422
Model: xu3
DRAM:  2 GiB
MMC:   EXYNOS DWMMC: 0, EXYNOS DWMMC: 1

*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   No ethernet found.
Hit any key to stop autoboot:  0

switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
starting USB...

USB0:   USB EHCI 1.00
USB1:   Register 2000140 NbrPorts 2

Quoted 13 lines

Starting the controller
USB XHCI 1.00
USB2: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus 0 for devices... 1 USB Device(s) found
scanning bus 1 for devices... 1 USB Device(s) found
scanning bus 2 for devices... 1 USB Device(s) found
scanning usb for ethernet devices... 0 Ethernet Device(s) found
No ethernet found.
missing environment variable: pxeuuid
missing environment variable: bootfile
-----------------------------------------------------------------------------------------

Hi Anand,

Quoted 7 lines

This looks like it might be the same problem as

     http://lists.denx.de/pipermail/u-boot/2015-October/230827.html

Simon Glass asked if this also happens on XU3, so maybe you could test the same workaround on your board and provide feedback?

--

Odroid u3 also has the same problem
---------------------------------------------------------
U-Boot 2015.10-rc5-00030-gac6a532-dirty (Oct 20 2015 - 01:37:27 +1030)

CPU:   Exynos4412 @ 1 GHz
Model: Odroid based on Exynos4412
Board: Odroid based on Exynos4412
Model: u3
DRAM:  2 GiB
LDO20 at VDDQ_EMMC_1.8V: set 1800000 uV; enabling
LDO22 at VDDQ_EMMC_2.8V: set 2800000 uV; enabling
LDO21 at TFLASH_2.8V: set 2800000 uV; enabling
MMC:   SAMSUNG SDHCI: 0, EXYNOS DWMMC: 1

*** Warning - bad CRC, using default environment

Net:   No ethernet found.
Hit any key to stop autoboot:  0

Odroid # setenv usbethaddr 02:DE:AD:BE:EF:FF
Odroid # usb start
starting USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... 1 USB Device(s) found
scanning usb for ethernet devices... 0 Ethernet Device(s) found
Odroid #
---------------------------------------------------------

-Anand Moon

Quoted 2 lines

Best regards,
Siarhei Siamashka

This patchset adds:
- define the CPU name for Chromebook Peach Pi as Exynos5800
- set the cpu id of Exynos5422 to 0x5422
- S2MPS11 PMIC I/O driver
- Exynos5420-compatible (9-channel, 12-bit) ADC driver
- board detection for Odroid XU3 / XU3lite / XU4

This was tested on Odroid XU3 and XU3 Lite, without the XU4, but I'm waiting for reply from the Odroid forum users.

Tested with buildman for samsung.

Available on github:
https://github.com/bobenstein/u-boot/tree/xu3-patchset-test

Przemyslaw Marczak (7):
s5p: cpu_info: use defined CPU name if available
peach-pi: define CPU name for SoC Exynos5800 Exynos5422/5800: set cpu id to 0x5422
dm: pmic: add s2mps11 PMIC I/O driver
odroid-xu3: enable s2mps11 PMIC support
Exynos: add internal ADC driver
exynos5-dt: add board detection for Odroid XU3/XU3L/XU4.

Hi Przemyslaw,

Quoted 15 lines · Przemyslaw Marczak

This patchset adds:
- define the CPU name for Chromebook Peach Pi as Exynos5800
- set the cpu id of Exynos5422 to 0x5422
- S2MPS11 PMIC I/O driver
- Exynos5420-compatible (9-channel, 12-bit) ADC driver
- board detection for Odroid XU3 / XU3lite / XU4

This was tested on Odroid XU3 and XU3 Lite, without the XU4, but I'm waiting for reply from the Odroid forum users.

Tested with buildman for samsung.

Available on github:
https://github.com/bobenstein/u-boot/tree/xu3-patchset-test

Quoted 8 lines

Przemyslaw Marczak (7):
s5p: cpu_info: use defined CPU name if available
peach-pi: define CPU name for SoC Exynos5800 Exynos5422/5800: set cpu id to 0x5422
dm: pmic: add s2mps11 PMIC I/O driver
odroid-xu3: enable s2mps11 PMIC support
Exynos: add internal ADC driver
exynos5-dt: add board detection for Odroid XU3/XU3L/XU4.

It's nice to have things automatic. Is this easier than having a separate device tree for each board?

Regards
Simon

Hello Simon,

Quoted 30 lines · Simon Glass

Hi Przemyslaw,

Quoted 16 lines · Przemyslaw Marczak

This patchset adds:
- define the CPU name for Chromebook Peach Pi as Exynos5800
- set the cpu id of Exynos5422 to 0x5422
- S2MPS11 PMIC I/O driver
- Exynos5420-compatible (9-channel, 12-bit) ADC driver
- board detection for Odroid XU3 / XU3lite / XU4

This was tested on Odroid XU3 and XU3 Lite, without the XU4, but I'm waiting for reply from the Odroid forum users.

Tested with buildman for samsung.

Available on github:
https://github.com/bobenstein/u-boot/tree/xu3-patchset-test

Quoted 8 lines

Przemyslaw Marczak (7):
s5p: cpu_info: use defined CPU name if available
peach-pi: define CPU name for SoC Exynos5800 Exynos5422/5800: set cpu id to 0x5422
dm: pmic: add s2mps11 PMIC I/O driver
odroid-xu3: enable s2mps11 PMIC support
Exynos: add internal ADC driver
exynos5-dt: add board detection for Odroid XU3/XU3L/XU4.

Quoted 6 lines

It's nice to have things automatic. Is this easier than having a separate device tree for each board?

Regards
Simon

In my intention was using a single U-Boot binary (u-boot-dtb.bin) with the three almost full compatible boards. This is also easier for other developers, who don't need care about few configs and few dtb's.

And finally this code can load proper dtb for Linux Kernel for each supported board. So in the next part (Linux boot), things are done clean.

The common board file is quite messy because of this code, so if you don't like it, then I can move it to independent file.

Hi Przemyslaw,

Quoted 47 lines · Przemyslaw Marczak

Hello Simon,

Quoted 30 lines · Simon Glass

Hi Przemyslaw,

Quoted 16 lines · Przemyslaw Marczak

This patchset adds:
- define the CPU name for Chromebook Peach Pi as Exynos5800
- set the cpu id of Exynos5422 to 0x5422
- S2MPS11 PMIC I/O driver
- Exynos5420-compatible (9-channel, 12-bit) ADC driver
- board detection for Odroid XU3 / XU3lite / XU4

This was tested on Odroid XU3 and XU3 Lite, without the XU4, but I'm waiting for reply from the Odroid forum users.

Tested with buildman for samsung.

Available on github:
https://github.com/bobenstein/u-boot/tree/xu3-patchset-test

Quoted 8 lines

Przemyslaw Marczak (7):
s5p: cpu_info: use defined CPU name if available
peach-pi: define CPU name for SoC Exynos5800 Exynos5422/5800: set cpu id to 0x5422
dm: pmic: add s2mps11 PMIC I/O driver
odroid-xu3: enable s2mps11 PMIC support
Exynos: add internal ADC driver
exynos5-dt: add board detection for Odroid XU3/XU3L/XU4.

Quoted 6 lines

It's nice to have things automatic. Is this easier than having a separate device tree for each board?

Regards
Simon

In my intention was using a single U-Boot binary (u-boot-dtb.bin) with the three almost full compatible boards. This is also easier for other developers, who don't need care about few configs and few dtb's.

And finally this code can load proper dtb for Linux Kernel for each supported board. So in the next part (Linux boot), things are done clean.

Quoted 1 line

The common board file is quite messy because of this code, so if you don't like it, then I can move it to independent file.

I don't think it matters that much. I'm not keen on the #ifdef CONFIG_REVISION_TAG - can you instead check the board compatible string? The code should be generic to exynos5.

Regards,
Simon

The function get_board_type() is called in two places by common code, but the returned pointer was never check.

This commit adds checking the returned pointer, before use it.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
Changes V2:
- new commit

---
 board/samsung/common/board.c | 4 ++--
 board/samsung/common/misc.c  | 3 +++
 2 files changed, 5 insertions(+), 2 deletions(-)

The CPU name for Exynos was concatenated with cpu id, but for new Exynos platforms, like Chromebook Peach Pi based on Exynos5800, the name of SoC variant does not include the real SoC cpu id (0x5422).

For such case, the CPU name should be defined in device tree.

This commit introduces new device-tree property for Exynos:
- "cpu-model" - with cpu name string
If defined, then the cpu id is not printed.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
Changes V2:
- new commit

---
 arch/arm/cpu/armv7/s5p-common/cpu_info.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/s5p-common/cpu_info.c +3 -0

index 154d674..97d611f 100644
@@ -5,9 +5,12 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 #include <common.h>
+#include <fdtdec.h>
 #include <asm/io.h>
 #include <asm/arch/clk.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Default is s5pc100 */
 unsigned int s5p_cpu_id = 0xC100;
 /* Default is EVT1 */

arch/arm/cpu/armv7/s5p-common/cpu_info.c +8 -1

+
+       /* For SoC with no real CPU ID in naming convention. */
+       cpu_model = fdt_getprop(gd->fdt_blob, 0, "cpu-model", &len);
+       if (cpu_model)
+               printf("CPU:   %.*s @ ", len, cpu_model);
+       else
+               printf("CPU:   %s%X @ ", s5p_get_cpu_name(), s5p_cpu_id);
+
        print_freq(get_arm_clk(), "\n");
 
        return 0;
--

1.9.1

Quoted 11 lines · Przemyslaw Marczak

The CPU name for Exynos was concatenated with cpu id, but for new Exynos platforms, like Chromebook Peach Pi based on Exynos5800, the name of SoC variant does not include the real SoC cpu id (0x5422).

For such case, the CPU name should be defined in device tree.

This commit introduces new device-tree property for Exynos:
- "cpu-model" - with cpu name string
If defined, then the cpu id is not printed.

Quoted 8 lines

Signed-off-by Przemyslaw Marczak <[email protected]>

---
Changes V2:
- new commit

---
  arch/arm/cpu/armv7/s5p-common/cpu_info.c | 14 +++++++++++++-
  1 file changed, 13 insertions(+), 1 deletion(-)

Reviewed-by Simon Glass <[email protected]>

Please see nit below.

Quoted 12 lines

arch/arm/cpu/armv7/s5p-common/cpu_info.c +1 -0

index 154d674..97d611f 100644
@@ -5,9 +5,12 @@
   * SPDX-License-Identifier:    GPL-2.0+
   */
  #include <common.h>
+#include <fdtdec.h>
  #include <asm/io.h>
  #include <asm/arch/clk.h>
 

arch/arm/cpu/armv7/s5p-common/cpu_info.c u32 get_device_type(void) · line 37

Quoted 12 lines

arch/arm/cpu/armv7/s5p-common/cpu_info.c +4 -1

+DECLARE_GLOBAL_DATA_PTR;
+
  /* Default is s5pc100 */
  unsigned int s5p_cpu_id = 0xC100;
  /* Default is EVT1 */

@@ -30,7 +33,16 @@ u32 get_device_type(void)
  #ifdef CONFIG_DISPLAY_CPUINFO
  int print_cpuinfo(void)
  {
-       printf("CPU:   %s%X @ ", s5p_get_cpu_name(), s5p_cpu_id);
+       const char *cpu_model = NULL;
+       int len = 0;

No need to init these two variables.

Quoted 10 lines

arch/arm/cpu/armv7/s5p-common/cpu_info.c +8 -0

+
+       /* For SoC with no real CPU ID in naming convention. */
+       cpu_model = fdt_getprop(gd->fdt_blob, 0, "cpu-model", &len);
+       if (cpu_model)
+               printf("CPU:   %.*s @ ", len, cpu_model);
+       else
+               printf("CPU:   %s%X @ ", s5p_get_cpu_name(), s5p_cpu_id);
+
         print_freq(get_arm_clk(), "\n");
 

Quoted 4 lines

arch/arm/cpu/armv7/s5p-common/cpu_info.c +0 -1

         return 0;
--

1.9.1

This platform is based on Exynos5800 but the cpu id is 0x5422. This doesn't fit the common Exynos SoC name convention, so now, the CPU name is defined by device tree string, to be printed properly.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
Changes V2:
- move cpu name from config to dts

---
 arch/arm/dts/exynos5800-peach-pi.dts | 1 +
 1 file changed, 1 insertion(+)

arch/arm/dts/exynos5800-peach-pi.dts +1 -1

index 1d7ff23..76826dc 100644
@@ -12,6 +12,7 @@
 
 / {
        model = "Samsung/Google Peach Pi board based on Exynos5800";
+       cpu-model = "Exynos5800";
 
        compatible = "google,pit-rev#", "google,pit",
                "google,peach", "samsung,exynos5800", "samsung,exynos5";
--

1.9.1

Hi Przemyslaw,

Quoted 26 lines · Przemyslaw Marczak

This platform is based on Exynos5800 but the cpu id is 0x5422. This doesn't fit the common Exynos SoC name convention, so now, the CPU name is defined by device tree string, to be printed properly.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
Changes V2:
- move cpu name from config to dts

---
  arch/arm/dts/exynos5800-peach-pi.dts | 1 +
  1 file changed, 1 insertion(+)

arch/arm/dts/exynos5800-peach-pi.dts +1 -1

index 1d7ff23..76826dc 100644
@@ -12,6 +12,7 @@
 
  / {
         model = "Samsung/Google Peach Pi board based on Exynos5800";
+       cpu-model = "Exynos5800";
 
         compatible = "google,pit-rev#", "google,pit",
                 "google,peach", "samsung,exynos5800", "samsung,exynos5";
--

Quoted 2 lines

1.9.1

Is this defined by the standard binding? If not, can you add or change the binding file?

Regards,
Simon

The proper CPU ID for those Exynos variants is 0x5422, but before the 0x5800 was set. This commit fix this back.

Changes:
- set cpu id to 0x5422 instead of 0x5800
- remove macro proid_is_exynos5800()
- add macro proid_is_exynos5422()
- change the calls to proid_is_exynos5800() with new macro

Signed-off-by Przemyslaw Marczak <[email protected]>

---
Changes V2:
- none

---
 arch/arm/mach-exynos/clock.c              | 16 ++++++++--------
 arch/arm/mach-exynos/clock_init_exynos5.c |  2 +-
 arch/arm/mach-exynos/common_setup.h       |  4 ++--
 arch/arm/mach-exynos/include/mach/cpu.h   |  6 +++---
 arch/arm/mach-exynos/include/mach/gpio.h  |  4 ++--
 arch/arm/mach-exynos/pinmux.c             |  2 +-
 arch/arm/mach-exynos/power.c              |  2 +-
 7 files changed, 18 insertions(+), 18 deletions(-)

arch/arm/mach-exynos/clock.c +8 -8

index 1c6baa1..2d94851 100644
@@ -159,8 +159,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 			div = PLL_DIV_1024;
 		else if (proid_is_exynos4412())
 			div = PLL_DIV_65535;
-		else if (proid_is_exynos5250() || proid_is_exynos5420()
-			 || proid_is_exynos5800())
+		else if (proid_is_exynos5250() || proid_is_exynos5420() ||
+			 proid_is_exynos5422())
 			div = PLL_DIV_65536;
 		else
 			return 0;

@@ -346,7 +346,7 @@ static struct clk_bit_info *get_clk_bit_info(int peripheral)
 	int i;
 	struct clk_bit_info *info;
 
-	if (proid_is_exynos5420() || proid_is_exynos5800())
+	if (proid_is_exynos5420() || proid_is_exynos5422())
 		info = exynos542x_bit_info;
 	else
 		info = exynos5_bit_info;

@@ -558,7 +558,7 @@ static unsigned long exynos542x_get_periph_rate(int peripheral)
 unsigned long clock_get_periph_rate(int peripheral)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
+		if (proid_is_exynos5420() || proid_is_exynos5422())
 			return exynos542x_get_periph_rate(peripheral);
 		return exynos5_get_periph_rate(peripheral);
 	} else {

@@ -1576,7 +1576,7 @@ static unsigned long exynos4_get_i2c_clk(void)
 unsigned long get_pll_clk(int pllreg)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
+		if (proid_is_exynos5420() || proid_is_exynos5422())
 			return exynos542x_get_pll_clk(pllreg);
 		return exynos5_get_pll_clk(pllreg);
 	} else if (cpu_is_exynos4()) {

@@ -1694,7 +1694,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
 		div -= 1;
 
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
+		if (proid_is_exynos5420() || proid_is_exynos5422())
 			exynos5420_set_mmc_clk(dev_index, div);
 		else
 			exynos5_set_mmc_clk(dev_index, div);

@@ -1710,7 +1710,7 @@ unsigned long get_lcd_clk(void)
 	} else if (cpu_is_exynos5()) {
 		if (proid_is_exynos5420())
 			return exynos5420_get_lcd_clk();
-		else if (proid_is_exynos5800())
+		else if (proid_is_exynos5422())
 			return exynos5800_get_lcd_clk();
 		else
 			return exynos5_get_lcd_clk();

@@ -1742,7 +1742,7 @@ void set_mipi_clk(void)
 int set_spi_clk(int periph_id, unsigned int rate)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
+		if (proid_is_exynos5420() || proid_is_exynos5422())
 			return exynos5420_set_spi_clk(periph_id, rate);
 		return exynos5_set_spi_clk(periph_id, rate);
 	}

arch/arm/mach-exynos/clock_init_exynos5.c +1 -1

index 0200fd1..1b7498d 100644
@@ -971,7 +971,7 @@ static void exynos5420_system_clock_init(void)
 
 void system_clock_init(void)
 {
-	if (proid_is_exynos5420() || proid_is_exynos5800())
+	if (proid_is_exynos5420() || proid_is_exynos5422())
 		exynos5420_system_clock_init();
 	else
 		exynos5250_system_clock_init();

arch/arm/mach-exynos/common_setup.h +2 -2

index 67aac2d..2829fb2 100644
@@ -78,7 +78,7 @@ static inline void configure_l2_ctlr(void)
 		CACHE_TAG_RAM_LATENCY_2_CYCLES |
 		CACHE_DATA_RAM_LATENCY_2_CYCLES;
 
-	if (proid_is_exynos5420() || proid_is_exynos5800()) {
+	if (proid_is_exynos5420() || proid_is_exynos5422()) {
 		val |= CACHE_ECC_AND_PARITY |
 			CACHE_TAG_RAM_LATENCY_3_CYCLES |
 			CACHE_DATA_RAM_LATENCY_3_CYCLES;

@@ -97,7 +97,7 @@ static inline void configure_l2_actlr(void)
 {
 	uint32_t val;
 
-	if (proid_is_exynos5420() || proid_is_exynos5800()) {
+	if (proid_is_exynos5420() || proid_is_exynos5422()) {
 		mrc_l2_aux_ctlr(val);
 		val |= CACHE_ENABLE_FORCE_L2_LOGIC |
 			CACHE_DISABLE_CLEAN_EVICT;

arch/arm/mach-exynos/include/mach/cpu.h +0 -0

index cb3d2cc..14a1692 100644