clk: atlas7: merge lots of discrete clocks into arrays

From: Guo Zeng <[email protected]>

this patch merges lots of discrete dividers, divider tables and dto into arrays, then drops lots of codes.

Signed-off-by Guo Zeng <[email protected]>

Signed-off-by Barry Song <[email protected]>

---
 drivers/clk/sirf/clk-atlas7.c | 211 ++++++++++--------------------------------
 1 file changed, 47 insertions(+), 164 deletions(-)

drivers/clk/sirf/clk-atlas7.c +8 -0

@@ -719,6 +727,24 @@ static struct atlas7_div_init_data divider_list[] __initdata = {
        { "sys2pll_qa20", "sys2pll_fixdiv", "sys2pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 0, &share_div_lock },
        { "sys1pll_qa17", "sys1pll_fixdiv", "sys1pll_a17", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 8, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 20, &share_div_lock },
        { "sys0pll_qa20", "sys0pll_fixdiv", "sys0pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 16, &share_div_lock },
+       { "sys0pll_div1", "sys0pll_vco", "sys0pll_clk1", 1, 0, 0, SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 0, 3, SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 12, &sys0pll_ctrl1_lock },
+       { "sys0pll_div2", "sys0pll_vco", "sys0pll_clk2", 1, 0, 0, SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 4, 3, SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 13, &sys0pll_ctrl1_lock },
+       { "sys0pll_div3", "sys0pll_vco", "sys0pll_clk3", 1, 0, 0, SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 8, 3, SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 14, &sys0pll_ctrl1_lock },
+       { "sys1pll_div1", "sys1pll_vco", "sys1pll_clk1", 1, 0, 0, SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 0, 3, SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 12, &sys1pll_ctrl1_lock },
+       { "sys1pll_div2", "sys1pll_vco", "sys1pll_clk2", 1, 0, 0, SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 4, 3, SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 13, &sys1pll_ctrl1_lock },
+       { "sys1pll_div3", "sys1pll_vco", "sys1pll_clk3", 1, 0, 0, SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 8, 3, SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 14, &sys1pll_ctrl1_lock },
+       { "sys2pll_div1", "sys2pll_vco", "sys2pll_clk1", 1, 0, 0, SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 0, 3, SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 12, &sys2pll_ctrl1_lock },
+       { "sys2pll_div2", "sys2pll_vco", "sys2pll_clk2", 1, 0, 0, SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 4, 3, SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 13, &sys2pll_ctrl1_lock },

drivers/clk/sirf/clk-atlas7.c +21 -164

 };
 
 static const char * const i2s_clk_parents[] = {

@@ -1199,7 +1225,8 @@ static struct atlas7_unit_init_data unit_list[] __initdata = {
        { 141, "thcgum_sys", "sys_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 3, 0, 0, &leaf0_gate_lock },
 };
 
-static struct clk *atlas7_clks[ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list)];
+static struct clk *atlas7_clks[ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list) +
+                       ARRAY_SIZE(divider_list) + ARRAY_SIZE(dto_list)];
 
 static int unit_clk_is_enabled(struct clk_hw *hw)
 {

@@ -1461,88 +1488,14 @@ static void __init atlas7_clk_init(struct device_node *np)
        clk = clk_register(NULL, &clk_sys3pll.hw);
        BUG_ON(!clk);
 
-       clk = clk_register_divider_table(NULL, "cpupll_div1", "cpupll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 0, 3, 0,
-                        pll_div_table, &cpupll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_divider_table(NULL, "cpupll_div2", "cpupll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 4, 3, 0,
-                        pll_div_table, &cpupll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_divider_table(NULL, "cpupll_div3", "cpupll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 8, 3, 0,
-                        pll_div_table, &cpupll_ctrl1_lock);
-       BUG_ON(!clk);
-
-       clk = clk_register_divider_table(NULL, "mempll_div1", "mempll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 0, 3, 0,
-                        pll_div_table, &mempll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_divider_table(NULL, "mempll_div2", "mempll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 4, 3, 0,
-                        pll_div_table, &mempll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_divider_table(NULL, "mempll_div3", "mempll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 8, 3, 0,
-                        pll_div_table, &mempll_ctrl1_lock);
-       BUG_ON(!clk);
-
-       clk = clk_register_divider_table(NULL, "sys0pll_div1", "sys0pll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 0, 3, 0,
-                        pll_div_table, &sys0pll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_divider_table(NULL, "sys0pll_div2", "sys0pll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 4, 3, 0,
-                        pll_div_table, &sys0pll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_divider_table(NULL, "sys0pll_div3", "sys0pll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 8, 3, 0,
-                        pll_div_table, &sys0pll_ctrl1_lock);
-       BUG_ON(!clk);
        clk = clk_register_fixed_factor(NULL, "sys0pll_fixdiv", "sys0pll_vco",
                                        CLK_SET_RATE_PARENT, 1, 2);
-
-       clk = clk_register_divider_table(NULL, "sys1pll_div1", "sys1pll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 0, 3, 0,
-                        pll_div_table, &sys1pll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_divider_table(NULL, "sys1pll_div2", "sys1pll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 4, 3, 0,
-                        pll_div_table, &sys1pll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_divider_table(NULL, "sys1pll_div3", "sys1pll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 8, 3, 0,
-                        pll_div_table, &sys1pll_ctrl1_lock);
        BUG_ON(!clk);
        clk = clk_register_fixed_factor(NULL, "sys1pll_fixdiv", "sys1pll_vco",
                                        CLK_SET_RATE_PARENT, 1, 2);
-
-       clk = clk_register_divider_table(NULL, "sys2pll_div1", "sys2pll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 0, 3, 0,
-                        pll_div_table, &sys2pll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_divider_table(NULL, "sys2pll_div2", "sys2pll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 4, 3, 0,
-                        pll_div_table, &sys2pll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_divider_table(NULL, "sys2pll_div3", "sys2pll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 8, 3, 0,
-                        pll_div_table, &sys2pll_ctrl1_lock);
        BUG_ON(!clk);
        clk = clk_register_fixed_factor(NULL, "sys2pll_fixdiv", "sys2pll_vco",
                                        CLK_SET_RATE_PARENT, 1, 2);
-
-       clk = clk_register_divider_table(NULL, "sys3pll_div1", "sys3pll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 0, 3, 0,
-                        pll_div_table, &sys3pll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_divider_table(NULL, "sys3pll_div2", "sys3pll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 4, 3, 0,
-                        pll_div_table, &sys3pll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_divider_table(NULL, "sys3pll_div3", "sys3pll_vco", 0,
-                        sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 8, 3, 0,
-                        pll_div_table, &sys3pll_ctrl1_lock);
        BUG_ON(!clk);
        clk = clk_register_fixed_factor(NULL, "sys3pll_fixdiv", "sys3pll_vco",
                                        CLK_SET_RATE_PARENT, 1, 2);

@@ -1552,104 +1505,33 @@ static void __init atlas7_clk_init(struct device_node *np)
                                        CLK_SET_RATE_PARENT, 1, 4);
 
        BUG_ON(!clk);
-       clk = clk_register_gate(NULL, "cpupll_clk1", "cpupll_div1",
-               CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1,
-                               12, 0, &cpupll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_gate(NULL, "cpupll_clk2", "cpupll_div2",
-               CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1,
-                               13, 0, &cpupll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_gate(NULL, "cpupll_clk3", "cpupll_div3",
-               CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1,
-                               14, 0, &cpupll_ctrl1_lock);
-       BUG_ON(!clk);
-
-       clk = clk_register_gate(NULL, "mempll_clk1", "mempll_div1",
-               CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
-               sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1,
-               12, 0, &mempll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_gate(NULL, "mempll_clk2", "mempll_div2",
-               CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1,
-                               13, 0, &mempll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_gate(NULL, "mempll_clk3", "mempll_div3",
-               CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1,
-                               14, 0, &mempll_ctrl1_lock);
-       BUG_ON(!clk);
-
-       clk = clk_register_gate(NULL, "sys0pll_clk1", "sys0pll_div1",
-               CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1,
-                               12, 0, &sys0pll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_gate(NULL, "sys0pll_clk2", "sys0pll_div2",
-               CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1,
-                               13, 0, &sys0pll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_gate(NULL, "sys0pll_clk3", "sys0pll_div3",
-               CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1,
-                               14, 0, &sys0pll_ctrl1_lock);
-       BUG_ON(!clk);
-
-       clk = clk_register_gate(NULL, "sys1pll_clk1", "sys1pll_div1",
-               CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1,
-                               12, 0, &sys1pll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_gate(NULL, "sys1pll_clk2", "sys1pll_div2",
-               CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1,
-                               13, 0, &sys1pll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_gate(NULL, "sys1pll_clk3", "sys1pll_div3",
-               CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1,
-                               14, 0, &sys1pll_ctrl1_lock);
-       BUG_ON(!clk);
 
-       clk = clk_register_gate(NULL, "sys2pll_clk1", "sys2pll_div1",
-               CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1,
-                               12, 0, &sys2pll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_gate(NULL, "sys2pll_clk2", "sys2pll_div2",
-               CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1,
-                               13, 0, &sys2pll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_gate(NULL, "sys2pll_clk3", "sys2pll_div3",
-               CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1,
-                               14, 0, &sys2pll_ctrl1_lock);
-       BUG_ON(!clk);
-
-       clk = clk_register_gate(NULL, "sys3pll_clk1", "sys3pll_div1",
-               CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1,
-                               12, 0, &sys3pll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_gate(NULL, "sys3pll_clk2", "sys3pll_div2",
-               CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1,
-                               13, 0, &sys3pll_ctrl1_lock);
-       BUG_ON(!clk);
-       clk = clk_register_gate(NULL, "sys3pll_clk3", "sys3pll_div3",
-               CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1,
-                               14, 0, &sys3pll_ctrl1_lock);
-       BUG_ON(!clk);
-
-       clk = clk_register(NULL, &clk_audio_dto.hw);
-       BUG_ON(!clk);
-
-       clk = clk_register(NULL, &clk_disp0_dto.hw);
-       BUG_ON(!clk);
+       for (i = 0; i < ARRAY_SIZE(dto_list); i++) {
+               clk = clk_register(NULL, &dto_list[i]->hw);
+               BUG_ON(!clk);
 
-       clk = clk_register(NULL, &clk_disp1_dto.hw);
-       BUG_ON(!clk);
+               atlas7_clks[ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list) +
+                       ARRAY_SIZE(divider_list) + i] = clk;
+       }
 
        for (i = 0; i < ARRAY_SIZE(divider_list); i++) {
                div = &divider_list[i];
-               clk = clk_register_divider(NULL, div->div_name,
-                       div->parent_name, div->divider_flags, sirfsoc_clk_vbase + div->div_offset,
-                       div->shift, div->width, 0, div->lock);
+               if (div->flags == SIRFSOC_DIVIDOR_TYPE_TABLE)
+                       clk = clk_register_divider_table(NULL, div->div_name,
+                               div->parent_name, div->divider_flags, sirfsoc_clk_vbase + div->div_offset,
+                               div->shift, div->width, 0, pll_div_table, div->lock);
+               else
+                       clk = clk_register_divider(NULL, div->div_name,
+                               div->parent_name, div->divider_flags, sirfsoc_clk_vbase + div->div_offset,
+                               div->shift, div->width, 0, div->lock);
                BUG_ON(!clk);
+
                clk = clk_register_gate(NULL, div->gate_name, div->div_name,
                        div->gate_flags, sirfsoc_clk_vbase + div->gate_offset,
                                div->gate_bit, 0, div->lock);
                BUG_ON(!clk);
+
+               atlas7_clks[ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list) + i] = clk;
        }
        /* ignore selector status register check */
        for (i = 0; i < ARRAY_SIZE(mux_list); i++) {

@@ -1671,7 +1553,8 @@ static void __init atlas7_clk_init(struct device_node *np)
        }
 
        clk_data.clks = atlas7_clks;
-       clk_data.clk_num = ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list);
+       clk_data.clk_num = ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list) +
+               ARRAY_SIZE(divider_list) + ARRAY_SIZE(dto_list);
 
        ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
        BUG_ON(ret);

Signature · 1 line

1.9.1

Hello Barry,

Quoting Barry Song (2015-10-09 01:05:31)

Quoted 10 lines

From: Guo Zeng <[email protected]>

this patch merges lots of discrete dividers, divider tables and dto into arrays, then drops lots of codes.

Signed-off-by Guo Zeng <[email protected]>

Signed-off-by Barry Song <[email protected]>

---
 drivers/clk/sirf/clk-atlas7.c | 211 ++++++++++--------------------------------
 1 file changed, 47 insertions(+), 164 deletions(-)

Seems like a nice change with a nice diffstat.

Quoted 17 lines

drivers/clk/sirf/clk-atlas7.c +13 -0

@@ -719,6 +727,24 @@ static struct atlas7_div_init_data divider_list[] __initdata = {
        { "sys2pll_qa20", "sys2pll_fixdiv", "sys2pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 0, &share_div_lock },
        { "sys1pll_qa17", "sys1pll_fixdiv", "sys1pll_a17", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 8, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 20, &share_div_lock },
        { "sys0pll_qa20", "sys0pll_fixdiv", "sys0pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 16, &share_div_lock },
+       { "sys0pll_div1", "sys0pll_vco", "sys0pll_clk1", 1, 0, 0, SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 0, 3, SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 12, &sys0pll_ctrl1_lock },
+       { "sys0pll_div2", "sys0pll_vco", "sys0pll_clk2", 1, 0, 0, SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 4, 3, SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 13, &sys0pll_ctrl1_lock },
+       { "sys0pll_div3", "sys0pll_vco", "sys0pll_clk3", 1, 0, 0, SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 8, 3, SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 14, &sys0pll_ctrl1_lock },
+       { "sys1pll_div1", "sys1pll_vco", "sys1pll_clk1", 1, 0, 0, SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 0, 3, SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 12, &sys1pll_ctrl1_lock },
+       { "sys1pll_div2", "sys1pll_vco", "sys1pll_clk2", 1, 0, 0, SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 4, 3, SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 13, &sys1pll_ctrl1_lock },
+       { "sys1pll_div3", "sys1pll_vco", "sys1pll_clk3", 1, 0, 0, SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 8, 3, SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 14, &sys1pll_ctrl1_lock },
+       { "sys2pll_div1", "sys2pll_vco", "sys2pll_clk1", 1, 0, 0, SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 0, 3, SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 12, &sys2pll_ctrl1_lock },
+       { "sys2pll_div2", "sys2pll_vco", "sys2pll_clk2", 1, 0, 0, SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 4, 3, SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 13, &sys2pll_ctrl1_lock },
+       { "sys2pll_div3", "sys2pll_vco", "sys2pll_clk3", 1, 0, 0, SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 8, 3, SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 14, &sys2pll_ctrl1_lock },
+       { "sys3pll_div1", "sys3pll_vco", "sys3pll_clk1", 1, 0, 0, SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 0, 3, SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 12, &sys3pll_ctrl1_lock },
+       { "sys3pll_div2", "sys3pll_vco", "sys3pll_clk2", 1, 0, 0, SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 4, 3, SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 13, &sys3pll_ctrl1_lock },
+       { "sys3pll_div3", "sys3pll_vco", "sys3pll_clk3", 1, 0, 0, SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 8, 3, SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 14, &sys3pll_ctrl1_lock },
+       { "cpupll_div1", "cpupll_vco", "cpupll_clk1", 1, 0, 0, SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 0, 3, SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 12, &cpupll_ctrl1_lock },

drivers/clk/sirf/clk-atlas7.c static struct atlas7_div_init_data divider_list[] __initdata = { · line 747

Quoted 5 lines

drivers/clk/sirf/clk-atlas7.c +5 -0

+       { "cpupll_div2", "cpupll_vco", "cpupll_clk2", 1, 0, 0, SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 4, 3, SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 13, &cpupll_ctrl1_lock },
+       { "cpupll_div3", "cpupll_vco", "cpupll_clk3", 1, 0, 0, SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 8, 3, SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 14, &cpupll_ctrl1_lock },
+       { "mempll_div1", "mempll_vco", "mempll_clk1", 1, 0, 0, SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 0, 3, SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 12, &mempll_ctrl1_lock },
+       { "mempll_div2", "mempll_vco", "mempll_clk2", 1, 0, 0, SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 4, 3, SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 13, &mempll_ctrl1_lock },
+       { "mempll_div3", "mempll_vco", "mempll_clk3", 1, 0, 0, SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 8, 3, SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 14, &mempll_ctrl1_lock },

Checkpatch warns on 23 lines that are over 80 character, including some of the code below in atlas7_clk_init.