arm: discard relocation entries for secure text

The code such as PSCI in section named secure is bundled with u-boot image, and when bootm, the code will be copied to their runtime address same to compliation/linking address - CONFIG_ARMV7_SECURE_BASE.

When compile the PSCI code and link it into the u-boot image, there will be relocation entries in .rel.dyn section for PSCI. Actually, we do not needs these relocation entries.

If still keep the relocation entries in .rel.dyn section, r0 at line 103 and 106 in arch/arm/lib/relocate.S may be an invalid address which may not support read/write for one SoC.

102         /* relative fix: increase location by offset */
103         add     r0, r0, r4
104         ldr     r1, [r0]
105         add     r1, r1, r4
106         str     r1, [r0]

So discard them to avoid touching the relocation entry in arch/arm/lib/relocate.S.

---

V2 thread: http://lists.denx.de/pipermail/u-boot/2015-October/230755.html
Changes v3:
Move the relocation entries to the very begining and discard them.

V1 thread: http://lists.denx.de/pipermail/u-boot/2015-October/229426.html
Changes V2:
Refine commit msg.
Discard the relocation entry section for secure text.

 arch/arm/cpu/u-boot.lds | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

index 03cd9f6..d48a905 100644
@@ -14,6 +14,23 @@ OUTPUT_ARCH(arm)
 ENTRY(_start)
 SECTIONS
 {
+	/*
+	 * Discard the relocation entries for secure text.
+	 * The secure code is bundled with u-boot image, so there will
+	 * be relocations entries for the secure code, since we use
+	 * "-mword-relocations" to compile and "-pie" to link into the
+	 * final image. We do not need the relocation entries for secure
+	 * code, because secure code will not be relocated, it only needs
+	 * to be copied from loading address to CONFIG_ARMV7_SECURE_BASE,
+	 * which is the linking and running address for secure code.
+	 * If keep the relocation entries in .rel.dyn section,
+	 * "relocation offset + linking address" may locates into an
+	 * address that is reserved by SoC, then will trigger data abort.
+	 *
+	 * The reason that move .rel._secure at the beginning, is to
+	 * avoid hole in the final image.
+	 */
+	/DISCARD/ : { *(.rel._secure*) }
 	. = 0x00000000;
 
 	. = ALIGN(4);

1.8.4

1. add basic psci support for imx7 chip.
2. support cpu_on and cpu_off.
3. switch to non-secure mode when boot linux kernel.
4. set csu allow accessing all peripherial register in non-secure mode.

---

Changes V3:
Addressed Fabio and Frank's comments.
http://lists.denx.de/pipermail/u-boot/2015-October/230756.html

Changes V2:
Refine commit msg.

 arch/arm/cpu/armv7/mx7/Makefile   |  4 +++
 arch/arm/cpu/armv7/mx7/psci-mx7.c | 69 +++++++++++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/mx7/psci.S     | 54 ++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/mx7/soc.c      |  9 +++++
 4 files changed, 136 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/mx7/psci-mx7.c
 create mode 100644 arch/arm/cpu/armv7/mx7/psci.S

index e6ecef0..d21f87f 100644
@@ -6,3 +6,7 @@
 #
 
 obj-y	:= soc.o clock.o clock_slice.o
+
+ifdef CONFIG_ARMV7_PSCI
+obj-y  += psci-mx7.o psci.o
+endif

index 2ed05ea..020731d 100644
@@ -114,10 +114,19 @@ u32 __weak get_board_rev(void)
 }
 #endif
 
+/* enable all periherial can be access in nosec mode */
+static void init_csu(void)
+{
+	int i = 0;
+	for (i = 0; i < 64; i++)
+		writel(0x00FF00FF, 0x303e0000 + i * 4);
+}
+
 int arch_cpu_init(void)
 {
 	init_aips();
 
+	init_csu();
 	/* Disable PDE bit of WMCR register */
 	imx_set_wdog_powerdown(false);
 

1.8.4

Oh. I missed this part.
Will use macro for the two value.

Regards,
Peng.

Support PSCI and switch to non-secure mode when booting linux.

---

Changes V3:
none

Changes V2:
default no enable CONFIG_ARMV7_VIRT

 include/configs/mx7_common.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

index ea2be49..e3a70b8 100644
@@ -92,4 +92,15 @@
 #define CONFIG_CMD_FUSE
 #define CONFIG_MXC_OCOTP
 
+/*
+ * Default boot linux kernel in no secure mode.
+ * If want to boot kernel in secure mode, please define CONFIG_MX7_SEC
+ */
+#ifndef CONFIG_MX7_SEC
+#define CONFIG_ARMV7_NONSEC		1
+#define CONFIG_ARMV7_PSCI		1
+#define CONFIG_ARMV7_PSCI_NR_CPUS	2
+#define CONFIG_ARMV7_SECURE_BASE	0x00900000
+#endif
+
 #endif

1.8.4

I saw sunxi also have 1. Does it hurt?

It does not hurt, but is not needed. Please remove it from this patch.