ARM: k2g: Add support for 66AK2G02

index f98a24e..cbb836c 100644
@@ -247,6 +247,7 @@ typedef volatile unsigned int   *dv_reg_p;
 #define CPU_66AK2Hx	0xb981
 #define CPU_66AK2Ex	0xb9a6
 #define CPU_66AK2Lx	0xb9a7
+#define CPU_66AK2Gx	0xbb06
 
 /* DEVSPEED register */
 #define DEVSPEED_DEVSPEED_SHIFT	16

@@ -291,6 +292,11 @@ static inline u8 cpu_is_k2l(void)
 	return get_part_number() == CPU_66AK2Lx;
 }
 
+static inline u8 cpu_is_k2g(void)
+{
+	return get_part_number() == CPU_66AK2Gx;
+}
+
 static inline u8 cpu_revision(void)
 {
 	u32 jtag_id	= __raw_readl(KS2_JTAG_ID_REG);

index 678afb1..1157214 100644
@@ -169,6 +169,9 @@ int print_cpuinfo(void)
 	case CPU_66AK2Ex:
 		puts("66AK2Ex SR");
 		break;
+	case CPU_66AK2Gx:
+		puts("66AK2Gx SR");
+		break;
 	default:
 		puts("Unknown\n");
 	}

index fc3eadb..31ae936 100644
@@ -31,6 +31,7 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
 	[TETRIS_PLL]	= {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
 	[DDR3A_PLL]	= {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
 	[DDR3B_PLL]	= {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
+	[UART_PLL]	= {KS2_UARTPLLCTL0, KS2_UARTPLLCTL1},
 };
 
 static void wait_for_completion(const struct pll_init_data *data)

@@ -309,6 +310,10 @@ static unsigned long pll_freq_get(int pll)
 			ret = external_clk[ddr3b_clk];
 			reg = KS2_DDR3BPLLCTL0;
 			break;
+		case UART_PLL:
+			ret = external_clk[uart_clk];
+			reg = KS2_UARTPLLCTL0;
+			break;
 		default:
 			return 0;
 		}

new file mode 100644
index 0000000..4d3f92e
@@ -0,0 +1,18 @@
+/*
+ * K2G: Clock data
+ *
+ * (C) Copyright 2015
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_K2G_H
+#define __ASM_ARCH_CLOCK_K2G_H
+
+#define PLLSET_CMD_LIST		"<pa|arm|ddr3>"
+
+#define DEV_SUPPORTED_SPEEDS	0xfff
+#define ARM_SUPPORTED_SPEEDS	0xfff
+
+#endif

index ddc5f8e..0a59fa0 100644
@@ -24,8 +24,13 @@
 #include <asm/arch/clock-k2l.h>
 #endif
 
+#ifdef CONFIG_SOC_K2G
+#include <asm/arch/clock-k2g.h>
+#endif
+
 #define CORE_PLL MAIN_PLL
 #define DDR3_PLL DDR3A_PLL
+#define NSS_PLL PASS_PLL
 
 #define CLK_LIST(CLK)\
 	CLK(0, core_pll_clk)\

@@ -75,6 +80,7 @@ enum {
 	PASS_PLL,
 	DDR3A_PLL,
 	DDR3B_PLL,
+	UART_PLL,
 	MAX_PLL_COUNT,
 };
 

index cbb836c..2c5167e 100644
@@ -167,6 +167,8 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_DDR3BPLLCTL1		(KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
 #define KS2_ARMPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x370)
 #define KS2_ARMPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x374)
+#define KS2_UARTPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x390)
+#define KS2_UARTPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x394)
 
 #define KS2_PLL_CNTRL_BASE		0x02310000
 #define KS2_CLOCK_BASE			KS2_PLL_CNTRL_BASE

63 lines not on this page · raw message

index 011c03c..4b5ea05 100644
@@ -49,7 +49,11 @@
 #define MAC_ID_BASE_ADDR		CONFIG_KSNET_MAC_ID_BASE
 
 /* MDIO module input frequency */
+#ifdef CONFIG_SOC_K2G
+#define EMAC_MDIO_BUS_FREQ		(clk_get_rate(sys_clk0_3_clk))
+#else
 #define EMAC_MDIO_BUS_FREQ		(clk_get_rate(pass_pll_clk))
+#endif
 /* MDIO clock output frequency */
 #define EMAC_MDIO_CLOCK_FREQ		2500000	/* 2.5 MHz */
 

index 31ae936..5d37ac3 100644
@@ -356,6 +356,10 @@ unsigned long clk_get_rate(unsigned int clk)
 		if (cpu_is_k2hk())
 			freq = pll_freq_get(DDR3B_PLL);
 		break;
+	case uart_pll_clk:
+		if (cpu_is_k2g())
+			freq = pll_freq_get(UART_PLL);
+		break;
 	case sys_clk0_1_clk:
 	case sys_clk0_clk:
 		freq = pll_freq_get(CORE_PLL) / pll0div_read(1);

index 73ceb83..a539d5d 100644
@@ -37,7 +37,7 @@ static int do_mon_install(cmd_tbl_t *cmdtp, int flag, int argc,
 	if (argc < 2)
 		return CMD_RET_USAGE;
 
-	freq = clk_get_rate(sys_clk0_6_clk);
+	freq = CONFIG_SYS_HZ_CLOCK;
 
 	addr = simple_strtoul(argv[1], NULL, 16);
 

index 4d3f92e..214c1d3 100644
@@ -15,4 +15,6 @@
 #define DEV_SUPPORTED_SPEEDS	0xfff
 #define ARM_SUPPORTED_SPEEDS	0xfff
 
+#define KS2_CLK1_6 sys_clk0_6_clk
+
 #endif

index 0a59fa0..05c2a76 100644
@@ -53,7 +53,8 @@
 	CLK(17, sys_clk1_6_clk)\
 	CLK(18, sys_clk1_12_clk)\
 	CLK(19, sys_clk2_clk)\
-	CLK(20, sys_clk3_clk)
+	CLK(20, sys_clk3_clk)\
+	CLK(21, uart_pll_clk)
 
 #include <asm/types.h>
 

@@ -91,6 +92,7 @@ enum ext_clk_e {
 	tetris_clk,
 	ddr3a_clk,
 	ddr3b_clk,
+	uart_clk,
 	ext_clk_count /* number of external clocks */
 };
 

index 6234baa..2d4602f 100644
@@ -9,6 +9,16 @@
 #include <common.h>
 #include <asm/arch/clock.h>
 
+#define SYS_CLK		24000000
+
+unsigned int external_clk[ext_clk_count] = {
+	[sys_clk]	=	SYS_CLK,
+	[pa_clk]	=	SYS_CLK,
+	[tetris_clk]	=	SYS_CLK,
+	[ddr3a_clk]	=	SYS_CLK,
+	[uart_clk]	=	SYS_CLK,
+};
+
 static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4};
 static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4};
 static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};

index 1830760..ed86561 100644
@@ -68,9 +68,14 @@
 #endif
 #define CONFIG_SYS_NS16550_COM1		KS2_UART0_BASE
 #define CONFIG_SYS_NS16550_COM2		KS2_UART1_BASE
-#define CONFIG_SYS_NS16550_CLK		clk_get_rate(KS2_CLK1_6)
 #define CONFIG_CONS_INDEX		1
 
+#ifndef CONFIG_SOC_K2G
+#define CONFIG_SYS_NS16550_CLK		clk_get_rate(KS2_CLK1_6)
+#else
+#define CONFIG_SYS_NS16550_CLK		clk_get_rate(uart_pll_clk) / 2
+#endif
+
 /* SPI Configuration */
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_DAVINCI_SPI

@@ -302,6 +307,10 @@
 /* we may include files below only after all above definitions */
 #include <asm/arch/hardware.h>
 #include <asm/arch/clock.h>
+#ifndef CONFIG_SOC_K2G
 #define CONFIG_SYS_HZ_CLOCK		clk_get_rate(KS2_CLK1_6)
+#else
+#define CONFIG_SYS_HZ_CLOCK		external_clk[sys_clk]
+#endif
 
 #endif /* __CONFIG_KS2_EVM_H */

new file mode 100644
index 0000000..646ea85
@@ -0,0 +1,51 @@
+/*
+ * K2G: SoC definitions
+ *
+ * (C) Copyright 2015
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_K2G_H
+#define __ASM_ARCH_HARDWARE_K2G_H
+
+#define KS2_NUM_DSPS	0
+
+/* Power and Sleep Controller (PSC) Domains */
+#define KS2_LPSC_ALWAYSON		0
+#define KS2_LPSC_PMMC			1
+#define KS2_LPSC_DEBUG			2
+#define KS2_LPSC_NSS			3
+#define KS2_LPSC_SA			4
+#define KS2_LPSC_TERANET		5
+#define KS2_LPSC_SYS_COMP		6
+#define KS2_LPSC_QSPI			7
+#define KS2_LPSC_MMC			8
+#define KS2_LPSC_GPMC			9
+#define KS2_LPSC_MLB			11
+#define KS2_LPSC_EHRPWM			12
+#define KS2_LPSC_EQEP			13
+#define KS2_LPSC_ECAP			14
+#define KS2_LPSC_MCASP			15
+#define KS2_LPSC_SR			16
+#define KS2_LPSC_MSMC			17
+#define KS2_LPSC_GEM			18
+#define KS2_LPSC_ARM			19
+#define KS2_LPSC_ASRC			20
+#define KS2_LPSC_ICSS			21
+#define KS2_LPSC_DSS			23
+#define KS2_LPSC_PCIE			24
+#define KS2_LPSC_USB_0			25
+#define KS2_LPSC_USB			KS2_LPSC_USB_0
+#define KS2_LPSC_USB_1			26
+#define KS2_LPSC_DDR3			27
+#define KS2_LPSC_SPARE0_LPSC0		28
+#define KS2_LPSC_SPARE0_LPSC1		29
+#define KS2_LPSC_SPARE1_LPSC0		30
+#define KS2_LPSC_SPARE1_LPSC1		31
+
+#define KS2_LPSC_CPGMAC			KS2_LPSC_NSS
+#define KS2_LPSC_CRYPTO			KS2_LPSC_SA
+
+#endif /* __ASM_ARCH_HARDWARE_K2G_H */

index 2c5167e..a99713a 100644
@@ -270,6 +270,10 @@ typedef volatile unsigned int   *dv_reg_p;
 #include <asm/arch/hardware-k2l.h>
 #endif
 
+#ifdef CONFIG_SOC_K2G
+#include <asm/arch/hardware-k2g.h>
+#endif
+
 #ifndef __ASSEMBLY__
 
 static inline u16 get_part_number(void)

index dfb27b5..34606f4 100644
@@ -52,7 +52,8 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
 	__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
 	__raw_writel(phy_cfg->mr0,   base + KS2_DDRPHY_MR0_OFFSET);
 	__raw_writel(phy_cfg->mr1,   base + KS2_DDRPHY_MR1_OFFSET);
-	__raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
+	if (!cpu_is_k2g())
+		__raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
 	__raw_writel(phy_cfg->dtcr,  base + KS2_DDRPHY_DTCR_OFFSET);
 	__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
 

@@ -64,6 +65,15 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
 	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
 		;
 
+	/* Disable ECC for K2G */
+	if (cpu_is_k2g()) {
+		clrbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
+		clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1);
+		clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1);
+		clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);
+		clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1);
+	}
+
 	__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
 	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
 		;

index a99713a..2fd5b23 100644
@@ -52,6 +52,10 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_DDRPHY_ZQ2CR1_OFFSET        0x1A4
 #define KS2_DDRPHY_ZQ3CR1_OFFSET        0x1B4
 
+#define KS2_DDRPHY_DATX8_4_OFFSET       0x2C0
+#define KS2_DDRPHY_DATX8_5_OFFSET       0x300
+#define KS2_DDRPHY_DATX8_6_OFFSET       0x340
+#define KS2_DDRPHY_DATX8_7_OFFSET       0x380
 #define KS2_DDRPHY_DATX8_8_OFFSET       0x3C0
 
 #define IODDRM_MASK                     0x00000180

index 859a260..73c13fc 100644
@@ -42,7 +42,8 @@ int dram_init(void)
 	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 				    CONFIG_MAX_RAM_BANK_SIZE);
 	aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
-	ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
+	if (ddr3_size)
+		ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
 	return 0;
 }
 

index 2d4602f..81cef70 100644
@@ -23,7 +23,7 @@ static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4};
 static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4};
 static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
 static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
-static struct pll_init_data ddr3_pll_config = {DDR3_PLL, 250, 3, 10};
+static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};
 
 struct pll_init_data *get_pll_init_data(int pll)
 {

@@ -34,7 +34,7 @@ struct pll_init_data *get_pll_init_data(int pll)
 		data = &main_pll_config;
 		break;
 	case TETRIS_PLL:
-		data = &tetris_pll_config[speed];
+		data = &tetris_pll_config;
 		break;
 	case NSS_PLL:
 		data = &nss_pll_config;

@@ -43,7 +43,7 @@ struct pll_init_data *get_pll_init_data(int pll)
 		data = &uart_pll_config;
 		break;
 	case DDR3_PLL:
-		data = &ddr_pll_config;
+		data = &ddr3_pll_config;
 		break;
 	default:
 		data = NULL;

64 lines not on this page · raw message

new file mode 100644
index 0000000..6167d2c
@@ -0,0 +1,58 @@
+/*
+ * K2G: Pinmux configuration
+ *
+ * (C) Copyright 2015
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MUX_K2G_H
+#define __ASM_ARCH_MUX_K2G_H
+
+#include <common.h>
+#include <asm/io.h>
+
+#define K2G_PADCFG_REG	(KS2_DEVICE_STATE_CTRL_BASE + 0x1000)
+
+/*
+ * 20:19 - buffer class RW fixed
+ * 18    - rxactive (Input enabled for the pad ) 0 - Di; 1 - En;
+ * 17    - pulltypesel (0 - PULLDOWN; 1 - PULLUP);
+ * 16    - pulluden (0 - PULLUP/DOWN EN; 1 - DI);
+ * 3:0   - muxmode (available modes 0:5)
+ */
+
+#define PIN_IEN	(1 << 18) /* pin input enabled */
+#define PIN_PDIS	(1 << 16) /* pull up/down disabled */
+#define PIN_PTU	(1 << 17) /* pull up */
+#define PIN_PTD	(0 << 17) /* pull down */
+
+#define MODE(m)	((m) & 0x7)
+#define MAX_PIN_N	260
+
+#define MUX_CFG(value, index)  \
+	__raw_writel(\
+		     (value) | \
+		     (__raw_readl(K2G_PADCFG_REG + (index << 2)) & \
+		      (0x3 << 19)),\
+		     (K2G_PADCFG_REG + (index << 2))\
+		    );
+
+struct pin_cfg {
+	int	reg_inx;
+	u32	val;
+};
+
+static inline void configure_pin_mux(struct pin_cfg *pin_mux)
+{
+	if (!pin_mux)
+		return;
+
+	while ((pin_mux->reg_inx >= 0) && (pin_mux->reg_inx < MAX_PIN_N)) {
+		MUX_CFG(pin_mux->val, pin_mux->reg_inx);
+		pin_mux++;
+	}
+}
+
+#endif /* __ASM_ARCH_MUX_K2G_H */

index 81cef70..3852138 100644
@@ -8,6 +8,7 @@
  */
 #include <common.h>
 #include <asm/arch/clock.h>
+#include "mux-k2g.h"
 
 #define SYS_CLK		24000000
 

@@ -61,6 +62,8 @@ int board_early_init_f(void)
 {
 	init_plls();
 
+	k2g_mux_config();
+
 	return 0;
 }
 #endif

313 lines not on this page · raw message

index 646ea85..fa4162f 100644
@@ -48,4 +48,27 @@
 #define KS2_LPSC_CPGMAC			KS2_LPSC_NSS
 #define KS2_LPSC_CRYPTO			KS2_LPSC_SA
 
+/* SGMII SerDes */
+#define KS2_LANES_PER_SGMII_SERDES	4
+
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE	0x04010000
+#define KS2_NETCP_PDMA_TX_BASE		0x04011000
+#define KS2_NETCP_PDMA_TX_CH_NUM	21
+#define KS2_NETCP_PDMA_RX_BASE		0x04012000
+#define KS2_NETCP_PDMA_RX_CH_NUM	32
+#define KS2_NETCP_PDMA_SCHED_BASE	0x04010100
+#define KS2_NETCP_PDMA_RX_FLOW_BASE	0x04013000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM	32
+#define KS2_NETCP_PDMA_TX_SND_QUEUE	5
+
+/* NETCP */
+#define KS2_NETCP_BASE			0x04000000
+
+#define K2G_GPIO0_BASE			0X02603000
+#define K2G_GPIO1_BASE			0X0260a000
+#define K2G_GPIO1_BANK2_BASE		K2G_GPIO1_BASE + 0x38
+#define K2G_GPIO_DIR_OFFSET		0x0
+#define K2G_GPIO_SETDATA_OFFSET		0x8
+
 #endif /* __ASM_ARCH_HARDWARE_K2G_H */

index 2fd5b23..286c63a 100644
@@ -147,6 +147,8 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_JTAG_ID_REG			(KS2_DEVICE_STATE_CTRL_BASE + 0x18)
 #define KS2_DEVSTAT			(KS2_DEVICE_STATE_CTRL_BASE + 0x20)
 #define KS2_DEVCFG			(KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
+#define KS2_ETHERNET_CFG		(KS2_DEVICE_STATE_CTRL_BASE + 0xe20)
+#define KS2_ETHERNET_RGMII		2
 
 /* PSC */
 #define KS2_PSC_BASE			0x02350000

@@ -185,10 +187,17 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_RSTYPE_PLL_SOFT		BIT(13)
 
 /* SPI */
+#ifdef CONFIG_SOC_K2G
+#define KS2_SPI0_BASE			0x21805400
+#define KS2_SPI1_BASE			0x21805800
+#define KS2_SPI2_BASE			0x21805c00
+#define KS2_SPI3_BASE			0x21806000
+#else
 #define KS2_SPI0_BASE			0x21000400
 #define KS2_SPI1_BASE			0x21000600
 #define KS2_SPI2_BASE			0x21000800
 #define KS2_SPI_BASE			KS2_SPI0_BASE
+#endif
 
 /* AEMIF */
 #define KS2_AEMIF_CNTRL_BASE       	0x21000a00

@@ -200,10 +209,16 @@ typedef volatile unsigned int   *dv_reg_p;
 /* MSMC control */
 #define KS2_MSMC_CTRL_BASE		0x0bc00000
 #define KS2_MSMC_DATA_BASE		0x0c000000
+#ifndef CONFIG_SOC_K2G
 #define KS2_MSMC_SEGMENT_TETRIS		8
 #define KS2_MSMC_SEGMENT_NETCP		9
 #define KS2_MSMC_SEGMENT_QM_PDSP	10
 #define KS2_MSMC_SEGMENT_PCIE0		11
+#else
+#define KS2_MSMC_SEGMENT_TETRIS		1
+#define KS2_MSMC_SEGMENT_NETCP		4
+#define KS2_MSMC_SEGMENT_PCIE0		5
+#endif
 
 /* MSMC segment size shift bits */
 #define KS2_MSMC_SEG_SIZE_SHIFT		12

@@ -217,6 +232,22 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_MISC_CTRL			(KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
 
 /* Queue manager */
+#ifdef CONFIG_SOC_K2G
+#define KS2_QM_BASE_ADDRESS		0x040C0000
+#define KS2_QM_CONF_BASE		0x04040000
+#define KS2_QM_DESC_SETUP_BASE		0x04080000
+#define KS2_QM_STATUS_RAM_BASE		0x0 /* K2G doesn't have it */
+#define KS2_QM_INTD_CONF_BASE		0x0
+#define KS2_QM_PDSP1_CMD_BASE		0x0
+#define KS2_QM_PDSP1_CTRL_BASE		0x0
+#define KS2_QM_PDSP1_IRAM_BASE		0x0
+#define KS2_QM_MANAGER_QUEUES_BASE	0x040c0000
+#define KS2_QM_MANAGER_Q_PROXY_BASE	0x04040200
+#define KS2_QM_QUEUE_STATUS_BASE	0x04100000
+#define KS2_QM_LINK_RAM_BASE		0x04020000
+#define KS2_QM_REGION_NUM		8
+#define KS2_QM_QPOOL_NUM		112
+#else
 #define KS2_QM_BASE_ADDRESS		0x23a80000
 #define KS2_QM_CONF_BASE		0x02a02000
 #define KS2_QM_DESC_SETUP_BASE		0x02a03000

@@ -231,6 +262,7 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_QM_LINK_RAM_BASE		0x00100000
 #define KS2_QM_REGION_NUM		64
 #define KS2_QM_QPOOL_NUM		4000
+#endif
 
 /* USB */
 #define KS2_USB_SS_BASE			0x02680000

index 1157214..aadd10b 100644
@@ -103,7 +103,9 @@ int arch_cpu_init(void)
 
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
+#ifdef KS2_MSMC_SEGMENT_QM_PDSP
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
+#endif
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
 
 	/* Initialize the PCIe-0 to work as Root Complex */

index 286c63a..edebcd7 100644
@@ -125,8 +125,13 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_EDMA_PARAM_1(x)		(0x4020 + (4 * x))
 
 /* NETCP pktdma */
+#ifdef CONFIG_SOC_K2G
+#define KS2_NETCP_PDMA_RX_FREE_QUEUE	113
+#define KS2_NETCP_PDMA_RX_RCV_QUEUE	114
+#else
 #define KS2_NETCP_PDMA_RX_FREE_QUEUE	4001
 #define KS2_NETCP_PDMA_RX_RCV_QUEUE	4002
+#endif
 
 /* Chip Interrupt Controller */
 #define KS2_CIC2_BASE			0x02608000

index 4b5ea05..43a6568 100644
@@ -11,6 +11,7 @@
 #define _KEYSTONE_NET_H_
 
 #include <asm/io.h>
+#include <phy.h>
 
 /* EMAC */
 #ifdef CONFIG_KSNET_NETCP_V1_0

@@ -243,6 +244,7 @@ struct eth_priv_t {
 	int phy_addr;
 	int slave_port;
 	int sgmii_link_type;
+	phy_interface_t phy_if;
 	struct phy_device *phy_dev;
 };
 

index dc00cf6..f58f623 100644
@@ -82,6 +82,7 @@ struct eth_priv_t eth_priv_cfg[] = {
 		.phy_addr        = 0,
 		.slave_port      = 1,
 		.sgmii_link_type = SGMII_LINK_MAC_PHY,
+		.phy_if          = PHY_INTERFACE_MODE_SGMII,
 	},
 	{
 		.int_name        = "K2E_EMAC1",

@@ -89,6 +90,7 @@ struct eth_priv_t eth_priv_cfg[] = {
 		.phy_addr        = 1,
 		.slave_port      = 2,
 		.sgmii_link_type = SGMII_LINK_MAC_PHY,
+		.phy_if          = PHY_INTERFACE_MODE_SGMII,
 	},
 	{
 		.int_name        = "K2E_EMAC2",

@@ -96,6 +98,7 @@ struct eth_priv_t eth_priv_cfg[] = {
 		.phy_addr        = 2,
 		.slave_port      = 3,
 		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+		.phy_if          = PHY_INTERFACE_MODE_SGMII,
 	},
 	{
 		.int_name        = "K2E_EMAC3",

@@ -103,6 +106,7 @@ struct eth_priv_t eth_priv_cfg[] = {
 		.phy_addr        = 3,
 		.slave_port      = 4,
 		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+		.phy_if          = PHY_INTERFACE_MODE_SGMII,
 	},
 	{
 		.int_name        = "K2E_EMAC4",

@@ -110,6 +114,7 @@ struct eth_priv_t eth_priv_cfg[] = {
 		.phy_addr        = 4,
 		.slave_port      = 5,
 		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+		.phy_if          = PHY_INTERFACE_MODE_SGMII,
 	},
 	{
 		.int_name        = "K2E_EMAC5",

@@ -117,6 +122,7 @@ struct eth_priv_t eth_priv_cfg[] = {
 		.phy_addr        = 5,
 		.slave_port      = 6,
 		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+		.phy_if          = PHY_INTERFACE_MODE_SGMII,
 	},
 	{
 		.int_name        = "K2E_EMAC6",

@@ -124,6 +130,7 @@ struct eth_priv_t eth_priv_cfg[] = {
 		.phy_addr        = 6,
 		.slave_port      = 7,
 		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+		.phy_if          = PHY_INTERFACE_MODE_SGMII,
 	},
 	{
 		.int_name        = "K2E_EMAC7",

@@ -131,6 +138,7 @@ struct eth_priv_t eth_priv_cfg[] = {
 		.phy_addr        = 7,
 		.slave_port      = 8,
 		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+		.phy_if          = PHY_INTERFACE_MODE_SGMII,
 	},
 };
 

index 6e681d7..0bd6b86 100644
@@ -76,6 +76,7 @@ struct eth_priv_t eth_priv_cfg[] = {
 		.phy_addr	= 0,
 		.slave_port	= 1,
 		.sgmii_link_type = SGMII_LINK_MAC_PHY,
+		.phy_if          = PHY_INTERFACE_MODE_SGMII,
 	},
 	{
 		.int_name	= "K2HK_EMAC1",

@@ -83,6 +84,7 @@ struct eth_priv_t eth_priv_cfg[] = {
 		.phy_addr	= 1,
 		.slave_port	= 2,
 		.sgmii_link_type = SGMII_LINK_MAC_PHY,
+		.phy_if          = PHY_INTERFACE_MODE_SGMII,
 	},
 	{
 		.int_name	= "K2HK_EMAC2",

@@ -90,6 +92,7 @@ struct eth_priv_t eth_priv_cfg[] = {
 		.phy_addr	= 2,
 		.slave_port	= 3,
 		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+		.phy_if          = PHY_INTERFACE_MODE_SGMII,
 	},
 	{
 		.int_name	= "K2HK_EMAC3",

@@ -97,6 +100,7 @@ struct eth_priv_t eth_priv_cfg[] = {
 		.phy_addr	= 3,
 		.slave_port	= 4,
 		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+		.phy_if          = PHY_INTERFACE_MODE_SGMII,
 	},
 };
 

index f35a64f..d750ad3 100644
@@ -75,6 +75,7 @@ struct eth_priv_t eth_priv_cfg[] = {
 		.phy_addr        = 0,
 		.slave_port      = 1,
 		.sgmii_link_type = SGMII_LINK_MAC_PHY,
+		.phy_if          = PHY_INTERFACE_MODE_SGMII,
 	},
 	{
 		.int_name        = "K2L_EMAC1",

@@ -82,6 +83,7 @@ struct eth_priv_t eth_priv_cfg[] = {
 		.phy_addr        = 1,
 		.slave_port      = 2,
 		.sgmii_link_type = SGMII_LINK_MAC_PHY,
+		.phy_if          = PHY_INTERFACE_MODE_SGMII,
 	},
 	{
 		.int_name        = "K2L_EMAC2",

@@ -89,6 +91,7 @@ struct eth_priv_t eth_priv_cfg[] = {
 		.phy_addr        = 2,
 		.slave_port      = 3,
 		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+		.phy_if          = PHY_INTERFACE_MODE_SGMII,
 	},
 	{
 		.int_name        = "K2L_EMAC3",

@@ -96,6 +99,7 @@ struct eth_priv_t eth_priv_cfg[] = {
 		.phy_addr        = 3,
 		.slave_port      = 4,
 		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+		.phy_if          = PHY_INTERFACE_MODE_SGMII,
 	},
 };
 

index 67b5702..2e64e7c 100644
@@ -569,11 +569,11 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
 	/* Create phy device and bind it with driver */
 #ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
 	phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
-			      dev, PHY_INTERFACE_MODE_SGMII);
+			      dev, eth_priv->phy_if);
 	phy_config(phy_dev);
 #else
 	phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
-				   PHY_INTERFACE_MODE_SGMII);
+				   eth_priv->phy_if);
 	phy_dev->dev = dev;
 #endif
 	eth_priv->phy_dev = phy_dev;

index dfca75a..5a65b62 100644
@@ -54,7 +54,7 @@ int _qm_init(struct qm_config *cfg)
 	qm_cfg = cfg;
 
 	qm_cfg->mngr_cfg->link_ram_base0	= qm_cfg->i_lram;
-	qm_cfg->mngr_cfg->link_ram_size0	= HDESC_NUM * 8;
+	qm_cfg->mngr_cfg->link_ram_size0	= HDESC_NUM * 8 - 1;
 	qm_cfg->mngr_cfg->link_ram_base1	= 0;
 	qm_cfg->mngr_cfg->link_ram_size1	= 0;
 	qm_cfg->mngr_cfg->link_ram_base2	= 0;

index 43a6568..a0d0d9b 100644
@@ -193,6 +193,11 @@ struct mac_sl_cfg {
 #define SGMII_RXCFG_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
 #define SGMII_AUXCFG_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
 
+/* RGMII */
+#define RGMII_REG_STATUS_LINK		BIT(0)
+
+#define RGMII_STATUS_REG		(GBETH_BASE + 0x18)
+
 /* PSS */
 #ifdef CONFIG_KSNET_NETCP_V1_0
 

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index 897d867..5ed29ae 100644
@@ -163,16 +163,6 @@ static void  __attribute__((unused))
 	       DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
 }
 
-int keystone_sgmii_link_status(int port)
-{
-	u32 status = 0;
-
-	status = __raw_readl(SGMII_STATUS_REG(port));
-
-	return (status & SGMII_REG_STATUS_LOCK) &&
-	       (status & SGMII_REG_STATUS_LINK);
-}
-
 #ifdef CONFIG_SOC_K2G
 int keystone_rgmii_config(struct phy_device *phy_dev)
 {

index 73c13fc..4d7b9de 100644
@@ -74,9 +74,14 @@ int board_eth_init(bd_t *bis)
 	int port_num;
 	char link_type_name[32];
 
+	if (cpu_is_k2g())
+		writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
+
 	/* By default, select PA PLL clock as PA clock source */
+#ifndef CONFIG_SOC_K2G
 	if (psc_enable_module(KS2_LPSC_PA))
 		return -1;
+#endif
 	if (psc_enable_module(KS2_LPSC_CPGMAC))
 		return -1;
 	if (psc_enable_module(KS2_LPSC_CRYPTO))

index 3852138..b2bc793 100644
@@ -8,6 +8,7 @@
  */
 #include <common.h>
 #include <asm/arch/clock.h>
+#include <asm/ti-common/keystone_net.h>
 #include "mux-k2g.h"
 
 #define SYS_CLK		24000000

@@ -74,3 +75,21 @@ void spl_init_keystone_plls(void)
 	init_plls();
 }
 #endif
+
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+struct eth_priv_t eth_priv_cfg[] = {
+	{
+		.int_name	= "K2G_EMAC",
+		.rx_flow	= 0,
+		.phy_addr	= 0,
+		.slave_port	= 1,
+		.sgmii_link_type = SGMII_LINK_MAC_PHY,
+		.phy_if          = PHY_INTERFACE_MODE_RGMII,
+	},
+};
+
+int get_num_eth_ports(void)
+{
+	return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
+}
+#endif

new file mode 100644
index 0000000..a5050ac
@@ -0,0 +1,22 @@
+/*
+ * K2G: MMC
+ *
+ * (C) Copyright 2015
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef K2G_MMC_HOST_DEF_H
+#define K2G_MMC_HOST_DEF_H
+
+#include <asm/omap_mmc.h>
+
+/*
+ * OMAP HSMMC register definitions
+ */
+
+#define OMAP_HSMMC1_BASE	0x23000100
+#define OMAP_HSMMC2_BASE	0x23100100
+
+#endif /* K2G_MMC_HOST_DEF_H */

index b2bc793..3e1dd4c 100644
@@ -9,6 +9,8 @@
 #include <common.h>
 #include <asm/arch/clock.h>
 #include <asm/ti-common/keystone_net.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/mmc_host_def.h>
 #include "mux-k2g.h"
 
 #define SYS_CLK		24000000

@@ -58,6 +60,20 @@ s16 divn_val[16] = {
 	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 };
 
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+	if (psc_enable_module(KS2_LPSC_MMC)) {
+		printf("%s module enabled failed\n", __func__);
+		return -1;
+	}
+
+	omap_mmc_init(0, 0, 0, -1, -1);
+	omap_mmc_init(1, 0, 0, -1, -1);
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {

index d7b388f..5b74a5a 100644
@@ -31,10 +31,12 @@
 #include <twl4030.h>
 #include <twl6030.h>
 #include <palmas.h>
-#include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/mmc_host_def.h>
+#if !defined(CONFIG_SOC_KEYSTONE)
+#include <asm/gpio.h>
 #include <asm/arch/sys_proto.h>
+#endif
 
 /* simplify defines to OMAP_HSMMC_USE_GPIO */
 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \

@@ -662,7 +664,8 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 	defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) || \
-	defined(CONFIG_AM43XX)) && defined(CONFIG_HSMMC2_8BIT)
+	defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
+		defined(CONFIG_HSMMC2_8BIT)
 		/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
 		host_caps_val |= MMC_MODE_8BIT;
 #endif

index 3e1dd4c..cdeb056 100644
@@ -81,6 +81,12 @@ int board_early_init_f(void)
 
 	k2g_mux_config();
 
+	/* deassert FLASH_HOLD */
+	clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
+		     BIT(9));
+	setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
+		     BIT(9));
+
 	return 0;
 }
 #endif

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