Trustzone: DSB before/after SMC
Hello,
I have a few questions about SMC. (I'm using Cortex-A9)
Platforms that use SMC often/always execute DSB beforehand.
1a) Is DSB required before SMC?
1b) Is DSB required after SMC?
2a) Is DSB required before returning to non-secure OS? 2b) Is DSB required after returning to non-secure OS?
3) Is this documented in the ARM ARM?
Bonus question: if DSB is required before SMC, why didn't ARM make SMC implicitly do a DSB?
Regards.
Quoted 5 lines · Mason
Hello,
I have a few questions about SMC. (I'm using Cortex-A9)
Platforms that use SMC often/always execute DSB beforehand.
Please give an example. We don't do this for PSCI, for instance.
Quoted 4 lines
1a) Is DSB required before SMC?
1b) Is DSB required after SMC?
2a) Is DSB required before returning to non-secure OS? 2b) Is DSB required after returning to non-secure OS?
It depends on what you're trying to achieve, and the design of both the secure and non-secure OS code.
A DSB is certainly not always required before nor after an SMC.
Quoted 1 line
3) Is this documented in the ARM ARM?
The semantics of DSB and SMC are documented in the ARM ARM.
How they are used is up to the programmer.
Quoted 2 lines
Bonus question: if DSB is required before SMC, why didn't ARM make SMC implicitly do a DSB?
As above, it is not always required.
Thanks,
Mark.
Quoted 7 lines · Mark Rutland
Quoted 3 lines · Mason
I have a few questions about SMC. (I'm using Cortex-A9)
Platforms that use SMC often/always execute DSB beforehand.
Please give an example. We don't do this for PSCI, for instance.
arch/arm/mach-exynos/exynos-smc.Sarch/arm/mach-highbank/smc.Sarch/arm/mach-omap2/omap-smc.S
A few that don't execute DSB before SMC:arch/arm/mach-bcm/bcm_kona_smc.carch/arm/mach-keystone/smc.S
Quoted 7 lines
Quoted 4 lines
1a) Is DSB required before SMC?
1b) Is DSB required after SMC?
2a) Is DSB required before returning to non-secure OS? 2b) Is DSB required after returning to non-secure OS?It depends on what you're trying to achieve, and the design of both the secure and non-secure OS code.
In my case, I just want to write the L2_CONTROL register.
Quoted 1 line
A DSB is certainly not always required before nor after an SMC.
That makes sense. But a colleague mentioned that the secure OS may be using different MMU mappings. In that case, it might be required to wait for all in-flight accesses to resolve?
Regards.
Quoted 8 lines · Mason
Quoted 6 lines · Mark Rutland
Quoted 3 lines · Mason
I have a few questions about SMC. (I'm using Cortex-A9)
Platforms that use SMC often/always execute DSB beforehand.
Quoted 7 lines
Quoted 1 line
Please give an example. We don't do this for PSCI, for instance.
arch/arm/mach-exynos/exynos-smc.Sarch/arm/mach-highbank/smc.Sarch/arm/mach-omap2/omap-smc.SFrom a quick look, it's not obvious to me why those DSBs are present. It
would be best to ask the original authors; it may simply be that this was never necessary and has simply been copied.
In particular, the DSB; DMB; SMC sequence in omap_smc2 makes no sense to me, given that a DSB provides a superset of the guarantees of a DMB. If the DSB is necessary I don't see that the DMB would also be necessary.
Quoted 9 lines
A few that don't execute DSB before SMC:
arch/arm/mach-bcm/bcm_kona_smc.carch/arm/mach-keystone/smc.SQuoted 5 lines
Quoted 4 lines
1a) Is DSB required before SMC?
1b) Is DSB required after SMC?
2a) Is DSB required before returning to non-secure OS? 2b) Is DSB required after returning to non-secure OS?
Quoted 4 lines
Quoted 2 lines
It depends on what you're trying to achieve, and the design of both the secure and non-secure OS code.
In my case, I just want to write the
L2_CONTROLregister.
Is that a register in the L2, or in the CPU? Which L2/CPU?
There may be a constraint that the memory system needs to be quiescent or something to that effect. Without more information I cannot say what specifically you need to do.
Quoted 5 lines
Quoted 1 line
A DSB is certainly not always required before nor after an SMC.
That makes sense. But a colleague mentioned that the secure OS may be using different MMU mappings. In that case, it might be required to wait for all in-flight accesses to resolve?
Are you referring to differing VAs or differing attributes?
For ARMv6 and above the former does not matter; the caches behaves as if they are PIPT.
The latter may require the use of barriers and/or cache maintenance if the secure and non-secure OSs are communicating through shared memory. That's somewhat independent of the SMC itself.
Thanks,
Mark.
Quoted 11 lines · Mark Rutland
Quoted 10 lines · Mason
Quoted 7 lines · Mark Rutland
Quoted 3 lines · Mason
I have a few questions about SMC. (I'm using Cortex-A9)
Platforms that use SMC often/always execute DSB beforehand.
Please give an example. We don't do this for PSCI, for instance.
Quoted 7 lines
Quoted 3 lines
arch/arm/mach-exynos/exynos-smc.Sarch/arm/mach-highbank/smc.Sarch/arm/mach-omap2/omap-smc.SFrom a quick look, it's not obvious to me why those DSBs are present. It would be best to ask the original authors; it may simply be that this was never necessary and has simply been copied.
It could be required due to secure firmware bugs or CPU errata.
Quoted 3 lines
Quoted 1 line
In my case, I just want to write the
L2_CONTROLregister.Is that a register in the L2, or in the CPU? Which L2/CPU?
Cortex-A9, he said. I believe it's the usual PL310 L2 controller.
Quoted 9 lines
There may be a constraint that the memory system needs to be quiescent or something to that effect. Without more information I cannot say what specifically you need to do.
Quoted 5 lines
Quoted 1 line
A DSB is certainly not always required before nor after an SMC.
That makes sense. But a colleague mentioned that the secure OS may be using different MMU mappings. In that case, it might be required to wait for all in-flight accesses to resolve?
It's normally a design error for a more secure domain to require things of a less secure one. If the secure monitor code requires a DMB for proper operation, it had better do it itself, or else hostile non-secure code might be able to exploit it.
Signature · 2 lines
M?ns Rullg?rd mans at mansr.com
Quoted 15 lines · Mark Rutland
Quoted 6 lines · Mason
Quoted 4 lines · Mark Rutland
Quoted 2 lines · Mason
I have a few questions about SMC. (I'm using Cortex-A9)
Quoted 7 lines
Quoted 3 lines
Quoted 1 line
Platforms that use SMC often/always execute DSB beforehand.
Please give an example. We don't do this for PSCI, for instance.
arch/arm/mach-exynos/exynos-smc.Sarch/arm/mach-highbank/smc.Sarch/arm/mach-omap2/omap-smc.S
Quoted 7 lines
From a quick look, it's not obvious to me why those DSBs are present. It would be best to ask the original authors; it may simply be that this was never necessary and has simply been copied.
In particular, the DSB; DMB; SMC sequence in
omap_smc2makes no sense to me, given that a DSB provides a superset of the guarantees of a DMB. If the DSB is necessary I don't see that the DMB would also be necessary.
I agree the DSB; DMB; SMC sequence looks fishy.
It also shows up there:
http://genode.org/documentation/articles/trustzone
Quoted 9 lines
Quoted 9 lines
A few that don't execute DSB before SMC:
arch/arm/mach-bcm/bcm_kona_smc.carch/arm/mach-keystone/smc.SQuoted 5 lines
Quoted 4 lines
1a) Is DSB required before SMC?
1b) Is DSB required after SMC?
2a) Is DSB required before returning to non-secure OS? 2b) Is DSB required after returning to non-secure OS?
Quoted 6 lines
Quoted 4 lines
Quoted 2 lines
It depends on what you're trying to achieve, and the design of both the secure and non-secure OS code.
In my case, I just want to write the
L2_CONTROLregister.Is that a register in the L2, or in the CPU? Which L2/CPU?
Sorry for being so sloppy.
L2C-310 reg1_control (offset 0x100) connected to Cortex-A9 MPCore.
Quoted 10 lines
There may be a constraint that the memory system needs to be quiescent or something to that effect. Without more information I cannot say what specifically you need to do.
Quoted 5 lines
Quoted 1 line
A DSB is certainly not always required before nor after an SMC.
That makes sense. But a colleague mentioned that the secure OS may be using different MMU mappings. In that case, it might be required to wait for all in-flight accesses to resolve?
Quoted 8 lines
Are you referring to differing VAs or differing attributes?
For ARMv6 and above the former does not matter; the caches behaves as if they are PIPT.
The latter may require the use of barriers and/or cache maintenance if the secure and non-secure OSs are communicating through shared memory. That's somewhat independent of the SMC itself.
AFAICT, the two OSes only communicate through registers.
I think DSB is unnecessary. But I'm not confident enough to remove it. (It might not matter, since that function is called very rarely.)
Regards.