nios2: add 10m50 devboard support

PATCH New Thomas Chou 2 participants 8 messages Oct 26, 2015 – Nov 9, 2015

Subsystems (2)

Memory technology devices (MTD) NIOS2 architecture

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Thomas Chou

author

2015-10-26 00:15 UTC #0 lore raw

PATCH 1/1 nios2: add 10m50 devboard support

Add 10m50 devboard support. It is based on the Golden Hardware Reference Design (GHRD), available at,

http://rocketboards.org/foswiki/view/Documentation/
AlteraMAX1010M50RevCDevelopmentKitLinuxSetup

Though we supported only one nios2-generic board in the past. Now, with the removal of the nios2-generic board dir, adding new nios2 boards to u-boot is easier than before. It should be helpful to add those boards supported in Linux mainline. There are only two such nios2 boards, the 3c120 devboard and 10m50 devboard. The nios2-generic is actually 3c120, and should restore the name. The 10m50 is this one.

Signed-off-by Thomas Chou <[email protected]>

---
 arch/nios2/dts/10m50_devboard.dts | 259 ++++++++++++++++++++++++++++++++++++++
 configs/10m50_defconfig           |  23 ++++
 include/configs/10m50_devboard.h  |  98 +++++++++++++++
 3 files changed, 380 insertions(+)
 create mode 100644 arch/nios2/dts/10m50_devboard.dts
 create mode 100644 configs/10m50_defconfig
 create mode 100644 include/configs/10m50_devboard.h

arch/nios2/dts/10m50_devboard.dts new file +259 -0

new file mode 100644
index 0000000..8f22318
@@ -0,0 +1,259 @@
+/*
+ *  Copyright (C) 2015 Altera Corporation
+ *
+ * This file is generated by sopc2dts.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+	model = "Altera NiosII Max10";
+	compatible = "altr,niosii-max10";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu: cpu at 0 {
+			device_type = "cpu";
+			compatible = "altr,nios2-1.1";
+			reg = <0x00000000>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			altr,exception-addr = <0xc8000120>;
+			altr,fast-tlb-miss-addr = <0xc0000100>;
+			altr,has-div = <1>;
+			altr,has-initda = <1>;
+			altr,has-mmu = <1>;
+			altr,has-mul = <1>;
+			altr,implementation = "fast";
+			altr,pid-num-bits = <8>;
+			altr,reset-addr = <0xd4000000>;
+			altr,tlb-num-entries = <256>;
+			altr,tlb-num-ways = <16>;
+			altr,tlb-ptr-sz = <8>;
+			clock-frequency = <75000000>;
+			dcache-line-size = <32>;
+			dcache-size = <32768>;
+			icache-line-size = <32>;
+			icache-size = <32768>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x08000000 0x08000000>,
+			<0x00000000 0x00000400>;
+	};
+
+	sopc0: sopc at 0 {
+		device_type = "soc";
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "altr,avalon", "simple-bus";
+		bus-frequency = <75000000>;
+
+		jtag_uart: serial at 18001530 {
+			compatible = "altr,juart-1.0";
+			reg = <0x18001530 0x00000008>;
+			interrupt-parent = <&cpu>;
+			interrupts = <7>;
+		};
+
+		a_16550_uart_0: serial at 18001600 {
+			compatible = "altr,16550-FIFO32", "ns16550a";
+			reg = <0x18001600 0x00000200>;
+			interrupt-parent = <&cpu>;
+			interrupts = <1>;
+			auto-flow-control = <1>;
+			clock-frequency = <50000000>;
+			fifo-size = <32>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+		};
+
+		ext_flash: quadspi at 0x180014a0 {
+			compatible = "altr,quadspi-1.0";
+			reg = <0x180014a0 0x00000020>,
+				<0x14000000 0x04000000>;
+			reg-names = "avl_csr", "avl_mem";
+			interrupt-parent = <&cpu>;
+			interrupts = <4>;
+		};
+
+		sysid: sysid at 18001528 {
+			compatible = "altr,sysid-1.0";
+			reg = <0x18001528 0x00000008>;
+		};
+
+		rgmii_0_eth_tse_0: ethernet at 400 {
+			compatible = "altr,tse-msgdma-1.0", "altr,tse-1.0";
+			reg = <0x00000400 0x00000400>,
+				<0x00000820 0x00000020>,
+				<0x00000800 0x00000020>,
+				<0x000008c0 0x00000008>,
+				<0x00000840 0x00000020>,
+				<0x00000860 0x00000020>;
+			reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc";
+			interrupt-parent = <&cpu>;
+			interrupts = <2 3>;
+			interrupt-names = "rx_irq", "tx_irq";
+			rx-fifo-depth = <8192>;
+			tx-fifo-depth = <8192>;
+			address-bits = <48>;
+			max-frame-size = <1518>;
+			local-mac-address = [00 00 00 00 00 00];
+			altr,has-supplementary-unicast;
+			altr,enable-sup-addr = <1>;
+			altr,has-hash-multicast-filter;
+			altr,enable-hash = <1>;
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy0>;
+			rgmii_0_eth_tse_0_mdio: mdio {
+				compatible = "altr,tse-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				phy0: ethernet-phy at 0 {
+					reg = <0>;
+					device_type = "ethernet-phy";
+				};
+			};
+		};
+
+		enet_pll: clock at 0 {
+			compatible = "altr,pll-1.0";
+			#clock-cells = <1>;
+
+			enet_pll_c0: enet_pll_c0 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <125000000>;
+				clock-output-names = "enet_pll-c0";
+			};
+
+			enet_pll_c1: enet_pll_c1 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <25000000>;
+				clock-output-names = "enet_pll-c1";
+			};
+
+			enet_pll_c2: enet_pll_c2 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <2500000>;
+				clock-output-names = "enet_pll-c2";
+			};
+		};
+
+		sys_pll: clock at 1 {
+			compatible = "altr,pll-1.0";
+			#clock-cells = <1>;
+
+			sys_pll_c0: sys_pll_c0 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <100000000>;
+				clock-output-names = "sys_pll-c0";
+			};
+
+			sys_pll_c1: sys_pll_c1 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <50000000>;
+				clock-output-names = "sys_pll-c1";
+			};
+
+			sys_pll_c2: sys_pll_c2 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <75000000>;
+				clock-output-names = "sys_pll-c2";
+			};
+		};
+
+		sys_clk_timer: timer at 18001440 {
+			compatible = "altr,timer-1.0";
+			reg = <0x18001440 0x00000020>;
+			interrupt-parent = <&cpu>;
+			interrupts = <0>;
+			clock-frequency = <75000000>;
+		};
+
+		led_pio: gpio at 180014d0 {
+			compatible = "altr,pio-1.0";
+			reg = <0x180014d0 0x00000010>;
+			altr,gpio-bank-width = <4>;
+			resetvalue = <15>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-bank-name = "led";
+		};
+
+		uart_0: serial at 0x18001420 {
+			compatible = "altr,uart-1.0";
+			reg = <0x18001420 0x00000020>;
+			interrupt-parent = <&cpu>;
+			interrupts = <1>;
+			clock-frequency = <75000000>;
+			current-speed = <115200>;
+		};
+
+		button_pio: gpio at 180014c0 {
+			compatible = "altr,pio-1.0";
+			reg = <0x180014c0 0x00000010>;
+			interrupt-parent = <&cpu>;
+			interrupts = <6>;
+			altr,gpio-bank-width = <3>;
+			altr,interrupt-type = <2>;
+			edge_type = <1>;
+			level_trigger = <0>;
+			resetvalue = <0>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-bank-name = "button";
+		};
+
+		sys_clk_timer_1: timer at 880 {
+			compatible = "altr,timer-1.0";
+			reg = <0x00000880 0x00000020>;
+			interrupt-parent = <&cpu>;
+			interrupts = <5>;
+			clock-frequency = <75000000>;
+		};
+
+		fpga_leds: leds {
+			compatible = "gpio-leds";
+
+			led_fpga0: fpga0 {
+				label = "fpga_led0";
+				gpios = <&led_pio 0 1>;
+			};
+
+			led_fpga1: fpga1 {
+				label = "fpga_led1";
+				gpios = <&led_pio 1 1>;
+			};
+
+			led_fpga2: fpga2 {
+				label = "fpga_led2";
+				gpios = <&led_pio 2 1>;
+			};
+
+			led_fpga3: fpga3 {
+				label = "fpga_led3";
+				gpios = <&led_pio 3 1>;
+			};
+		};
+	};
+
+	chosen {
+		bootargs = "debug console=ttyS0,115200";
+		stdout-path = &uart_0;
+	};
+};

configs/10m50_defconfig new file +23 -0

new file mode 100644
index 0000000..fa5ffd7
@@ -0,0 +1,23 @@
+CONFIG_NIOS2=y
+CONFIG_SYS_CONFIG_NAME="10m50_devboard"
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ALTERA_PIO=y
+CONFIG_MISC=y
+CONFIG_ALTERA_SYSID=y
+CONFIG_ALTERA_UART=y
+CONFIG_TIMER=y
+CONFIG_ALTERA_TIMER=y

include/configs/10m50_devboard.h new file +98 -0

98 lines not on this page · raw message

Signature · 1 line

2.1.4

Marek Vasut

2015-10-28 23:45 UTC #1 lore raw

PATCH 1/1 nios2: add 10m50 devboard support

Quoted 15 lines · Thomas Chou

Add 10m50 devboard support. It is based on the Golden Hardware Reference Design (GHRD), available at,
http://rocketboards.org/foswiki/view/Documentation/
AlteraMAX1010M50RevCDevelopmentKitLinuxSetup
Though we supported only one nios2-generic board in the past. Now, with the removal of the nios2-generic board dir, adding new nios2 boards to u-boot is easier than before. It should be helpful to add those boards supported in Linux mainline. There are only two such nios2 boards, the 3c120 devboard and 10m50 devboard. The nios2-generic is actually 3c120, and should restore the name. The 10m50 is this one.
Signed-off-by Thomas Chou <[email protected]>

Quoted 9 lines

---
 arch/nios2/dts/10m50_devboard.dts | 259
++++++++++++++++++++++++++++++++++++++ configs/10m50_defconfig           |
 23 ++++
 include/configs/10m50_devboard.h  |  98 +++++++++++++++
 3 files changed, 380 insertions(+)
 create mode 100644 arch/nios2/dts/10m50_devboard.dts
 create mode 100644 configs/10m50_defconfig
 create mode 100644 include/configs/10m50_devboard.h

Indeed, this patch is an excellent example of adding a new nios2 board.

Just a few nitpicks below.

[...]

Quoted 9 lines

configs/10m50_defconfig new file +3 -0

new file mode 100644
index 0000000..fa5ffd7
@@ -0,0 +1,23 @@
+CONFIG_NIOS2=y
+CONFIG_SYS_CONFIG_NAME="10m50_devboard"
+CONFIG_DM_SERIAL=y

configs/10m50_defconfig line 13

Quoted 10 lines

configs/10m50_defconfig new file +10 -0

+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set

Please keep setexpr, it's really useful.

Quoted 41 lines

configs/10m50_defconfig new file +10 -0

+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ALTERA_PIO=y
+CONFIG_MISC=y
+CONFIG_ALTERA_SYSID=y
+CONFIG_ALTERA_UART=y
+CONFIG_TIMER=y
+CONFIG_ALTERA_TIMER=y

(quoted diff) +0 -0

b/include/configs/10m50_devboard.h new file mode 100644 index 0000000..4140f2d

include/configs/10m50_devboard.h new file +25 -0

@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <[email protected]>
+ * (C) Copyright 2010, Thomas Chou <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * SERIAL
+ */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* Suppress console info */
+
+/*
+ * CFI Flash

include/configs/10m50_devboard.h line 35

Quoted 10 lines

include/configs/10m50_devboard.h new file +10 -0

+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * MII/PHY
+ */
+#define CONFIG_CMD_MII			1
+#define CONFIG_PHY_GIGE			1
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
+#define CONFIG_PHY_MARVELL		1

Are you sure all these macros must have a value (1) ? I doubt it.

[...]

Thomas Chou

author

2015-10-29 05:34 UTC #2 lore raw

PATCH 1/1 nios2: add 10m50 devboard support

Hi Marek,

Quoted 3 lines · Marek Vasut

Quoted 1 line
+# CONFIG_CMD_SETEXPR is not set
Please keep setexpr, it's really useful.

OK, I will keep it.

Quoted 9 lines

include/configs/10m50_devboard.h line 35
Quoted 7 lines
include/configs/10m50_devboard.h new file +7 -0
+/*
+ * MII/PHY
+ */
+#define CONFIG_CMD_MII			1
+#define CONFIG_PHY_GIGE			1
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
+#define CONFIG_PHY_MARVELL		1
Are you sure all these macros must have a value (1) ? I doubt it.

Oops, these '1' should be removed.

I will resend this patch after I finish the altera quadspi and altera tse msgdma update. Thank you.

Best regards,
Thomas

Marek Vasut

2015-10-29 13:16 UTC #3 lore raw

PATCH 1/1 nios2: add 10m50 devboard support

Quoted 19 lines · Thomas Chou

Hi Marek,
Quoted 3 lines · Marek Vasut
Quoted 1 line
+# CONFIG_CMD_SETEXPR is not set
Please keep setexpr, it's really useful.
OK, I will keep it.
Quoted 9 lines
include/configs/10m50_devboard.h line 35
Quoted 7 lines
include/configs/10m50_devboard.h new file +7 -0
+/*
+ * MII/PHY
+ */
+#define CONFIG_CMD_MII			1
+#define CONFIG_PHY_GIGE			1
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
+#define CONFIG_PHY_MARVELL		1
Are you sure all these macros must have a value (1) ? I doubt it.

Quoted 4 lines

Oops, these '1' should be removed.
I will resend this patch after I finish the altera quadspi and altera tse msgdma update. Thank you.

Thanks!

Best regards,
Marek Vasut

Thomas Chou

author

2015-11-09 06:52 UTC #4 lore raw

PATCH v2 1/1 mtd: add altera quadspi driver

In reply to Thomas Chou

Add Altera Generic Quad SPI Controller support. The controller converts SPI NOR flash to parallel flash interface. So it is not like other SPI flash, but rather like CFI flash.

Signed-off-by Thomas Chou <[email protected]>

---
v2
change memory alllocation macros.
add altera_qspi support.

 doc/device-tree-bindings/mtd/altera_qspi.txt |  35 ++++
 drivers/mtd/Kconfig                          |   9 +
 drivers/mtd/Makefile                         |   1 +
 drivers/mtd/altera_qspi.c                    | 273 +++++++++++++++++++++++++++
 4 files changed, 318 insertions(+)
 create mode 100644 doc/device-tree-bindings/mtd/altera_qspi.txt
 create mode 100644 drivers/mtd/altera_qspi.c

doc/device-tree-bindings/mtd/altera_qspi.txt new file +35 -0

new file mode 100644
index 0000000..3361ac9
@@ -0,0 +1,35 @@
+Altera QUADSPI driver
+
+Required properties:
+- compatible: Should be "altr,quadspi-1.0"
+- reg: Address and length of the register set  for the device. It contains
+  the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+  "avl_csr": Should contain the register configuration base address
+  "avl_mem": Should contain the data base address
+- #address-cells: Must be <1>.
+- #size-cells: Must be <0>.
+- flash device tree subnode, there must be a node with the following fields:
+	- compatible: Should contain the flash name:
+	  1. EPCS:   epcs16, epcs64, epcs128
+	  2. EPCQ:   epcq16, epcq32, epcq64, epcq128, epcq256, epcq512, epcq1024
+	  3. EPCQ-L: epcql256, epcql512, epcql1024
+	- #address-cells: please refer to /mtd/partition.txt
+	- #size-cells: please refer to /mtd/partition.txt
+	For partitions inside each flash, please refer to /mtd/partition.txt
+
+Example:
+
+	quadspi_controller_0: quadspi at 0x180014a0 {
+		compatible = "altr,quadspi-1.0";
+		reg = <0x180014a0 0x00000020>,
+		      <0x14000000 0x04000000>;
+		reg-names = "avl_csr", "avl_mem";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		flash0: epcq512 at 0 {
+			compatible = "altr,epcq512";
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+	};

drivers/mtd/Kconfig +9 -0

index 57e4b86..c58841e 100644
@@ -19,6 +19,15 @@ config CFI_FLASH
 	  option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
 	  for more information on CFI.
 
+config ALTERA_QSPI
+	bool "Altera Generic Quad SPI Controller"
+	depends on MTD
+	help
+	  This enables access to Altera EPCQ/EPCS flash chips using the
+	  Altera Generic Quad SPI Controller. The controller converts SPI
+	  NOR flash to parallel flash interface. Please find details on the
+	  "Embedded Peripherals IP User Guide" of Altera.
+
 endmenu
 
 source "drivers/mtd/nand/Kconfig"

drivers/mtd/Makefile +1 -0

index c23c0c1..7f018a4 100644
@@ -11,6 +11,7 @@ endif
 obj-$(CONFIG_MTD) += mtd-uclass.o
 obj-$(CONFIG_MTD_PARTITIONS) += mtdpart.o
 obj-$(CONFIG_MTD_CONCAT) += mtdconcat.o
+obj-$(CONFIG_ALTERA_QSPI) += altera_qspi.o
 obj-$(CONFIG_HAS_DATAFLASH) += at45.o
 obj-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o
 obj-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o

drivers/mtd/altera_qspi.c new file +273 -0

273 lines not on this page · raw message

Signature · 1 line

2.5.0

Thomas Chou

author

2015-11-09 06:59 UTC #5 lore raw

PATCH v2 1/1 mtd: add altera quadspi driver

Quoted 3 lines · Thomas Chou

v2
change memory alllocation macros.
add altera_qspi support.

Sorry, wrong patch. Please ignore this one.

- Thomas

Thomas Chou

author

2015-11-09 06:59 UTC #6 lore raw

PATCH v2 1/1 nios2: add 10m50 devboard support

In reply to Thomas Chou

Add 10m50 devboard support. It is based on the Golden Hardware Reference Design (GHRD), available at,

http://rocketboards.org/foswiki/view/Documentation/
AlteraMAX1010M50RevCDevelopmentKitLinuxSetup

Signed-off-by Thomas Chou <[email protected]>

---
v2
change memory alllocation macros.
add altera_qspi support.

 arch/nios2/dts/10m50_devboard.dts | 267 ++++++++++++++++++++++++++++++++++++++
 configs/10m50_defconfig           |  26 ++++
 include/configs/10m50_devboard.h  | 103 +++++++++++++++
 3 files changed, 396 insertions(+)
 create mode 100644 arch/nios2/dts/10m50_devboard.dts
 create mode 100644 configs/10m50_defconfig
 create mode 100644 include/configs/10m50_devboard.h

arch/nios2/dts/10m50_devboard.dts new file +267 -0

new file mode 100644
index 0000000..e89dbb2
@@ -0,0 +1,267 @@
+/*
+ *  Copyright (C) 2015 Altera Corporation
+ *
+ * This file is generated by sopc2dts.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+	model = "Altera NiosII Max10";
+	compatible = "altr,niosii-max10";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu: cpu at 0 {
+			device_type = "cpu";
+			compatible = "altr,nios2-1.1";
+			reg = <0x00000000>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			altr,exception-addr = <0xc8000120>;
+			altr,fast-tlb-miss-addr = <0xc0000100>;
+			altr,has-div = <1>;
+			altr,has-initda = <1>;
+			altr,has-mmu = <1>;
+			altr,has-mul = <1>;
+			altr,implementation = "fast";
+			altr,pid-num-bits = <8>;
+			altr,reset-addr = <0xd4000000>;
+			altr,tlb-num-entries = <256>;
+			altr,tlb-num-ways = <16>;
+			altr,tlb-ptr-sz = <8>;
+			clock-frequency = <75000000>;
+			dcache-line-size = <32>;
+			dcache-size = <32768>;
+			icache-line-size = <32>;
+			icache-size = <32768>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x08000000 0x08000000>,
+			<0x00000000 0x00000400>;
+	};
+
+	sopc0: sopc at 0 {
+		device_type = "soc";
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "altr,avalon", "simple-bus";
+		bus-frequency = <75000000>;
+
+		jtag_uart: serial at 18001530 {
+			compatible = "altr,juart-1.0";
+			reg = <0x18001530 0x00000008>;
+			interrupt-parent = <&cpu>;
+			interrupts = <7>;
+		};
+
+		a_16550_uart_0: serial at 18001600 {
+			compatible = "altr,16550-FIFO32", "ns16550a";
+			reg = <0x18001600 0x00000200>;
+			interrupt-parent = <&cpu>;
+			interrupts = <1>;
+			auto-flow-control = <1>;
+			clock-frequency = <50000000>;
+			fifo-size = <32>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+		};
+
+		ext_flash: quadspi at 0x180014a0 {
+			compatible = "altr,quadspi-1.0";
+			reg = <0x180014a0 0x00000020>,
+				<0x14000000 0x04000000>;
+			reg-names = "avl_csr", "avl_mem";
+			interrupt-parent = <&cpu>;
+			interrupts = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			flash0: nor0 at 0 {
+				compatible = "micron,n25q512a";
+				#address-cells = <1>;
+				#size-cells = <1>;
+			};
+		};
+
+		sysid: sysid at 18001528 {
+			compatible = "altr,sysid-1.0";
+			reg = <0x18001528 0x00000008>;
+		};
+
+		rgmii_0_eth_tse_0: ethernet at 400 {
+			compatible = "altr,tse-msgdma-1.0", "altr,tse-1.0";
+			reg = <0x00000400 0x00000400>,
+				<0x00000820 0x00000020>,
+				<0x00000800 0x00000020>,
+				<0x000008c0 0x00000008>,
+				<0x00000840 0x00000020>,
+				<0x00000860 0x00000020>;
+			reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp",
+				  "tx_csr", "tx_desc";
+			interrupt-parent = <&cpu>;
+			interrupts = <2 3>;
+			interrupt-names = "rx_irq", "tx_irq";
+			rx-fifo-depth = <8192>;
+			tx-fifo-depth = <8192>;
+			address-bits = <48>;
+			max-frame-size = <1518>;
+			local-mac-address = [00 00 00 00 00 00];
+			altr,has-supplementary-unicast;
+			altr,enable-sup-addr = <1>;
+			altr,has-hash-multicast-filter;
+			altr,enable-hash = <1>;
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy0>;
+			rgmii_0_eth_tse_0_mdio: mdio {
+				compatible = "altr,tse-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				phy0: ethernet-phy at 0 {
+					reg = <0>;
+					device_type = "ethernet-phy";
+				};
+			};
+		};
+
+		enet_pll: clock at 0 {
+			compatible = "altr,pll-1.0";
+			#clock-cells = <1>;
+
+			enet_pll_c0: enet_pll_c0 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <125000000>;
+				clock-output-names = "enet_pll-c0";
+			};
+
+			enet_pll_c1: enet_pll_c1 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <25000000>;
+				clock-output-names = "enet_pll-c1";
+			};
+
+			enet_pll_c2: enet_pll_c2 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <2500000>;
+				clock-output-names = "enet_pll-c2";
+			};
+		};
+
+		sys_pll: clock at 1 {
+			compatible = "altr,pll-1.0";
+			#clock-cells = <1>;
+
+			sys_pll_c0: sys_pll_c0 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <100000000>;
+				clock-output-names = "sys_pll-c0";
+			};
+
+			sys_pll_c1: sys_pll_c1 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <50000000>;
+				clock-output-names = "sys_pll-c1";
+			};
+
+			sys_pll_c2: sys_pll_c2 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <75000000>;
+				clock-output-names = "sys_pll-c2";
+			};
+		};
+
+		sys_clk_timer: timer at 18001440 {
+			compatible = "altr,timer-1.0";
+			reg = <0x18001440 0x00000020>;
+			interrupt-parent = <&cpu>;
+			interrupts = <0>;
+			clock-frequency = <75000000>;
+		};
+
+		led_pio: gpio at 180014d0 {
+			compatible = "altr,pio-1.0";
+			reg = <0x180014d0 0x00000010>;
+			altr,gpio-bank-width = <4>;
+			resetvalue = <15>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-bank-name = "led";
+		};
+
+		uart_0: serial at 0x18001420 {
+			compatible = "altr,uart-1.0";
+			reg = <0x18001420 0x00000020>;
+			interrupt-parent = <&cpu>;
+			interrupts = <1>;
+			clock-frequency = <75000000>;
+			current-speed = <115200>;
+		};
+
+		button_pio: gpio at 180014c0 {
+			compatible = "altr,pio-1.0";
+			reg = <0x180014c0 0x00000010>;
+			interrupt-parent = <&cpu>;
+			interrupts = <6>;
+			altr,gpio-bank-width = <3>;
+			altr,interrupt-type = <2>;
+			edge_type = <1>;
+			level_trigger = <0>;
+			resetvalue = <0>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-bank-name = "button";
+		};
+
+		sys_clk_timer_1: timer at 880 {
+			compatible = "altr,timer-1.0";
+			reg = <0x00000880 0x00000020>;
+			interrupt-parent = <&cpu>;
+			interrupts = <5>;
+			clock-frequency = <75000000>;
+		};
+
+		fpga_leds: leds {
+			compatible = "gpio-leds";
+
+			led_fpga0: fpga0 {
+				label = "fpga_led0";
+				gpios = <&led_pio 0 1>;
+			};
+
+			led_fpga1: fpga1 {
+				label = "fpga_led1";
+				gpios = <&led_pio 1 1>;
+			};
+
+			led_fpga2: fpga2 {
+				label = "fpga_led2";
+				gpios = <&led_pio 2 1>;
+			};
+
+			led_fpga3: fpga3 {
+				label = "fpga_led3";
+				gpios = <&led_pio 3 1>;
+			};
+		};
+	};
+
+	chosen {
+		bootargs = "debug console=ttyS0,115200";
+		stdout-path = &uart_0;
+	};
+};

configs/10m50_defconfig new file +26 -0

new file mode 100644
index 0000000..af2cef7
@@ -0,0 +1,26 @@
+CONFIG_NIOS2=y
+CONFIG_SYS_CONFIG_NAME="10m50_devboard"
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ALTERA_PIO=y
+CONFIG_MISC=y
+CONFIG_ALTERA_SYSID=y
+CONFIG_MTD=y
+CONFIG_ALTERA_QSPI=y
+CONFIG_DM_ETH=y
+CONFIG_ALTERA_TSE=y
+CONFIG_ALTERA_UART=y
+CONFIG_TIMER=y
+CONFIG_ALTERA_TIMER=y

include/configs/10m50_devboard.h new file +103 -0

103 lines not on this page · raw message

Signature · 1 line

2.5.0

Marek Vasut

2015-11-09 14:27 UTC #7 lore raw

PATCH v2 1/1 nios2: add 10m50 devboard support

Quoted 14 lines · Thomas Chou

Add 10m50 devboard support. It is based on the Golden Hardware Reference Design (GHRD), available at,
http://rocketboards.org/foswiki/view/Documentation/
AlteraMAX1010M50RevCDevelopmentKitLinuxSetup
Though we supported only one nios2-generic board in the past. Now, with the removal of the nios2-generic board dir, adding new nios2 boards to u-boot is easier than before. It should be helpful to add those boards supported in Linux mainline. There are only two such nios2 boards, the 3c120 devboard and 10m50 devboard. The nios2-generic is actually 3c120, and should restore the name. The 10m50 is this one.

Quoted 1 line

Signed-off-by Thomas Chou <[email protected]>

Reviewed-by Marek Vasut <[email protected]>

Best regards,
Marek Vasut