arm64: renesas: Add Renesas R8A7795 SoC support

Hi,

this pathcset adds basic support for the Renesas R-Car H3 (R8A7795) SoC and its Saovator-X board.

This series has undergone a number of rounds of development and review on the linux-sh mailing list. This is the first posting to a wider audience from which we are now seeking review.

It is anticpated that the CPG bindings used this patchset will be changed before they hit mainline and thus this patchset will need to be updated accordinly. Reviwers are advised to skip over that portion of this patchset unless they have a particlar interest in that discussion.

Based on v4.3-rc1.

Further run-time dependencies are included in the topic/gen3-latest branch of Geert Uytterhoeven's renesas-drivers tree. which currently includes these patches less the MAINTAINERS update.

To aid review (and Geert's branch preparation) this series is available in the topic/arm64-rcar-gen3-v11 branch of the my renesas tree.

Gaku Inami (1):
arm64: renesas: r8a7795: Add Renesas R8A7795 SoC support

Geert Uytterhoeven (3):
arm64: renesas: r8a7795 dtsi: Add all common divider clocks
arm64: renesas: r8a7795 dtsi: Add dummy dma-controller nodes
arm64: renesas: r8a7795 dtsi: Add all SCIF nodes

Kuninori Morimoto (3):
arm64: renesas: r8a7795: enable PFC
arm64: renesas: add Salvator-X board support on DTS
arm64: defconfig: renesas: Enable Renesas r8a7795 SoC

Simon Horman (1):
MAINTAINERS: Add entry Renesas arm64 architecture

 Documentation/devicetree/bindings/arm/shmobile.txt |   4 +
 MAINTAINERS                                        |  10 +
 arch/arm64/Kconfig.platforms                       |  17 +
 arch/arm64/boot/dts/Makefile                       |   1 +
 arch/arm64/boot/dts/renesas/Makefile               |   4 +
 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts |  62 ++++
 arch/arm64/boot/dts/renesas/r8a7795.dtsi           | 384 +++++++++++++++++++++
 arch/arm64/configs/defconfig                       |   5 +
 include/dt-bindings/clock/r8a7795-clock.h          |  44 +++
 9 files changed, 531 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/Makefile
 create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r8a7795.dtsi
 create mode 100644 include/dt-bindings/clock/r8a7795-clock.h

2.1.4

From: Gaku Inami <[email protected]>

Initial version of Renesas R-Car H3 support (V10)

---
TODO:
- Split this patch based on ARM-SoC maintainer preference

Changes since v10:
- None

Changes since v9: (Magnus Damm <[email protected]>)
- Added clock-output-names for the CPG

Changes since v8: (Magnus Damm <[email protected]>)
- Renamed xtal node name to drop _clk - thanks Geert!
- Kconfig s/platform/platforms/g - thanks Laurent!
- Added select PINCTRL - thanks Geert
- Removed unused Makefile subdir line - thanks Laurent!

Changes since v7: (Magnus Damm <[email protected]>)
- Folded together the following patches from v7:
[PATCH 6/25] arm64: renesas: Add new Renesas R-Car Gen3 SoC Kconfig [PATCH 7/25] arm64: renesas: r8a7795: Add Renesas R8A7795 SoC support [PATCH 8/25] arm64: renesas: r8a7795: Add initial SoC support
- Updated Kconfig bits
Changed to CONFIG_ARCH_R8A7795 and CONFIG_RENESAS CONFIG_ARCH_SHMOBILE is still set to be able to build various drivers CONFIG_ARCH_SHMOBILE_MULTI is gone
select PM_GENERIC_DOMAINS if PM
- Moved "s3d4_clk" to clock patch from geert
- Replaced CPG clock-output-names with clock-indices
- set #power-domain-cells to 0

---
 Documentation/devicetree/bindings/arm/shmobile.txt |  2 +
 arch/arm64/Kconfig.platforms                       | 17 +++++
 arch/arm64/boot/dts/Makefile                       |  1 +
 arch/arm64/boot/dts/renesas/Makefile               |  2 +
 arch/arm64/boot/dts/renesas/r8a7795.dtsi           | 89 ++++++++++++++++++++++
 include/dt-bindings/clock/r8a7795-clock.h          | 38 +++++++++
 6 files changed, 149 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/Makefile
 create mode 100644 arch/arm64/boot/dts/renesas/r8a7795.dtsi
 create mode 100644 include/dt-bindings/clock/r8a7795-clock.h

index c4f19b2e7dd9..8d696a0d62b3 100644
@@ -27,6 +27,8 @@ SoCs:
     compatible = "renesas,r8a7793"
   - R-Car E2 (R8A77940)
     compatible = "renesas,r8a7794"
+  - R-Car H3 (R8A77950)
+    compatible = "renesas,r8a7795"
 
 
 Boards:

index 23800a19a7bc..04bf6de3b01a 100644
@@ -66,6 +66,23 @@ config ARCH_SEATTLE
 	help
 	  This enables support for AMD Seattle SOC Family
 
+config ARCH_SHMOBILE
+	bool
+
+config ARCH_RENESAS
+	bool "Renesas SoC Platforms"
+	select ARCH_SHMOBILE
+	select PINCTRL
+	select PM_GENERIC_DOMAINS if PM
+	help
+	  This enables support for the ARMv8 based Renesas SoCs.
+
+config ARCH_R8A7795
+	bool "Renesas R-Car H3 SoC Platform"
+	depends on ARCH_RENESAS
+	help
+	  This enables support for the Renesas R-Car H3 SoC.
+
 config ARCH_TEGRA
 	bool "NVIDIA Tegra SoC Family"
 	select ARCH_HAS_RESET_CONTROLLER

index d9f88330e7b0..54e401119639 100644
@@ -9,6 +9,7 @@ dts-dirs += hisilicon
 dts-dirs += marvell
 dts-dirs += mediatek
 dts-dirs += qcom
+dts-dirs += renesas
 dts-dirs += rockchip
 dts-dirs += sprd
 dts-dirs += xilinx

new file mode 100644
index 000000000000..fec69f46d65b
@@ -0,0 +1,2 @@
+always		:= $(dtb-y)
+clean-files	:= *.dtb

new file mode 100644
index 000000000000..334fa13d1bb4
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A7795_H__
+#define __DT_BINDINGS_CLOCK_R8A7795_H__
+
+/* CPG */
+#define R8A7795_CLK_MAIN		0
+#define R8A7795_CLK_PLL0		1
+#define R8A7795_CLK_PLL1		2
+#define R8A7795_CLK_PLL2		3
+#define R8A7795_CLK_PLL3		4
+#define R8A7795_CLK_PLL4		5
+
+/* MSTP0 */
+
+/* MSTP1 */
+
+/* MSTP2 */
+
+/* MSTP3 */
+
+/* MSTP5 */
+
+/* MSTP7 */
+
+/* MSTP8 */
+
+/* MSTP9 */
+
+/* MSTP10 */
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7795_H__ */

2.1.4

Hi,

Hi Mark,

These seem to be defined in the "arm,gic-v3" DT bindings only, while this is an "arm,gic-400" (GICD_IIDR 0x0200043b)?

I did notice hi6220.dtsi does have GICH and GICV, while it also claims to be an "arm,gic-400"...

No idea.

The "clock" node is planned to be removed.

Indeed.

Note that the final CPG node will be the one from "[PATCH/RFC v4 0/5] clk:
shmobile: Add new Renesas CPG/MSSR DT bindings", cfr. the example in
https://patchwork.ozlabs.org/patch/531300/.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

See the "GIC virtualization extensions (VGIC)" section in Documentation/devicetree/bindings/arm/gic.txt

That's fine, that's valid for any GICv2 with virtualization extensions.

For reference, the kernel should print it out just after booting all CPUs. e.g. on Juno:

SMP: Total of 6 processors activated.
CPU: All CPU(s) started at EL2

Thanks,
Mark.

Hi Mark,

All I can find in the docs are the two register blocks we have in the dtsi.

Thanks!

CPU: All CPU(s) started at EL1

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Hi Mark,

DDI0471B_gic400_r0p1_trm.pdf says:

    Address range GIC-400 functional block
    A. 0x0000 - 0x0FFF Reserved
    B. 0x1000 - 0x1FFF Distributor
    C. 0x2000 - 0x3FFF CPU interfaces
    D. 0x4000 - 0x4FFF Virtual interface control block, for the processor that
                       is performing the access
    E. 0x5000 - 0x5FFF Virtual interface control block, for the processor
                       selected by address bits [11:9]
    F. 0x6000 - 0x7FFF Virtual CPU interfaces

The DT binding document says:
1. The first region is the GIC distributor register base and size.
2. The 2nd region is the GIC cpu interface register base and size.
3. The first additional region is the GIC virtual interface control register base and size.
4. The 2nd additional region is the GIC virtual cpu interface register base and size.

Matching with the example:

        interrupt-controller at 2c001000 {
                compatible = "arm,cortex-a15-gic";
                #interrupt-cells = <3>;
                interrupt-controller;
                reg = <0x2c001000 0x1000>,
                      <0x2c002000 0x1000>,
                      <0x2c004000 0x2000>,
                      <0x2c006000 0x2000>;
                interrupts = <1 9 0xf04>;
        };

This means:
- reg entry 1. covers address range B,
- reg entry 2. covers address range C,
- reg entry 3. covers address ranges D _and_ E,
- reg entry 4. covers address range F.

On R-Car Gen3, the base addresses are:

    Distributor             : 0xF101_0000
    CPU interfaces          : 0xF102_0000
    Virtual interfaces      : 0xF104_0000
    Virtual interfaces      : 0xF105_0000
    Virtual CPU interfaces  : 0xF106_0000

Note the additional multiplication factor of 16 in the offsets relative to the base address 0xf1000000 (e.g. 0x50000 instead of 0x5000).

As address ranges D and E are merged in a single reg entry, how is the GIC driver supposed to know about this multiplication factor?

Thanks!

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

From: Geert Uytterhoeven <[email protected]>

Add all clocks generated from PLL1 by the CPG common divider block.

---
Changes since v10:
- None

Changes since V9: (Magnus Damm <[email protected]>)
- Introduce pll1_div2 by folding in earlier posted patch:
[PATCH][RFC] arm64: renesas: r8a7795 dtsi: Update common divider clocks

Changes since V8: (Magnus Damm <[email protected]>)
- Updated commit message.

Changes since V7: (Magnus Damm <[email protected]>)
- Folded in s3d4_clk
- Reordered to apply without SCIF bits

Based on:
[PATCH 3/3] arm64: renesas: r8a7795 dtsi: Add all common divider clocks

---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 169 +++++++++++++++++++++++++++++++
 1 file changed, 169 insertions(+)

index ff6e0e98664a..77f93a77aa79 100644
@@ -70,6 +70,175 @@
 			#clock-cells = <1>;
 			ranges;
 
+			/* Fixed factor clocks */
+			pll1_div2_clk: pll1_div2 {
+				compatible = "fixed-factor-clock";
+				clocks = <&cpg_clocks R8A7795_CLK_PLL1>;
+				#clock-cells = <0>;
+				clock-div = <2>;
+				clock-mult = <1>;
+			};
+
+			zt_clk: zt {
+				compatible = "fixed-factor-clock";
+				clocks = <&pll1_div2_clk>;
+				#clock-cells = <0>;
+				clock-div = <4>;
+				clock-mult = <1>;
+			};
+
+			ztr_clk: ztr {
+				compatible = "fixed-factor-clock";
+				clocks = <&pll1_div2_clk>;
+				#clock-cells = <0>;
+				clock-div = <6>;
+				clock-mult = <1>;
+			};
+
+			ztrd2_clk: ztrd2 {
+				compatible = "fixed-factor-clock";
+				clocks = <&pll1_div2_clk>;
+				#clock-cells = <0>;
+				clock-div = <12>;
+				clock-mult = <1>;
+			};
+
+			zx_clk: zx {
+				compatible = "fixed-factor-clock";
+				clocks = <&pll1_div2_clk>;
+				#clock-cells = <0>;
+				clock-div = <2>;
+				clock-mult = <1>;
+			};
+
+			s0_clk: s0 {
+				compatible = "fixed-factor-clock";
+				clocks = <&pll1_div2_clk>;
+				#clock-cells = <0>;
+				clock-div = <2>;
+				clock-mult = <1>;
+			};
+
+			s0d1_clk: s0d1 {
+				compatible = "fixed-factor-clock";
+				clocks = <&s0_clk>;
+				#clock-cells = <0>;
+				clock-div = <1>;
+				clock-mult = <1>;
+			};
+
+			s0d4_clk: s0d4 {
+				compatible = "fixed-factor-clock";
+				clocks = <&s0_clk>;
+				#clock-cells = <0>;
+				clock-div = <4>;
+				clock-mult = <1>;
+			};
+
+			s1_clk: s1 {
+				compatible = "fixed-factor-clock";
+				clocks = <&pll1_div2_clk>;
+				#clock-cells = <0>;
+				clock-div = <3>;
+				clock-mult = <1>;
+			};
+
+			s1d1_clk: s1d1 {
+				compatible = "fixed-factor-clock";
+				clocks = <&s1_clk>;
+				#clock-cells = <0>;
+				clock-div = <1>;
+				clock-mult = <1>;
+			};
+
+			s1d2_clk: s1d2 {
+				compatible = "fixed-factor-clock";
+				clocks = <&s1_clk>;
+				#clock-cells = <0>;
+				clock-div = <2>;
+				clock-mult = <1>;
+			};
+
+			s1d4_clk: s1d4 {
+				compatible = "fixed-factor-clock";
+				clocks = <&s1_clk>;
+				#clock-cells = <0>;
+				clock-div = <4>;
+				clock-mult = <1>;
+			};
+
+			s2_clk: s2 {
+				compatible = "fixed-factor-clock";
+				clocks = <&pll1_div2_clk>;
+				#clock-cells = <0>;
+				clock-div = <4>;
+				clock-mult = <1>;
+			};
+
+			s2d1_clk: s2d1 {
+				compatible = "fixed-factor-clock";
+				clocks = <&s2_clk>;
+				#clock-cells = <0>;
+				clock-div = <1>;
+				clock-mult = <1>;
+			};
+
+			s2d2_clk: s2d2 {
+				compatible = "fixed-factor-clock";
+				clocks = <&s2_clk>;
+				#clock-cells = <0>;
+				clock-div = <2>;
+				clock-mult = <1>;
+			};
+
+			s2d4_clk: s2d4 {
+				compatible = "fixed-factor-clock";
+				clocks = <&s2_clk>;
+				#clock-cells = <0>;
+				clock-div = <4>;
+				clock-mult = <1>;
+			};
+
+			s3_clk: s3 {
+				compatible = "fixed-factor-clock";
+				clocks = <&pll1_div2_clk>;
+				#clock-cells = <0>;
+				clock-div = <6>;
+				clock-mult = <1>;
+			};
+
+			s3d1_clk: s3d1 {
+				compatible = "fixed-factor-clock";
+				clocks = <&s3_clk>;
+				#clock-cells = <0>;
+				clock-div = <1>;
+				clock-mult = <1>;
+			};
+
+			s3d2_clk: s3d2 {
+				compatible = "fixed-factor-clock";
+				clocks = <&s3_clk>;
+				#clock-cells = <0>;
+				clock-div = <2>;
+				clock-mult = <1>;
+			};
+
+			s3d4_clk: s3d4 {
+				compatible = "fixed-factor-clock";
+				clocks = <&s3_clk>;
+				#clock-cells = <0>;
+				clock-div = <4>;
+				clock-mult = <1>;
+			};
+
+			cl_clk: cl {
+				compatible = "fixed-factor-clock";
+				clocks = <&pll1_div2_clk>;
+				#clock-cells = <0>;
+				clock-div = <48>;
+				clock-mult = <1>;
+			};
+
 			cpg_clocks: cpg_clocks at e6150000 {
 				compatible = "renesas,r8a7795-cpg-clocks",
 					     "renesas,rcar-gen3-cpg-clocks";

2.1.4

From: Geert Uytterhoeven <[email protected]>

Add dummy nodes for the 3 DMA controllers.
This allows to start describing DMA channels for DMA slaves now.

---
Changes since v10:
- None

Changes from V9: (Magnus Damm <[email protected]>)
- Updated to remove fuzz

Changes from V8: (Magnus Damm <[email protected]>)
- Updated to remove fuzz

Changes from V7: (Magnus Damm <[email protected]>)
- Changed order not to depend on SCIF patch(es)

Based on:
[PATCH 2/6] arm64: renesas: r8a7795 dtsi: Add dummy dma-controller nodes

---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

index 77f93a77aa79..3d97a089e8be 100644
@@ -254,5 +254,17 @@
 				#power-domain-cells = <0>;
 			};
 		};
+
+		dmac0: dma-controller at e6700000 {
+			/* Empty node for now */
+		};
+
+		dmac1: dma-controller at e7300000 {
+			/* Empty node for now */
+		};
+
+		dmac2: dma-controller at e7310000 {
+			/* Empty node for now */
+		};
 	};
 };

2.1.4

From: Geert Uytterhoeven <[email protected]>

Add the device nodes for all R-Car H3 SCIF serial ports, incl. clocks, clock domain, and dma properties.

---
Changes since V10 (Simon Horman <[email protected]>)
- As suggested by Geert Uyterhoven
+ R8A7795_CLK_SCIF2 is 310 not 210

Changes since V9: (Magnus Damm <[email protected]>)
- Added SCIF2 DMA bits again
- Converted DT nodes for MSTP to MSSR, adjusted r8a7795-clock.h
- Include clock-output-names

Changes since V8: (Magnus Damm <[email protected]>)
- Dropped SCIF2 DMA bits - thanks Laurent!
- Changed name of mstp2 and mstp3 nodes - thanks Geert!
- Added Acked-by from Laurent

Changes since V7: (Magnus Damm <[email protected]>)
- Folded together above SCIF2 patches
- Added SCIF2 DMA bits
- Got rid of clock-output-names
- Replaced renesas,clock-indices with clock-indices

Based on:
[PATCH 9/25] arm64: renesas: r8a7795: Add SCIF2 support [PATCH 1/6] arm64: renesas: r8a7795 dtsi: Mark scif2 disabled [PATCH 3/6] arm64: renesas: r8a7795 dtsi: Add all SCIF nodes

---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi  | 109 ++++++++++++++++++++++++++++++
 include/dt-bindings/clock/r8a7795-clock.h |   6 ++
 2 files changed, 115 insertions(+)

index 3d97a089e8be..0d7ac639094f 100644
@@ -240,6 +240,11 @@
 			};
 
 			cpg_clocks: cpg_clocks at e6150000 {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				#clock-cells = <1>;
+				ranges;
+
 				compatible = "renesas,r8a7795-cpg-clocks",
 					     "renesas,rcar-gen3-cpg-clocks";
 				reg = <0 0xe6150000 0 0x1000>;

@@ -252,6 +257,38 @@
 				clock-output-names = "main", "pll0", "pll1",
 						     "pll2", "pll3", "pll4";
 				#power-domain-cells = <0>;
+
+				/* Module Standby and Software Reset */
+				mssr: mssr at e6150130 {
+					compatible =
+						"renesas,r8a7795-cpg-mssr";
+					reg = <0 0xe6150000 0 0x1000>;
+					#clock-cells = <1>;
+					clocks =
+						/* MSTP2 */
+						<&s3d4_clk>, <&s3d4_clk>,
+						<&s3d4_clk>, <&s3d4_clk>,
+						<&s3d4_clk>,
+						/* MSTP3 */
+						<&s3d4_clk>;
+					clock-indices = <
+						/* MSTP2 */
+						R8A7795_CLK_SCIF5
+						R8A7795_CLK_SCIF4
+						R8A7795_CLK_SCIF3
+						R8A7795_CLK_SCIF1
+						R8A7795_CLK_SCIF0
+						/* MSTP3 */
+						R8A7795_CLK_SCIF2
+					>;
+					clock-output-names =
+						/* MSTP2 */
+						"scif5", "scif4", "scif3",
+						"scif1", "scif0",
+						/* MSTP3 */
+						"scif2";
+					#reset-cells = <1>;
+				};
 			};
 		};
 

@@ -266,5 +303,77 @@
 		dmac2: dma-controller at e7310000 {
 			/* Empty node for now */
 		};
+
+		scif0: serial at e6e60000 {
+			compatible = "renesas,scif-r8a7795", "renesas,scif";
+			reg = <0 0xe6e60000 0 64>;
+			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mssr R8A7795_CLK_SCIF0>;
+			clock-names = "sci_ick";
+			dmas = <&dmac1 0x51>, <&dmac1 0x50>;
+			dma-names = "tx", "rx";
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		scif1: serial at e6e68000 {
+			compatible = "renesas,scif-r8a7795", "renesas,scif";
+			reg = <0 0xe6e68000 0 64>;
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mssr R8A7795_CLK_SCIF1>;
+			clock-names = "sci_ick";
+			dmas = <&dmac1 0x53>, <&dmac1 0x52>;
+			dma-names = "tx", "rx";
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		scif2: serial at e6e88000 {
+			compatible = "renesas,scif-r8a7795", "renesas,scif";
+			reg = <0 0xe6e88000 0 64>;
+			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mssr R8A7795_CLK_SCIF2>;
+			clock-names = "sci_ick";
+			dmas = <&dmac1 0x13>, <&dmac1 0x12>;
+			dma-names = "tx", "rx";
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		scif3: serial at e6c50000 {
+			compatible = "renesas,scif-r8a7795", "renesas,scif";
+			reg = <0 0xe6c50000 0 64>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mssr R8A7795_CLK_SCIF3>;
+			clock-names = "sci_ick";
+			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
+			dma-names = "tx", "rx";
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		scif4: serial at e6c40000 {
+			compatible = "renesas,scif-r8a7795", "renesas,scif";
+			reg = <0 0xe6c40000 0 64>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mssr R8A7795_CLK_SCIF4>;
+			clock-names = "sci_ick";
+			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
+			dma-names = "tx", "rx";
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
+
+		scif5: serial at e6f30000 {
+			compatible = "renesas,scif-r8a7795", "renesas,scif";
+			reg = <0 0xe6f30000 0 64>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mssr R8A7795_CLK_SCIF5>;
+			clock-names = "sci_ick";
+			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
+			dma-names = "tx", "rx";
+			power-domains = <&cpg_clocks>;
+			status = "disabled";
+		};
 	};
 };

index 334fa13d1bb4..51048d79f80d 100644
@@ -22,8 +22,14 @@
 /* MSTP1 */
 
 /* MSTP2 */
+#define R8A7795_CLK_SCIF5		202
+#define R8A7795_CLK_SCIF4		203
+#define R8A7795_CLK_SCIF3		204
+#define R8A7795_CLK_SCIF1		206
+#define R8A7795_CLK_SCIF0		207
 
 /* MSTP3 */
+#define R8A7795_CLK_SCIF2		310
 
 /* MSTP5 */
 

2.1.4

From: Kuninori Morimoto <[email protected]>

Add a PFC node for the on-chip r8a7795 pin controller.

---
Changes since v10:
- None

Changes since V9: (Magnus Damm <[email protected]>)
- None

Changes since V8: (Magnus Damm <[email protected]>)
- Dropped Kconfig TODO - select PINCTRL happens in patch 1
- Added Acked-by from Laurent

Changes since V7: (Magnus Damm <[email protected]>)
- Added changelog

Based on:
[PATCH 10/25 v7][RFC] arm64: renesas: r8a7795: enable PFC

---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

index 0d7ac639094f..e2cc40fa5aa3 100644
@@ -292,6 +292,11 @@
 			};
 		};
 
+		pfc: pfc at e6060000 {
+			compatible = "renesas,pfc-r8a7795";
+			reg = <0 0xe6060000 0 0x50c>;
+		};
+
 		dmac0: dma-controller at e6700000 {
 			/* Empty node for now */
 		};

2.1.4

From: Kuninori Morimoto <[email protected]>

Add initial board support for r8a7795 Salvator-X. At this point only DEBUG0 and DEBUG1 serial ports are supported.

---
Changes since v10:
- None

Changes since V9: (Magnus Damm <[email protected]>)
- Added board specific EXTAL information by folding in:
[PATCH][RFC] arm64: renesas: Add EXTAL configuration to Salvator-X

Changes since V8: (Magnus Damm <[email protected]>)
- None

Changes since V7: (Magnus Damm <[email protected]>)
- Added changelog

Based on:
[PATCH 15/25] arm64: renesas: add Salvator-X board support on DTS [PATCH 5/5] arm64: renesas: salvator-x: Update SCIF2 pin group [PATCH 5/6] arm64: renesas: salvator-x: Enable SCIF1 on serial1

---
 Documentation/devicetree/bindings/arm/shmobile.txt |  2 +
 arch/arm64/boot/dts/renesas/Makefile               |  2 +
 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 62 ++++++++++++++++++++++
 3 files changed, 66 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts

index 8d696a0d62b3..95d0aea4c701 100644
@@ -59,6 +59,8 @@ Boards:
     compatible = "renesas,lager", "renesas,r8a7790"
   - Marzen
     compatible = "renesas,marzen", "renesas,r8a7779"
+  - Salvator-X
+    compatible = "renesas,salvator-x", "renesas,r8a7795";
 
 Note: Reference Device Tree Implementations are temporary implementations
       to ease the migration from platform devices to Device Tree, and are

index fec69f46d65b..9ce1890a650e 100644
@@ -1,2 +1,4 @@
+dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb
+
 always		:= $(dtb-y)
 clean-files	:= *.dtb

2.1.4

I agree this looks a bit lonely by itself, and I'm not entirely opposed to removing it. However, I do seek consistency between the renesas ARM and ARM64 SoCs where possible.

Further work[1] on this file outside of this series adds "rw root=/dev/nfs ip=dhcp" to bootargs, the result being consistent with Renesas ARM32 SoCs.

[1] [PATCH v5 4/5] arm64: dts: r8a7795: enable nfs root on Salvator-X board

    http://www.spinics.net/lists/arm-kernel/msg452743.html

I think that we have had this discussion before in relation to a different board for a different Renesas SoC but I could be mistaken.

The r8a7795 uses the sh-sci serial driver for which the default rate is 115200. It is hard for me to conceive of a situation where that would change without due consideration being given to the implications for DT files.

Not specifying the baud here is consistent with what we have been doing for ARM32 Renesas SoCs for some time.

Hi Simon,

IIRC, at that time the code to parse the options wasn't upstream yet, so adding the options would have broken the serial console.

I can confirm it works fine on Salvator-X with

        stdout-path = "serial0:115200n8";

FWIW, I have updated all ARM32 Renesas DTSes locally:
1. Use alias in and add serial options to stdout-path,
2. Drop superfluous console= from bootargs (shmobile-legacy is gone, and it works fine on boards with both fbdev and serial consoles).

And everything looks fine on the boards I could try it on (sh73a0/kzm9g, r8a73a4/ape6evm, r8a7740/armadillo, r8a7791/koelsch).

Hence if you're open for this change, I can submit patches (or a single patch, up to your preference).

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Thanks.

Is this considered to be best practice?
If so I am of a mind to update the patch.

Sure, I'm happy to consider that (I slightly prefer per-board patches) if:

* That is now considered best practice and;
* Due consideration is given to backwards compatibility (I suspect it is new DTs work with old kernels so its a non-issue)

Hi Mark, Rob,

Unfortunately this breaks earlycon support:

Malformed early option 'earlycon'

The call to fdt_getprop() in early_init_dt_scan_chosen_serial() fails. I guess that unlike the standard console handling code, the fdt code can't handle aliases yet?

P.S. SCIF earlycon support is not yet upstream, as it still doesn't work on arm32 (I discovered today it does on arm64 ;-): it pretends to work, but nothing is output to the serial port (until the normal serial console kicks in).

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Hi,

As discussed off-list.

I will update the stdout-path as Mark suggested.
The expectation being that early con will support that syntax.

Apparently this issue was fixed in v4.4-rc1. For the backport team:

commit 6296ad9e3375c6c1ddbb371f589ba6a145bb31df

Author: Stefan Agner <[email protected]>
Date:   Sat Oct 10 01:29:30 2015 -0700

of/fdt: fix aliases with baudrate in earlycon

And this issue is mostly resolved, too. So v4.5 will be perfect ;-)

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Excellent!

From: Kuninori Morimoto <[email protected]>

This patch enables the Renesas R-Car H3 SoC together with the SCIF driver in the arm64 defconfig.

---
Changes since v10:
- None

Changes since V9: (Magnus Damm <[email protected]>)
- None

Changes since V8: (Magnus Damm <[email protected]>)
- Added Acked-by from Geert

Changes since V7: (Magnus Damm <[email protected]>)
- Updated changelog
- Use CONFIG_RENESAS and CONFIG_R8A7795

Based on:
[PATCH 19/25] arm64: defconfig: renesas: Enable Renesas R-Car Gen3 SoC [PATCH 20/25] arm64: defconfig: renesas: enable SCIF

---
 arch/arm64/configs/defconfig | 5 +++++
 1 file changed, 5 insertions(+)

index 34d71dd86781..dccc685b58ae 100644
@@ -39,6 +39,8 @@ CONFIG_ARCH_HISI=y
 CONFIG_ARCH_MEDIATEK=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_ARCH_SEATTLE=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_R8A7795=y
 CONFIG_ARCH_TEGRA=y
 CONFIG_ARCH_TEGRA_132_SOC=y
 CONFIG_ARCH_QCOM=y

@@ -109,6 +111,9 @@ CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_8250_MT6577=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=11
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
 CONFIG_SERIAL_MSM=y
 CONFIG_SERIAL_MSM_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y

2.1.4

Initial Renesas arm64 architecture support will be for the R-Car H3, r8a7795, SoC and its Salvator-X board.

---

Changes since v10:
- New Patch

---
 MAINTAINERS | 10 ++++++++++
 1 file changed, 10 insertions(+)

index 7ba7ab749c85..0067b7156622 100644
@@ -1392,6 +1392,16 @@ M:	Lennert Buytenhek <[email protected]>
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 
+ARM/RENESAS ARM64 ARCHITECTURE
+M:	Simon Horman <[email protected]>
+M:	Magnus Damm <[email protected]>
+L:	linux-sh at vger.kernel.org
+W:	http://oss.renesas.com
+Q:	http://patchwork.kernel.org/project/linux-sh/list/
+T:	git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next
+S:	Supported
+F:	arch/arm64/boot/dts/renesas/
+
 ARM/RISCPC ARCHITECTURE
 M:	Russell King <[email protected]>
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)

2.1.4

Hi Simon,

Thanks for your patch.

The file being modified has this in it:

Note: For the hard of thinking, this list is meant to remain in alphabetical order. If you could add yourselves to it in alphabetical order that would be so much easier [Ed]

It's not freely orderable.

There is no "ARM/RENESAS ARM ARCHITECTURE" in the file. There is "ARM/SHMOBILE ARM ARCHITECTURE" though.

FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

I see. Thanks for your explanation.