doc/bindings: Update Layerscape PCIe devicetree bindings for LS2080A
PATCH 1/1 doc/bindings: Update Layerscape PCIe devicetree bindings for LS2080A
Update the definition of the Layerscape PCI compatible string to add support for LS2080A, as the controller on LS2080A is different from LS1021A SoC.
While at it, move the clock related properties in the Designware PCIe controller bindings to 'optional' set of properties.
---
Hi Bjorn,
As discussed with Arnd (http://www.spinics.net/lists/linux-clk/msg04092.html),
this patch depends on a patch that is in your PCI tree but not yet in mainline.
So, sending this to you, so that you can apply the patch on top of the other one.
.../devicetree/bindings/pci/designware-pcie.txt | 10 +++++----- .../devicetree/bindings/pci/layerscape-pci.txt | 14 ++++++++++++-- 2 files changed, 17 insertions(+), 7 deletions(-)
Documentation/devicetree/bindings/pci/designware-pcie.txt +5 -5
@@ -14,11 +14,6 @@ Required properties: - interrupt-map-mask and interrupt-map: standard PCI properties to define the mapping of the PCIe interface to interrupt numbers. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - "pcie" - - "pcie_bus" Optional properties: - num-lanes: number of lanes to use (this property should be specified unless
@@ -27,3 +22,8 @@ Optional properties: - bus-range: PCI bus numbers covered (it is recommended for new devicetrees to specify this property, to keep backwards compatibility a range of 0x00-0xff is assumed if not present) +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - "pcie" + - "pcie_bus"
Documentation/devicetree/bindings/pci/layerscape-pci.txt +12 -2
@@ -1,10 +1,20 @@ Freescale Layerscape PCIe controller -This PCIe host controller is based on the Synopsis Designware PCIe IP +This PCIe host controller is based on the Synopsys Designware PCIe IP and thus inherits all the common properties defined in designware-pcie.txt. +This controller derives its clocks from the Reset Configuration Word (RCW) +which is used to describe the PLL settings at the time of chip-reset. + +Also as per the available Reference Manuals, there is no specific 'version' +register available in the Freescale PCIe controller register set, +which can allow determining the underlying Designware PCIe controller version +information. + Required properties: -- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie" +- compatible: should contain the platform identifier such as: + "fsl,ls1021a-pcie", "snps,dw-pcie" + "fsl,ls2080a-pcie", "snps,dw-pcie" - reg: base addresses and lengths of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property.
Signature · 1 line
1.7.9.5
PATCH 1/1 doc/bindings: Update Layerscape PCIe devicetree bindings for LS2080A
Hi Bjorn,
Quoted 16 lines
From: Bhupesh Sharma [mailto:bhupesh.sharma at freescale.com]
Sent: Monday, October 26, 2015 1:01 PMUpdate the definition of the Layerscape PCI compatible string to add support for LS2080A, as the controller on LS2080A is different from LS1021A SoC.
While at it, move the clock related properties in the Designware PCIe controller bindings to 'optional' set of properties.
Signed-off-by Minghuan Lian <[email protected]>Signed-off-by Bhupesh Sharma <[email protected]>Acked-by Arnd Bergmann <[email protected]>---
Hi Bjorn,
Quoted 7 lines
As discussed with Arnd (http://www.spinics.net/lists/linux-
clk/msg04092.html),
this patch depends on a patch that is in your PCI tree but not yet in mainline.So, sending this to you, so that you can apply the patch on top of the other one.
Ping..
Quoted 64 lines
.../devicetree/bindings/pci/designware-pcie.txt | 10 +++++----- .../devicetree/bindings/pci/layerscape-pci.txt | 14 ++++++++++++-- 2 files changed, 17 insertions(+), 7 deletions(-)Documentation/devicetree/bindings/pci/designware-pcie.txt +0
-5@@ -14,11 +14,6 @@ Required properties: - interrupt-map-mask and interrupt-map: standard PCI properties to define the mapping of the PCIe interface to interrupt numbers. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - "pcie" - - "pcie_bus" Optional properties: - num-lanes: number of lanes to use (this property should be specifiedunless @@ -27,3 +22,8 @@ Optional properties:
- bus-range: PCI bus numbers covered (it is recommended for new
devicetrees to
specify this property, to keep backwards compatibility a range of
0x00-0xff
is assumed if not present)
+- clocks: Must contain an entry for each entry in clock-names.Documentation/devicetree/bindings/pci/designware-pcie.txt +4
-0+ See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - "pcie" + - "pcie_bus"Documentation/devicetree/bindings/pci/layerscape-pci.txt +1
-1@@ -1,10 +1,20 @@ Freescale Layerscape PCIe controller -This PCIe host controller is based on the Synopsis Designware PCIe IP +This PCIe host controller is based on the Synopsys Designware PCIe IP and thus inherits all the common properties defined in designware-pcie.txt.
Documentation/devicetree/bindings/pci/layerscape-pci.txt +2
-0+This controller derives its clocks from the Reset Configuration Word +(RCW) which is used to describe the PLL settings at the time of chip-reset.
Documentation/devicetree/bindings/pci/layerscape-pci.txt +2
-0+ +Also as per the available Reference Manuals, there is no specific'version'
Documentation/devicetree/bindings/pci/layerscape-pci.txt +4
-1+register available in the Freescale PCIe controller register set, which +can allow determining the underlying Designware PCIe controller version +information. + Required properties: -- compatible: should contain the platform identifier such as"fsl,ls1021a-pcie"
+- compatible: should contain the platform identifier such as:Documentation/devicetree/bindings/pci/layerscape-pci.txt +2
-0+ "fsl,ls1021a-pcie", "snps,dw-pcie" + "fsl,ls2080a-pcie", "snps,dw-pcie" - reg: base addresses and lengths of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must
Quoted 5 lines
contain an
entry for each entry in the interrupt-names property.
--
1.7.9.5
Regards,
Bhupesh
PATCH 1/1 doc/bindings: Update Layerscape PCIe devicetree bindings for LS2080A
In reply to Bhupesh SharmaQuoted 13 lines · Bhupesh Sharma
Update the definition of the Layerscape PCI compatible string to add support for LS2080A, as the controller on LS2080A is different from LS1021A SoC.
While at it, move the clock related properties in the Designware PCIe controller bindings to 'optional' set of properties.
Signed-off-by Minghuan Lian <[email protected]>Signed-off-by Bhupesh Sharma <[email protected]>Acked-by Arnd Bergmann <[email protected]>---
Hi Bjorn,
Quoted 8 lines
As discussed with Arnd (http://www.spinics.net/lists/linux-clk/msg04092.html),
this patch depends on a patch that is in your PCI tree but not yet in mainline.So, sending this to you, so that you can apply the patch on top of the other one.
.../devicetree/bindings/pci/designware-pcie.txt | 10 +++++----- .../devicetree/bindings/pci/layerscape-pci.txt | 14 ++++++++++++--
Split into two patches and applied to pci/host-designware and pci/host-layerscape, since the clocks change doesn't look related to the Layerscape change.
Quoted 60 lines
Documentation/devicetree/bindings/pci/designware-pcie.txt +5
-5@@ -14,11 +14,6 @@ Required properties: - interrupt-map-mask and interrupt-map: standard PCI properties to define the mapping of the PCIe interface to interrupt numbers. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - "pcie" - - "pcie_bus" Optional properties: - num-lanes: number of lanes to use (this property should be specified unless@@ -27,3 +22,8 @@ Optional properties: - bus-range: PCI bus numbers covered (it is recommended for new devicetrees to specify this property, to keep backwards compatibility a range of 0x00-0xff is assumed if not present) +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - "pcie" + - "pcie_bus"Documentation/devicetree/bindings/pci/layerscape-pci.txt +12
-2@@ -1,10 +1,20 @@ Freescale Layerscape PCIe controller -This PCIe host controller is based on the Synopsis Designware PCIe IP +This PCIe host controller is based on the Synopsys Designware PCIe IP and thus inherits all the common properties defined in designware-pcie.txt. +This controller derives its clocks from the Reset Configuration Word (RCW) +which is used to describe the PLL settings at the time of chip-reset. + +Also as per the available Reference Manuals, there is no specific 'version' +register available in the Freescale PCIe controller register set, +which can allow determining the underlying Designware PCIe controller version +information. + Required properties: -- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie" +- compatible: should contain the platform identifier such as: + "fsl,ls1021a-pcie", "snps,dw-pcie" + "fsl,ls2080a-pcie", "snps,dw-pcie" - reg: base addresses and lengths of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property.Signature · 7 lines
1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo at vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
PATCH 1/1 doc/bindings: Update Layerscape PCIe devicetree bindings for LS2080A
Quoted 25 lines
From: Bjorn Helgaas [mailto:helgaas at kernel.org]
Sent: Tuesday, November 03, 2015 3:31 AMQuoted 10 lines · Bhupesh Sharma
Update the definition of the Layerscape PCI compatible string to add support for LS2080A, as the controller on LS2080A is different from LS1021A SoC.
While at it, move the clock related properties in the Designware PCIe controller bindings to 'optional' set of properties.
Signed-off-by Minghuan Lian <[email protected]>Signed-off-by Bhupesh Sharma <[email protected]>Acked-by Arnd Bergmann <[email protected]>Quoted 6 lines
---
Hi Bjorn,As discussed with Arnd
(http://www.spinics.net/lists/linux-clk/msg04092.html),
this patch depends on a patch that is in your PCI tree but not yet inmainline.
Quoted 4 lines
So, sending this to you, so that you can apply the patch on top of the other one.
Quoted 7 lines
Quoted 2 lines
.../devicetree/bindings/pci/designware-pcie.txt | 10 +++++----- .../devicetree/bindings/pci/layerscape-pci.txt | 14++++++++++++--
Split into two patches and applied to pci/host-designware and pci/host- layerscape, since the clocks change doesn't look related to the Layerscape change.
Thanks Bjorn.
Regards,
Bhupesh
Quoted 69 lines
Quoted 17 lines
Documentation/devicetree/bindings/pci/designware-pcie.txt +0
-5@@ -14,11 +14,6 @@ Required properties: - interrupt-map-mask and interrupt-map: standard PCI properties to define the mapping of the PCIe interface to interrupt numbers. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - "pcie" - - "pcie_bus" Optional properties: - num-lanes: number of lanes to use (this property should beQuoted 2 lines
specified unless @@ -27,3 +22,8 @@ Optional properties:
- bus-range: PCI bus numbers covered (it is recommended for newdevicetrees to
Quoted 1 line
specify this property, to keep backwards compatibility a range of
0x00-0xff
Quoted 12 lines
is assumed if not present)
+- clocks: Must contain an entry for each entry in clock-names.Documentation/devicetree/bindings/pci/designware-pcie.txt +4
-0+ See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - "pcie" + - "pcie_bus"Documentation/devicetree/bindings/pci/layerscape-pci.txt +0
-0Documentation/devicetree/bindings/pci/layerscape-pci.txt line 4
Quoted 5 lines
Documentation/devicetree/bindings/pci/layerscape-pci.txt +1
-1@@ -1,10 +1,20 @@ Freescale Layerscape PCIe controller -This PCIe host controller is based on the Synopsis Designware PCIe IP +This PCIe host controller is based on the Synopsys Designware PCIe IP and thus inherits all the common properties defined in designware-pcie.txt.
Documentation/devicetree/bindings/pci/layerscape-pci.txt line 6
Quoted 3 lines
Documentation/devicetree/bindings/pci/layerscape-pci.txt +2
-0+This controller derives its clocks from the Reset Configuration Word +(RCW) which is used to describe the PLL settings at the time of chip-reset.
Documentation/devicetree/bindings/pci/layerscape-pci.txt line 8
Quoted 2 lines
Documentation/devicetree/bindings/pci/layerscape-pci.txt +2
-0+ +Also as per the available Reference Manuals, there is no specific'version'
Documentation/devicetree/bindings/pci/layerscape-pci.txt
Quoted 6 lines
Documentation/devicetree/bindings/pci/layerscape-pci.txt +4
-1+register available in the Freescale PCIe controller register set, +which can allow determining the underlying Designware PCIe controller +version information. + Required properties: -- compatible: should contain the platform identifier such as"fsl,ls1021a-pcie"
Documentation/devicetree/bindings/pci/layerscape-pci.txt
Quoted 5 lines
Documentation/devicetree/bindings/pci/layerscape-pci.txt +3
-0+- compatible: should contain the platform identifier such as: + "fsl,ls1021a-pcie", "snps,dw-pcie" + "fsl,ls2080a-pcie", "snps,dw-pcie" - reg: base addresses and lengths of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Mustcontain an
Quoted 9 lines
Documentation/devicetree/bindings/pci/layerscape-pci.txt +0
-1entry for each entry in the interrupt-names property. --1.7.9.5
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