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arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines

PATCH New dinguyen at opensource.altera.com 2 participants 5 messages Nov 2, 2015 – Nov 3, 2015

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm/socfpga architecture
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dinguyen at opensource.altera.com

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#0 lore raw

PATCH 1/1 arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines

From: Dinh Nguyen <[email protected]>

The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0.

Signed-off-by Dinh Nguyen <[email protected]>
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
arch/arm/mach-socfpga/include/mach/reset_manager.h +3 -3
index 8e59578..666a2ef 100644
@@ -69,9 +69,9 @@ struct socfpga_reset_manager {
 #define RSTMGR_UART0		RSTMGR_DEFINE(1, 16)
 #define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 18)
 #define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 19)
-#define RSTMGR_QSPI		RSTMGR_DEFINE(0, 5)
-#define RSTMGR_SDMMC		RSTMGR_DEFINE(0, 22)
-#define RSTMGR_DMA		RSTMGR_DEFINE(0, 28)
+#define RSTMGR_QSPI		RSTMGR_DEFINE(1, 5)
+#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 22)
+#define RSTMGR_DMA		RSTMGR_DEFINE(1, 28)
 #define RSTMGR_SDR		RSTMGR_DEFINE(1, 29)
 
 /* Create a human-readable reference to SoCFPGA reset. */
Signature · 1 line
2.6.2
#1 lore raw

PATCH 1/1 arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines

Quoted 6 lines · dinguyen at opensource.altera.com

From: Dinh Nguyen <[email protected]>

The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0.

Signed-off-by Dinh Nguyen <[email protected]>

Thanks for finding this:

Acked-by Marek Vasut <[email protected]>

btw. how did you find this? I doubt it was some casual reading of the source code :)

Best regards,
Marek Vasut

author
#2 lore raw

PATCH 1/1 arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines

Quoted 7 lines · Marek Vasut
Quoted 5 lines · dinguyen at opensource.altera.com

From: Dinh Nguyen <[email protected]>

The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0.

Quoted 8 lines
Quoted 1 line
Signed-off-by Dinh Nguyen <[email protected]>

Thanks for finding this:

Acked-by Marek Vasut <[email protected]>

btw. how did you find this? I doubt it was some casual reading of the source code :)

I stumbled on this when I started adding the reset driver for Arria10, and did a quick code review.

BR,
Dinh

#3 lore raw

PATCH 1/1 arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines

Quoted 13 lines · Dinh Nguyen
Quoted 12 lines · Marek Vasut

On Tuesday, November 03, 2015 at 12:11:21 AM,
dinguyen at opensource.altera.com

Quoted 7 lines · wrote:

From: Dinh Nguyen <[email protected]>

The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0.

Signed-off-by Dinh Nguyen <[email protected]>
Quoted 8 lines
Quoted 5 lines

Thanks for finding this:

Acked-by Marek Vasut <[email protected]>

btw. how did you find this? I doubt it was some casual reading of the source code :)

I stumbled on this when I started adding the reset driver for Arria10, and did a quick code review.

Neat !

Best regards,
Marek Vasut

Applied
#4 lore raw

PATCH 1/1 arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines

In reply to dinguyen at opensource.altera.com
Quoted 6 lines · dinguyen at opensource.altera.com

From: Dinh Nguyen <[email protected]>

The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0.

Signed-off-by Dinh Nguyen <[email protected]>

Applied, thanks!

Best regards,
Marek Vasut