dm: Introduce Rockchip RK3288 support
Subsystems (12)
v4 cover dm: Introduce Rockchip RK3288 support
The Rockchip RK3288 is based on a quad-core Cortex-A17 CPU and has a good set of peripherals. Various full-featured U-Boot ports are available and this is an attempt to bring those features into mainline. With this series the Firefly RK3288 can boot to a prompt from an SD card.
Since much of the code is generic, this also supports the Radxa Rock 2. Since there is no device tree available for that yet, it uses the same config and device tree as the Firefly. This works because not all peripherals are supported, so the differences don't matter.
Support for booting from USB OTG is also provided, using the on-chip boot ROM and the rkflashtool utility. This can boot as far as SPL, but there is no support for reading U-Boot proper from USB as yet. This requires implementing a suitable protocol (perhaps DFU or Rockchip's proprietary one) in SPL.
Support is also provided for the Hisense Chromebook, which is based on the same SoC. In this case it boots from SPI rather than an SD card.
This seriea makes use of driver model including a number of recently added uclasses:
- Clocks - setting and getting PLL and peripheral clocks
- Pinctrl - adjusting pin multiplexing settings
- Reset - reseting the board or SoC
- RAM - setting up RAM controllers and detecting the available RAM
- MMC - MMC controllers (using the existing block device framework)
- LEDs - turning LEDs on and off, with only a GPIO driver so far
This series avoids hard-coding RK3288-specific code into the build. There is a CONFIG_ROCKCHIP_RK3288 but it only *adds* support for RK3288. In principle another CONFIG could add support for a different Rockchip SoC with only the device tree selecting which one U-Boot works on.
Support is provided in mkimage to build these image types:
- rkimage - suitable for packaging up SPL to be sent to the boot ROM over USB OTG
- rksd - suitable for writing to an SD card
Much of the source and ideas for this series came from downstream Rockchip U-Boot trees. SDRAM init came from Coreboot. In most cases it has been pretty heavily cleaned up / rewritten to meet U-Boot style and remove hard-coding of things.
Drivers are provided for:
- Clocks
- Pinctrl
- SoC reset
- DDR3 SDRAM
- I2C
- SPI
- GPIOs
- LEDs using GPIOS
- MMC
- Firefly main PMIC (ACT8846) and included regulators
These are lightly tested and doubtless some problems exist with some, particularly I2C.
One problem with device tree is that U-Boot has no way of dropping features it does not need or use. For SPL this problem needs to be solved and this series uses a new 'fdtgrep' tool for this. The 45KB Firefly device tree reduces to a 6KB bytes when unused material is removed. SDRAM timings are also in the device tree.
There is a large amount of additional work to bring other Rockchip drivers and features into mainline U-Boot, so this is only a start.
Note: This series sits on top of Masahiro's RFC pinctrl series. I wanted to get a new version out while we wait for this to make it to mainline. You can find this series at u-boot-dm/rockchip-working.
Changes in v4:
- Add a set_state_simple() method
- Adjust the defconfig file to suit mainline
- Rename pinctrl.h to dm/pinctrl.h
- Tweak the cover letter a little, drop mention of patches already applied
- Use CONFIG_SPL_LED instead of CONFIG_SPL_LED_SUPPORT
Changes in v3:
- Add device tree bindings for CRU and DMC
- Add various new patches to get RK3288 booting to a prompt
- Make use of additional features since version 2
- Update README to mention available drivers
- Update clock rate to always be 24MHz
Changes in v2:
- Drop use of CONFIG_USE_PRIVATE_LIBGCC=y
- Tidy up license headers and remove SPL #ifdefs
Masahiro Yamada (1):
dm: do not return pointer if NULL is given to devp of device_bind()
Simon Glass (32):
pinctrl: Correct build errors in the pinctrl_simple
pinctrl: Add help text to Kconfig
pinctrl: Add the concept of peripheral IDs
mmc: Support bypass mode with the get_mmc_clk() method
dm: Improve handling of a missing uclass
dm: Provide better debugging when a device fails to bind
arm: reset: Avoid a build error when the reset uclass is enabled
rockchip: Add serial support
rockchip: Bring in RK3288 device tree file includes and bindings
rockchip: rk3288: dts: Make core devices available early
mkimage: Allow padding to any length
mkimage: Allow the original file size to be recorded
rockchip: Add the rkimage format to mkimage
rockchip: Add support for the SD image
rockchip: Add support for the SPI image
rockchip: gpio: Add rockchip GPIO driver
rockchip: Add basic peripheral and clock definitions
power: Add support for ACT8846 PMIC
power: regulator: Add a driver for ACT8846 regulators
rockchip: rk3288: Add clock driver
rockchip: rk3288: Add header files for PMU and GRF
rockchip: rk3288: Add SoC reset driver
rockchip: rk3288: Add a simple syscon driver
rockchip: rk3288: Add pinctrl driver
rockchip: rk3288: Add SDRAM init
rockchip: Add an MMC driver
rockchip: Add core SoC start-up code
rockchip: Add I2C driver
rockchip: Add SPI driver
rockchip: Add basic support for firefly-rk3288
rockchip: Add basic support for jerry
rockchip: Add a simple README
arch/arm/Kconfig | 10 + arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 3 + arch/arm/dts/cros-ec-sbs.dtsi | 16 + arch/arm/dts/rk3288-firefly.dts | 75 + arch/arm/dts/rk3288-firefly.dtsi | 457 ++++++ arch/arm/dts/rk3288-jerry.dts | 203 +++ arch/arm/dts/rk3288-thermal.dtsi | 88 ++ arch/arm/dts/rk3288-veyron-chromebook.dtsi | 200 +++ arch/arm/dts/rk3288-veyron.dtsi | 844 +++++++++++ arch/arm/dts/rk3288.dtsi | 1473 ++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/clock.h | 45 + arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 185 +++ arch/arm/include/asm/arch-rockchip/ddr_rk3288.h | 484 +++++++ arch/arm/include/asm/arch-rockchip/gpio.h | 28 + arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 768 ++++++++++ arch/arm/include/asm/arch-rockchip/hardware.h | 20 + arch/arm/include/asm/arch-rockchip/i2c.h | 70 + arch/arm/include/asm/arch-rockchip/periph.h | 54 + arch/arm/include/asm/arch-rockchip/pmu_rk3288.h | 89 ++ arch/arm/include/asm/arch-rockchip/sdram.h | 92 ++ arch/arm/lib/Makefile | 2 + arch/arm/mach-rockchip/Kconfig | 41 + arch/arm/mach-rockchip/Makefile | 13 + arch/arm/mach-rockchip/board-spl.c | 290 ++++ arch/arm/mach-rockchip/board.c | 46 + arch/arm/mach-rockchip/common.c | 28 + arch/arm/mach-rockchip/rk3288/Kconfig | 26 + arch/arm/mach-rockchip/rk3288/Makefile | 9 + arch/arm/mach-rockchip/rk3288/reset_rk3288.c | 47 + arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 878 ++++++++++++ arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 25 + board/firefly/firefly-rk3288/Kconfig | 15 + board/firefly/firefly-rk3288/MAINTAINERS | 6 + board/firefly/firefly-rk3288/Makefile | 7 + board/firefly/firefly-rk3288/firefly-rk3288.c | 7 + board/google/chromebook_jerry/Kconfig | 15 + board/google/chromebook_jerry/MAINTAINERS | 6 + board/google/chromebook_jerry/Makefile | 7 + board/google/chromebook_jerry/jerry.c | 7 + board/google/common/Makefile | 2 +- common/image.c | 3 + configs/chromebook_jerry_defconfig | 43 + configs/firefly-rk3288_defconfig | 43 + doc/README.rockchip | 246 ++++ .../clock/rockchip,rk3188-cru.txt | 61 + .../clock/rockchip,rk3288-cru.txt | 61 + .../clock/rockchip,rk3288-dmc.txt | 155 ++ doc/device-tree-bindings/clock/rockchip.txt | 77 + .../pinctrl/rockchip,pinctrl.txt | 157 +++ .../thermal/rockchip-thermal.txt | 68 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3288.c | 618 ++++++++ drivers/core/device.c | 10 +- drivers/core/root.c | 5 +- drivers/core/uclass.c | 7 +- drivers/gpio/Kconfig | 9 + drivers/gpio/Makefile | 1 + drivers/gpio/rk_gpio.c | 123 ++ drivers/i2c/Kconfig | 9 + drivers/i2c/Makefile | 1 + drivers/i2c/rk_i2c.c | 391 ++++++ drivers/mmc/Kconfig | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/dw_mmc.c | 2 +- drivers/mmc/exynos_dw_mmc.c | 2 +- drivers/mmc/rockchip_mmc.c | 98 ++ drivers/pinctrl/Kconfig | 22 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-uclass.c | 41 +- drivers/pinctrl/rockchip/Makefile | 8 + drivers/pinctrl/rockchip/pinctrl_rk3288.c | 441 ++++++ drivers/power/pmic/Kconfig | 9 + drivers/power/pmic/Makefile | 1 + drivers/power/pmic/act8846.c | 90 ++ drivers/power/regulator/Kconfig | 9 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/act8846.c | 155 ++ drivers/serial/Kconfig | 9 + drivers/serial/Makefile | 1 + drivers/serial/serial_rockchip.c | 43 + drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/rk_spi.c | 375 +++++ drivers/spi/rk_spi.h | 121 ++ include/configs/chromebook_jerry.h | 16 + include/configs/firefly-rk3288.h | 15 + include/configs/rk3288_common.h | 98 ++ include/dm/pinctrl.h | 61 + include/dt-bindings/clock/rk3288-cru.h | 370 +++++ include/dt-bindings/clock/rockchip,rk808.h | 11 + include/dt-bindings/pinctrl/rockchip.h | 26 + include/dt-bindings/power-domain/rk3288.h | 11 + include/dwmmc.h | 16 +- include/image.h | 5 +- include/power/act8846_pmic.h | 37 + tools/Makefile | 3 + tools/imagetool.h | 1 + tools/mkimage.c | 23 +- tools/rkcommon.c | 72 + tools/rkcommon.h | 28 + tools/rkimage.c | 65 + tools/rksd.c | 102 ++ tools/rkspi.c | 119 ++ 104 files changed, 11274 insertions(+), 25 deletions(-) create mode 100644 arch/arm/dts/cros-ec-sbs.dtsi create mode 100644 arch/arm/dts/rk3288-firefly.dts create mode 100644 arch/arm/dts/rk3288-firefly.dtsi create mode 100644 arch/arm/dts/rk3288-jerry.dts create mode 100644 arch/arm/dts/rk3288-thermal.dtsi create mode 100644 arch/arm/dts/rk3288-veyron-chromebook.dtsi create mode 100644 arch/arm/dts/rk3288-veyron.dtsi create mode 100644 arch/arm/dts/rk3288.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/clock.h create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/gpio.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/hardware.h create mode 100644 arch/arm/include/asm/arch-rockchip/i2c.h create mode 100644 arch/arm/include/asm/arch-rockchip/periph.h create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/sdram.h create mode 100644 arch/arm/mach-rockchip/Kconfig create mode 100644 arch/arm/mach-rockchip/Makefile create mode 100644 arch/arm/mach-rockchip/board-spl.c create mode 100644 arch/arm/mach-rockchip/board.c create mode 100644 arch/arm/mach-rockchip/common.c create mode 100644 arch/arm/mach-rockchip/rk3288/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3288/Makefile create mode 100644 arch/arm/mach-rockchip/rk3288/reset_rk3288.c create mode 100644 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c create mode 100644 arch/arm/mach-rockchip/rk3288/syscon_rk3288.c create mode 100644 board/firefly/firefly-rk3288/Kconfig create mode 100644 board/firefly/firefly-rk3288/MAINTAINERS create mode 100644 board/firefly/firefly-rk3288/Makefile create mode 100644 board/firefly/firefly-rk3288/firefly-rk3288.c create mode 100644 board/google/chromebook_jerry/Kconfig create mode 100644 board/google/chromebook_jerry/MAINTAINERS create mode 100644 board/google/chromebook_jerry/Makefile create mode 100644 board/google/chromebook_jerry/jerry.c create mode 100644 configs/chromebook_jerry_defconfig create mode 100644 configs/firefly-rk3288_defconfig create mode 100644 doc/README.rockchip create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txt create mode 100644 doc/device-tree-bindings/clock/rockchip.txt create mode 100644 doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt create mode 100644 doc/device-tree-bindings/thermal/rockchip-thermal.txt create mode 100644 drivers/clk/clk_rk3288.c create mode 100644 drivers/gpio/rk_gpio.c create mode 100644 drivers/i2c/rk_i2c.c create mode 100644 drivers/mmc/rockchip_mmc.c create mode 100644 drivers/pinctrl/rockchip/Makefile create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3288.c create mode 100644 drivers/power/pmic/act8846.c create mode 100644 drivers/power/regulator/act8846.c create mode 100644 drivers/serial/serial_rockchip.c create mode 100644 drivers/spi/rk_spi.c create mode 100644 drivers/spi/rk_spi.h create mode 100644 include/configs/chromebook_jerry.h create mode 100644 include/configs/firefly-rk3288.h create mode 100644 include/configs/rk3288_common.h create mode 100644 include/dt-bindings/clock/rk3288-cru.h create mode 100644 include/dt-bindings/clock/rockchip,rk808.h create mode 100644 include/dt-bindings/pinctrl/rockchip.h create mode 100644 include/dt-bindings/power-domain/rk3288.h create mode 100644 include/power/act8846_pmic.h create mode 100644 tools/rkcommon.c create mode 100644 tools/rkcommon.h create mode 100644 tools/rkimage.c create mode 100644 tools/rksd.c create mode 100644 tools/rkspi.c
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 1/33 pinctrl: Correct build errors in the pinctrl_simple
There are a few minor tweaks needed to get this to build. Add them so that the simple pinctrl implementation can be used.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/pinctrl/pinctrl-uclass.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
drivers/pinctrl/pinctrl-uclass.c +4 -4
@@ -6,21 +6,21 @@#include <common.h> #include <libfdt.h> -#include <linux/err.h> -#include <linux/list.h> #include <dm/device.h> #include <dm/lists.h> #include <dm/pinctrl.h> #include <dm/uclass.h> +#include <linux/err.h> +#include <linux/list.h> DECLARE_GLOBAL_DATA_PTR ;#if CONFIG_IS_ENABLED (PINCTRL_SIMPLE ) -static int pinctrl_select_state (struct udevice *dev,const char *ignored) +int pinctrl_select_state (struct udevice *dev,const char *ignored) {struct udevice *pctldev; -struct pinconf_ops *ops; +const struct pinctrl_ops *ops;int ret; ret =uclass_get_device (UCLASS_PINCTRL ,0 , &pctldev);
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 1/33 pinctrl: Correct build errors in the pinctrl_simple
+Masahiro
Quoted 46 lines · Simon Glass
There are a few minor tweaks needed to get this to build. Add them so that the simple pinctrl implementation can be used.
Signed-off-by Simon Glass <[email protected]>---
Changes in v4: None
Changes in v3: None
Changes in v2: Nonedrivers/pinctrl/pinctrl-uclass.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)drivers/pinctrl/pinctrl-uclass.c +4
-5@@ -6,21 +6,21 @@#include <common.h> #include <libfdt.h> -#include <linux/err.h> -#include <linux/list.h> #include <dm/device.h> #include <dm/lists.h> #include <dm/pinctrl.h> #include <dm/uclass.h> +#include <linux/err.h> +#include <linux/list.h> DECLARE_GLOBAL_DATA_PTR ;#if CONFIG_IS_ENABLED (PINCTRL_SIMPLE ) -static int pinctrl_select_state (struct udevice *dev,const char *ignored) +int pinctrl_select_state (struct udevice *dev,const char *ignored) {struct udevice *pctldev; -struct pinconf_ops *ops; +const struct pinctrl_ops *ops;int ret; ret =uclass_get_device (UCLASS_PINCTRL ,0 , &pctldev); --2.5.0.457.gab17608
PATCH v4 1/33 pinctrl: Correct build errors in the pinctrl_simple
2015-08-25 0:31 GMT+09:00 Simon Glass <[email protected]>:
Quoted 46 lines
+Masahiro
Quoted 42 lines · Simon Glass
There are a few minor tweaks needed to get this to build. Add them so that the simple pinctrl implementation can be used.
Signed-off-by Simon Glass <[email protected]>---
Changes in v4: None
Changes in v3: None
Changes in v2: Nonedrivers/pinctrl/pinctrl-uclass.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)drivers/pinctrl/pinctrl-uclass.c +4
-4@@ -6,21 +6,21 @@#include <common.h> #include <libfdt.h> -#include <linux/err.h> -#include <linux/list.h> #include <dm/device.h> #include <dm/lists.h> #include <dm/pinctrl.h> #include <dm/uclass.h> +#include <linux/err.h> +#include <linux/list.h> DECLARE_GLOBAL_DATA_PTR ;#if CONFIG_IS_ENABLED (PINCTRL_SIMPLE ) -static int pinctrl_select_state (struct udevice *dev,const char *ignored) +int pinctrl_select_state (struct udevice *dev,const char *ignored) {struct udevice *pctldev; -struct pinconf_ops *ops; +const struct pinctrl_ops *ops;int ret;
Quoted 1 line
drivers/pinctrl/pinctrl-uclass.c line 26
Quoted 1 line
drivers/pinctrl/pinctrl-uclass.c +0
-0ret =uclass_get_device (UCLASS_PINCTRL ,0 , &pctldev);
This was fixed in my v4.
You can drop this unless you want to sort includes. (although I am not a fan of putting <linux/*> at the bottom)
Signature · 2 lines
Best Regards Masahiro Yamada
PATCH v4 2/33 pinctrl: Add help text to Kconfig
In reply to Simon GlassThe pinctrl Kconfig options should have help messages. Add this to a few options.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/pinctrl/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+)
drivers/pinctrl/Kconfig +13 -0
@@ -18,6 +18,12 @@ config PINCTRL_GENERIC config PINMUX bool "Support pin multiplexing controllers" depends on PINCTRL_GENERIC + help + Support pin multiplexing control in U-Boot. Most SoCs have their own + own multiplexing arrangement where a single pin can be used for + several functions. An SoC pinctrl driver allows the required + function to be selected for each pin. The driver is typically + controlled by the device tree. config PINCONF bool "Support pin configuration controllers"
@@ -38,6 +44,13 @@ config SPL_PINCTRL_GENERIC config SPL_PINMUX bool "Support pin multiplexing controllers in SPL" depends on SPL_PINCTRL_GENERIC + help + The pinctrl subsystem can add a substantial overhead to the SPL + image since it typically requires quite a few tables either in the + driver or in the device tree. If this is acceptable and you need + to adjust pin multiplexing in SPL in order to boot into U-Boot, + enable this option. You will need to enable device tree in SPL + for this to work. config SPL_PINCONF bool "Support pin configuration controllers in SPL"
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 3/33 pinctrl: Add the concept of peripheral IDs
In reply to Simon GlassMy original pinctrl patch operating using a peripheral ID enum. This was shared between pinmux and clock and provides an easy way to specify a device that needs to be controlled, even it is does not (yet) have a driver within driver model.
Masahiro's new simple pinctrl gets around this by providing a set_state_simple() pinctrl method. By passing a device to that call the peripheral ID becomes unnecessary. If the driver needs it, it can calculate it itself and use it internally.
However this does not solve the problem for peripheral clocks. The 'pure' solution would be to pass a driver to the clock uclass also. But this requires that all devices should have a driver, and a struct udevide. Also a key optimisation of the clock uclass is allowing a peripheral clock to be set even when there is no device for that clock.
There may be a better way to achive the same goal, but for now it seems expedient to add in peripheral ID to the pinctrl uclass. Two methods are added - one to get the peripheral ID and one to select it. The existing set_state_simple() is effectively the union of these.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/pinctrl/pinctrl-uclass.c | 33 ++++++++++++++++++++++ include/dm/pinctrl.h | 61 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+)
drivers/pinctrl/pinctrl-uclass.c +33 -0
@@ -9,6 +9,7 @@#include <dm/device.h> #include <dm/lists.h> #include <dm/pinctrl.h> +#include <dm/root.h> #include <dm/uclass.h> #include <linux/err.h> #include <linux/list.h>
@@ -36,9 +37,41 @@ int pinctrl_select_state(struct udevice *dev, const char *ignored)return ops->set_state_simple (pctldev, dev); } +int pinctrl_request (struct udevice *dev,int func,int flags) +{ +struct pinctrl_ops *ops =pinctrl_get_ops (dev); + +if (!ops->request) +return -ENOSYS ; + +return ops->request (dev, func, flags); +} + +int pinctrl_request_noflags (struct udevice *dev,int func) +{ +return pinctrl_request (dev, func,0 ); +} + +int pinctrl_get_periph_id (struct udevice *dev,struct udevice *periph) +{ +struct pinctrl_ops *ops =pinctrl_get_ops (dev); + +if (!ops->get_periph_id) +return -ENOSYS ; + +return ops->get_periph_id (dev, periph); +} + +static int pinctrl_post_bind (struct udevice *dev) +{ +/* Scan the bus for devices */ +return dm_scan_fdt_node (dev, gd->fdt_blob, dev->of_offset, false); +} +UCLASS_DRIVER (pinctrl) = { .id =UCLASS_PINCTRL , .name ="pinctrl" , + .post_bind = pinctrl_post_bind, };#else
include/dm/pinctrl.h +61 -0
75 lines not on this page · raw message
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 3/33 pinctrl: Add the concept of peripheral IDs
Hi Simon,
2015-08-25 0:12 GMT+09:00 Simon Glass <[email protected]>:
Quoted 62 lines
My original pinctrl patch operating using a peripheral ID enum. This was shared between pinmux and clock and provides an easy way to specify a device that needs to be controlled, even it is does not (yet) have a driver within driver model.
Masahiro's new simple pinctrl gets around this by providing a
set_state_simple()pinctrl method. By passing a device to that call the peripheral ID becomes unnecessary. If the driver needs it, it can calculate it itself and use it internally.However this does not solve the problem for peripheral clocks. The 'pure' solution would be to pass a driver to the clock uclass also. But this requires that all devices should have a driver, and a struct udevide. Also a key optimisation of the clock uclass is allowing a peripheral clock to be set even when there is no device for that clock.
There may be a better way to achive the same goal, but for now it seems expedient to add in peripheral ID to the pinctrl uclass. Two methods are added - one to get the peripheral ID and one to select it. The existing
set_state_simple()is effectively the union of these.Signed-off-by Simon Glass <[email protected]>---
Changes in v4: None
Changes in v3: None
Changes in v2: Nonedrivers/pinctrl/pinctrl-uclass.c | 33 ++++++++++++++++++++++ include/dm/pinctrl.h | 61 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+)drivers/pinctrl/pinctrl-uclass.c +15
-0@@ -9,6 +9,7 @@#include <dm/device.h> #include <dm/lists.h> #include <dm/pinctrl.h> +#include <dm/root.h> #include <dm/uclass.h> #include <linux/err.h> #include <linux/list.h> @@ -36,9 +37,41 @@ int pinctrl_select_state(struct udevice *dev, const char *ignored)return ops->set_state_simple (pctldev, dev); } +int pinctrl_request (struct udevice *dev,int func,int flags) +{ +struct pinctrl_ops *ops =pinctrl_get_ops (dev); + +if (!ops->request) +return -ENOSYS ; + +return ops->request (dev, func, flags); +} + +int pinctrl_request_noflags (struct udevice *dev,int func) +{ +return pinctrl_request (dev, func,0 ); +}
drivers/pinctrl/pinctrl-uclass.c int pinctrl_select_state(struct udevice *dev, const char *ignored) · line 63
Quoted 10 lines
drivers/pinctrl/pinctrl-uclass.c +10
-0+ +int pinctrl_get_periph_id (struct udevice *dev,struct udevice *periph) +{ +struct pinctrl_ops *ops =pinctrl_get_ops (dev); + +if (!ops->get_periph_id) +return -ENOSYS ; + +return ops->get_periph_id (dev, periph); +}
If _get_periph_id() is shared between clk and pinctrl (that what I understood
from your statement), where is it defined? Under arch/arm/mach-<soc>/ ?
drivers/pinctrl/pinctrl-uclass.c int pinctrl_select_state(struct udevice *dev, const char *ignored) · line 69
Quoted 5 lines
drivers/pinctrl/pinctrl-uclass.c +5
-0+static int pinctrl_post_bind (struct udevice *dev) +{ +/* Scan the bus for devices */ +return dm_scan_fdt_node (dev, gd->fdt_blob, dev->of_offset, false); +}
I do not think this work.
dm_scan_fdt_node() requires child nodes to be compatible to something for binding.
Pin configuration nodes do not have '.compatible' properties.
Quoted 78 lines
drivers/pinctrl/pinctrl-uclass.c +1
-0UCLASS_DRIVER (pinctrl) = { .id =UCLASS_PINCTRL , .name ="pinctrl" , + .post_bind = pinctrl_post_bind, };#else include/dm/pinctrl.h +52
-0@@ -85,10 +85,37 @@ struct pinctrl_ops {int (*pinconf_group_set)(struct udevice *dev,unsigned group_selector,unsigned param,unsigned argument);int (*set_state)(struct udevice *dev,struct udevice *config); +/* for pinctrl-simple */ int (*set_state_simple)(struct udevice *dev,struct udevice *periph); +/** +* request() - Request a particular pinctrl function +* +* This activates the selected function. +* +* @dev: Device to adjust (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @return 0 if OK, -ve on error +*/ +int (*request)(struct udevice *dev,int func,int flags); + +/** +* get_periph_id() - get the peripheral ID for a device +* +* This generally looks at the peripheral's device tree node to work +* out the peripheral ID. The return value is normally interpreted as +* enum periph_id. so long as this is defined by the platform (which it +* should be). +* +* @dev: Pinctrl device to use for decoding +* @periph: Device to check +* @return peripheral ID of @periph, or -ENOENT on error +*/ +int (*get_periph_id)(struct udevice *dev,struct udevice *periph); }; +#define pinctrl_get_ops (dev) ((struct pinctrl_ops *)(dev)->driver->ops) +/** * Generic pin configuration paramters * @@ -217,4 +244,38 @@ static inline int pinctrl_generic_set_state(struct udevice *pctldev, }#endif +/** +* pinctrl_request() - Request a particular pinctrl function +* +* @dev: Device to check (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @flags: Flags (driver-specific) +* @return 0 if OK, -ve on error +*/ +int pinctrl_request (struct udevice *dev,int func,int flags); + +/** +* pinctrl_request_noflags() - Request a particular pinctrl function +* +* This is similar to pinctrl_request() but uses 0 for @flags. +* +* @dev: Device to check (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @return 0 if OK, -ve on error +*/ +int pinctrl_request_noflags (struct udevice *dev,int func); + +/** +* pinctrl_get_periph_id() - get the peripheral ID for a device +* +* This generally looks at the peripheral's device tree node to work out the
include/dm/pinctrl.h static inline int pinctrl_generic_set_state(struct udevice *pctldev, · line 281
Quoted 10 lines
include/dm/pinctrl.h +9
-0+* peripheral ID. The return value is normally interpreted as enum periph_id. +* so long as this is defined by the platform (which it should be). +* +* @dev: Pinctrl device to use for decoding +* @periph: Device to check +* @return peripheral ID of @periph, or -ENOENT on error +*/ +int pinctrl_get_periph_id (struct udevice *dev,struct udevice *periph); +#endif /* __PINCTRL_H */
I am guessing these functions are only invoked from .set_state_simple(), If so, should they be exported to struct pinctrl_ops?
I expect callbacks are invoked from the core framework (uclass).
Signature · 2 lines
Best Regards Masahiro Yamada
PATCH v4 3/33 pinctrl: Add the concept of peripheral IDs
Hi Masahiro,
Quoted 73 lines · Masahiro Yamada
Hi Simon,
2015-08-25 0:12 GMT+09:00 Simon Glass <[email protected]>:
Quoted 68 lines
My original pinctrl patch operating using a peripheral ID enum. This was shared between pinmux and clock and provides an easy way to specify a device that needs to be controlled, even it is does not (yet) have a driver within driver model.
Masahiro's new simple pinctrl gets around this by providing a
set_state_simple()pinctrl method. By passing a device to that call the peripheral ID becomes unnecessary. If the driver needs it, it can calculate it itself and use it internally.However this does not solve the problem for peripheral clocks. The 'pure' solution would be to pass a driver to the clock uclass also. But this requires that all devices should have a driver, and a struct udevide. Also a key optimisation of the clock uclass is allowing a peripheral clock to be set even when there is no device for that clock.
There may be a better way to achive the same goal, but for now it seems expedient to add in peripheral ID to the pinctrl uclass. Two methods are added - one to get the peripheral ID and one to select it. The existing
set_state_simple()is effectively the union of these.Signed-off-by Simon Glass <[email protected]>---
Changes in v4: None
Changes in v3: None
Changes in v2: Nonedrivers/pinctrl/pinctrl-uclass.c | 33 ++++++++++++++++++++++ include/dm/pinctrl.h | 61 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+)drivers/pinctrl/pinctrl-uclass.c +21
-0@@ -9,6 +9,7 @@#include <dm/device.h> #include <dm/lists.h> #include <dm/pinctrl.h> +#include <dm/root.h> #include <dm/uclass.h> #include <linux/err.h> #include <linux/list.h> @@ -36,9 +37,41 @@ int pinctrl_select_state(struct udevice *dev, const char *ignored)return ops->set_state_simple (pctldev, dev); } +int pinctrl_request (struct udevice *dev,int func,int flags) +{ +struct pinctrl_ops *ops =pinctrl_get_ops (dev); + +if (!ops->request) +return -ENOSYS ; + +return ops->request (dev, func, flags); +} + +int pinctrl_request_noflags (struct udevice *dev,int func) +{ +return pinctrl_request (dev, func,0 ); +} + +int pinctrl_get_periph_id (struct udevice *dev,struct udevice *periph) +{ +struct pinctrl_ops *ops =pinctrl_get_ops (dev); + +if (!ops->get_periph_id)
Quoted 8 lines
drivers/pinctrl/pinctrl-uclass.c int pinctrl_select_state(struct udevice *dev, const char *ignored) · line 63
Quoted 4 lines
drivers/pinctrl/pinctrl-uclass.c +4
-0+return -ENOSYS ; + +return ops->get_periph_id (dev, periph); +}If
_get_periph_id()is shared between clk and pinctrl (that what I understood
from your statement), where is it defined? Under arch/arm/mach-<soc>/ ?
Yes.
Quoted 13 lines
drivers/pinctrl/pinctrl-uclass.c int pinctrl_select_state(struct udevice *dev, const char *ignored) · line 69
Quoted 9 lines
drivers/pinctrl/pinctrl-uclass.c +5
-0+static int pinctrl_post_bind (struct udevice *dev) +{ +/* Scan the bus for devices */ +return dm_scan_fdt_node (dev, gd->fdt_blob, dev->of_offset, false); +}I do not think this work.
Quoted 4 lines
dm_scan_fdt_node()requires child nodes to be compatible to something for binding.Pin configuration nodes do not have '.compatible' properties.
True in many cases, in which case it does not harm, but Rockchip has them:
Quoted 99 lines
Quoted 83 lines
drivers/pinctrl/pinctrl-uclass.c +1
-0UCLASS_DRIVER (pinctrl) = { .id =UCLASS_PINCTRL , .name ="pinctrl" , + .post_bind = pinctrl_post_bind, };#else include/dm/pinctrl.h +52
-0@@ -85,10 +85,37 @@ struct pinctrl_ops {int (*pinconf_group_set)(struct udevice *dev,unsigned group_selector,unsigned param,unsigned argument);int (*set_state)(struct udevice *dev,struct udevice *config); +/* for pinctrl-simple */ int (*set_state_simple)(struct udevice *dev,struct udevice *periph); +/** +* request() - Request a particular pinctrl function +* +* This activates the selected function. +* +* @dev: Device to adjust (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @return 0 if OK, -ve on error +*/ +int (*request)(struct udevice *dev,int func,int flags); + +/** +* get_periph_id() - get the peripheral ID for a device +* +* This generally looks at the peripheral's device tree node to work +* out the peripheral ID. The return value is normally interpreted as +* enum periph_id. so long as this is defined by the platform (which it +* should be). +* +* @dev: Pinctrl device to use for decoding +* @periph: Device to check +* @return peripheral ID of @periph, or -ENOENT on error +*/ +int (*get_periph_id)(struct udevice *dev,struct udevice *periph); }; +#define pinctrl_get_ops (dev) ((struct pinctrl_ops *)(dev)->driver->ops) +/** * Generic pin configuration paramters * @@ -217,4 +244,38 @@ static inline int pinctrl_generic_set_state(struct udevice *pctldev, }#endif +/** +* pinctrl_request() - Request a particular pinctrl function +* +* @dev: Device to check (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @flags: Flags (driver-specific) +* @return 0 if OK, -ve on error +*/ +int pinctrl_request (struct udevice *dev,int func,int flags); + +/** +* pinctrl_request_noflags() - Request a particular pinctrl function +* +* This is similar to pinctrl_request() but uses 0 for @flags. +* +* @dev: Device to check (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @return 0 if OK, -ve on error +*/ +int pinctrl_request_noflags (struct udevice *dev,int func); + +/** +* pinctrl_get_periph_id() - get the peripheral ID for a device +* +* This generally looks at the peripheral's device tree node to work out the include/dm/pinctrl.h static inline int pinctrl_generic_set_state(struct udevice *pctldev, · line 281
Quoted 10 lines
include/dm/pinctrl.h +9
-0+* peripheral ID. The return value is normally interpreted as enum periph_id. +* so long as this is defined by the platform (which it should be). +* +* @dev: Pinctrl device to use for decoding +* @periph: Device to check +* @return peripheral ID of @periph, or -ENOENT on error +*/ +int pinctrl_get_periph_id (struct udevice *dev,struct udevice *periph); +#endif /* __PINCTRL_H */ I am guessing these functions are only invoked from .set_state_simple(), If so, should they be exported to struct
pinctrl_ops?
Quoted 2 lines
I expect callbacks are invoked from the core framework (uclass).
They can be involved from other places. In particular you need to call get_periph_id() to get the peripheral ID for use with clocks.
Regards,
Simon
PATCH v4 3/33 pinctrl: Add the concept of peripheral IDs
2015-08-26 13:38 GMT+09:00 Simon Glass <[email protected]>:
Quoted 101 lines
Hi Masahiro,
Quoted 73 lines · Masahiro Yamada
Hi Simon,
2015-08-25 0:12 GMT+09:00 Simon Glass <[email protected]>:
Quoted 68 lines
My original pinctrl patch operating using a peripheral ID enum. This was shared between pinmux and clock and provides an easy way to specify a device that needs to be controlled, even it is does not (yet) have a driver within driver model.
Masahiro's new simple pinctrl gets around this by providing a
set_state_simple()pinctrl method. By passing a device to that call the peripheral ID becomes unnecessary. If the driver needs it, it can calculate it itself and use it internally.However this does not solve the problem for peripheral clocks. The 'pure' solution would be to pass a driver to the clock uclass also. But this requires that all devices should have a driver, and a struct udevide. Also a key optimisation of the clock uclass is allowing a peripheral clock to be set even when there is no device for that clock.
There may be a better way to achive the same goal, but for now it seems expedient to add in peripheral ID to the pinctrl uclass. Two methods are added - one to get the peripheral ID and one to select it. The existing
set_state_simple()is effectively the union of these.Signed-off-by Simon Glass <[email protected]>---
Changes in v4: None
Changes in v3: None
Changes in v2: Nonedrivers/pinctrl/pinctrl-uclass.c | 33 ++++++++++++++++++++++ include/dm/pinctrl.h | 61 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+)drivers/pinctrl/pinctrl-uclass.c +21
-0@@ -9,6 +9,7 @@#include <dm/device.h> #include <dm/lists.h> #include <dm/pinctrl.h> +#include <dm/root.h> #include <dm/uclass.h> #include <linux/err.h> #include <linux/list.h> @@ -36,9 +37,41 @@ int pinctrl_select_state(struct udevice *dev, const char *ignored)return ops->set_state_simple (pctldev, dev); } +int pinctrl_request (struct udevice *dev,int func,int flags) +{ +struct pinctrl_ops *ops =pinctrl_get_ops (dev); + +if (!ops->request) +return -ENOSYS ; + +return ops->request (dev, func, flags); +} + +int pinctrl_request_noflags (struct udevice *dev,int func) +{ +return pinctrl_request (dev, func,0 ); +} + +int pinctrl_get_periph_id (struct udevice *dev,struct udevice *periph) +{ +struct pinctrl_ops *ops =pinctrl_get_ops (dev); + +if (!ops->get_periph_id)Quoted 8 lines
drivers/pinctrl/pinctrl-uclass.c int pinctrl_select_state(struct udevice *dev, const char *ignored) · line 63
Quoted 4 lines
drivers/pinctrl/pinctrl-uclass.c +4
-0+return -ENOSYS ; + +return ops->get_periph_id (dev, periph); +}If
_get_periph_id()is shared between clk and pinctrl (that what I understood
from your statement), where is it defined? Under arch/arm/mach-<soc>/ ?Yes.
Quoted 13 lines
drivers/pinctrl/pinctrl-uclass.c int pinctrl_select_state(struct udevice *dev, const char *ignored) · line 69
Quoted 9 lines
drivers/pinctrl/pinctrl-uclass.c +5
-0+static int pinctrl_post_bind (struct udevice *dev) +{ +/* Scan the bus for devices */ +return dm_scan_fdt_node (dev, gd->fdt_blob, dev->of_offset, false); +}I do not think this work.
Quoted 8 lines
Quoted 4 lines
dm_scan_fdt_node()requires child nodes to be compatible to something for binding.Pin configuration nodes do not have '.compatible' properties.
True in many cases, in which case it does not harm, but Rockchip has them:
My bad.
It is possible a pinctrl device can have other devices under it (in this case, GPIO).
So, it turned out my patch should be fixed. device_bind_driver_to_node() should be called for devices that have no .compatible.
Quoted 98 lines
Quoted 98 lines
Quoted 82 lines
drivers/pinctrl/pinctrl-uclass.c +1
-0UCLASS_DRIVER (pinctrl) = { .id =UCLASS_PINCTRL , .name ="pinctrl" , + .post_bind = pinctrl_post_bind, };#else include/dm/pinctrl.h +52
-0@@ -85,10 +85,37 @@ struct pinctrl_ops {int (*pinconf_group_set)(struct udevice *dev,unsigned group_selector,unsigned param,unsigned argument);int (*set_state)(struct udevice *dev,struct udevice *config); +/* for pinctrl-simple */ int (*set_state_simple)(struct udevice *dev,struct udevice *periph); +/** +* request() - Request a particular pinctrl function +* +* This activates the selected function. +* +* @dev: Device to adjust (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @return 0 if OK, -ve on error +*/ +int (*request)(struct udevice *dev,int func,int flags); + +/** +* get_periph_id() - get the peripheral ID for a device +* +* This generally looks at the peripheral's device tree node to work +* out the peripheral ID. The return value is normally interpreted as +* enum periph_id. so long as this is defined by the platform (which it +* should be). +* +* @dev: Pinctrl device to use for decoding +* @periph: Device to check +* @return peripheral ID of @periph, or -ENOENT on error +*/ +int (*get_periph_id)(struct udevice *dev,struct udevice *periph); }; +#define pinctrl_get_ops (dev) ((struct pinctrl_ops *)(dev)->driver->ops) +/** * Generic pin configuration paramters * @@ -217,4 +244,38 @@ static inline int pinctrl_generic_set_state(struct udevice *pctldev, }#endif +/** +* pinctrl_request() - Request a particular pinctrl function +* +* @dev: Device to check (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @flags: Flags (driver-specific) +* @return 0 if OK, -ve on error +*/ +int pinctrl_request (struct udevice *dev,int func,int flags); + +/** +* pinctrl_request_noflags() - Request a particular pinctrl function +* +* This is similar to pinctrl_request() but uses 0 for @flags. +* +* @dev: Device to check (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @return 0 if OK, -ve on error +*/ +int pinctrl_request_noflags (struct udevice *dev,int func); + +/** +* pinctrl_get_periph_id() - get the peripheral ID for a device +* +* This generally looks at the peripheral's device tree node to work out the include/dm/pinctrl.h static inline int pinctrl_generic_set_state(struct udevice *pctldev, · line 281
Quoted 10 lines
include/dm/pinctrl.h +9
-0+* peripheral ID. The return value is normally interpreted as enum periph_id. +* so long as this is defined by the platform (which it should be). +* +* @dev: Pinctrl device to use for decoding +* @periph: Device to check +* @return peripheral ID of @periph, or -ENOENT on error +*/ +int pinctrl_get_periph_id (struct udevice *dev,struct udevice *periph); +#endif /* __PINCTRL_H */ I am guessing these functions are only invoked from .set_state_simple(), If so, should they be exported to struct
pinctrl_ops?
Quoted 6 lines
Quoted 2 lines
I expect callbacks are invoked from the core framework (uclass).
They can be involved from other places. In particular you need to call
get_periph_id()to get the peripheral ID for use with clocks.
In the first place, pinctrl_get_periph_id() should not be defined in a pinctrl driver.
The first argument, pinctrl device, is not needed to calculate the peripheral ID,
and the actual definition is placed under mach-<soc>, right?
Signature · 2 lines
Best Regards Masahiro Yamada
PATCH v4 3/33 pinctrl: Add the concept of peripheral IDs
Hi Masahiro,
Quoted 112 lines · Masahiro Yamada
2015-08-26 13:38 GMT+09:00 Simon Glass <[email protected]>:
Quoted 101 lines
Hi Masahiro,
Quoted 73 lines · Masahiro Yamada
Hi Simon,
2015-08-25 0:12 GMT+09:00 Simon Glass <[email protected]>:
Quoted 68 lines
My original pinctrl patch operating using a peripheral ID enum. This was shared between pinmux and clock and provides an easy way to specify a device that needs to be controlled, even it is does not (yet) have a driver within driver model.
Masahiro's new simple pinctrl gets around this by providing a
set_state_simple()pinctrl method. By passing a device to that call the peripheral ID becomes unnecessary. If the driver needs it, it can calculate it itself and use it internally.However this does not solve the problem for peripheral clocks. The 'pure' solution would be to pass a driver to the clock uclass also. But this requires that all devices should have a driver, and a struct udevide. Also a key optimisation of the clock uclass is allowing a peripheral clock to be set even when there is no device for that clock.
There may be a better way to achive the same goal, but for now it seems expedient to add in peripheral ID to the pinctrl uclass. Two methods are added - one to get the peripheral ID and one to select it. The existing
set_state_simple()is effectively the union of these.Signed-off-by Simon Glass <[email protected]>---
Changes in v4: None
Changes in v3: None
Changes in v2: Nonedrivers/pinctrl/pinctrl-uclass.c | 33 ++++++++++++++++++++++ include/dm/pinctrl.h | 61 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+)drivers/pinctrl/pinctrl-uclass.c +21
-0@@ -9,6 +9,7 @@#include <dm/device.h> #include <dm/lists.h> #include <dm/pinctrl.h> +#include <dm/root.h> #include <dm/uclass.h> #include <linux/err.h> #include <linux/list.h> @@ -36,9 +37,41 @@ int pinctrl_select_state(struct udevice *dev, const char *ignored)return ops->set_state_simple (pctldev, dev); } +int pinctrl_request (struct udevice *dev,int func,int flags) +{ +struct pinctrl_ops *ops =pinctrl_get_ops (dev); + +if (!ops->request) +return -ENOSYS ; + +return ops->request (dev, func, flags); +} + +int pinctrl_request_noflags (struct udevice *dev,int func) +{ +return pinctrl_request (dev, func,0 ); +} + +int pinctrl_get_periph_id (struct udevice *dev,struct udevice *periph) +{ +struct pinctrl_ops *ops =pinctrl_get_ops (dev); + +if (!ops->get_periph_id)Quoted 8 lines
drivers/pinctrl/pinctrl-uclass.c int pinctrl_select_state(struct udevice *dev, const char *ignored) · line 63
Quoted 4 lines
drivers/pinctrl/pinctrl-uclass.c +4
-0+return -ENOSYS ; + +return ops->get_periph_id (dev, periph); +}If
_get_periph_id()is shared between clk and pinctrl (that what I understood
from your statement), where is it defined? Under arch/arm/mach-<soc>/ ?Yes.
Quoted 13 lines
drivers/pinctrl/pinctrl-uclass.c int pinctrl_select_state(struct udevice *dev, const char *ignored) · line 69
Quoted 9 lines
drivers/pinctrl/pinctrl-uclass.c +5
-0+static int pinctrl_post_bind (struct udevice *dev) +{ +/* Scan the bus for devices */ +return dm_scan_fdt_node (dev, gd->fdt_blob, dev->of_offset, false); +}I do not think this work.
Quoted 8 lines
Quoted 4 lines
dm_scan_fdt_node()requires child nodes to be compatible to something for binding.Pin configuration nodes do not have '.compatible' properties.
True in many cases, in which case it does not harm, but Rockchip has them:
Quoted 9 lines
My bad.
It is possible a pinctrl device can have other devices under it (in this case, GPIO).
So, it turned out my patch should be fixed.
device_bind_driver_to_node()should be called for devices that have no .compatible.
OK.
Quoted 110 lines
Quoted 102 lines
Quoted 102 lines
Quoted 86 lines
drivers/pinctrl/pinctrl-uclass.c +1
-0UCLASS_DRIVER (pinctrl) = { .id =UCLASS_PINCTRL , .name ="pinctrl" , + .post_bind = pinctrl_post_bind, };#else include/dm/pinctrl.h +52
-0@@ -85,10 +85,37 @@ struct pinctrl_ops {int (*pinconf_group_set)(struct udevice *dev,unsigned group_selector,unsigned param,unsigned argument);int (*set_state)(struct udevice *dev,struct udevice *config); +/* for pinctrl-simple */ int (*set_state_simple)(struct udevice *dev,struct udevice *periph); +/** +* request() - Request a particular pinctrl function +* +* This activates the selected function. +* +* @dev: Device to adjust (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @return 0 if OK, -ve on error +*/ +int (*request)(struct udevice *dev,int func,int flags); + +/** +* get_periph_id() - get the peripheral ID for a device +* +* This generally looks at the peripheral's device tree node to work +* out the peripheral ID. The return value is normally interpreted as +* enum periph_id. so long as this is defined by the platform (which it +* should be). +* +* @dev: Pinctrl device to use for decoding +* @periph: Device to check +* @return peripheral ID of @periph, or -ENOENT on error +*/ +int (*get_periph_id)(struct udevice *dev,struct udevice *periph); }; +#define pinctrl_get_ops (dev) ((struct pinctrl_ops *)(dev)->driver->ops) +/** * Generic pin configuration paramters * @@ -217,4 +244,38 @@ static inline int pinctrl_generic_set_state(struct udevice *pctldev, }#endif +/** +* pinctrl_request() - Request a particular pinctrl function +* +* @dev: Device to check (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @flags: Flags (driver-specific) +* @return 0 if OK, -ve on error +*/ +int pinctrl_request (struct udevice *dev,int func,int flags); + +/** +* pinctrl_request_noflags() - Request a particular pinctrl function +* +* This is similar to pinctrl_request() but uses 0 for @flags. +* +* @dev: Device to check (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @return 0 if OK, -ve on error +*/ +int pinctrl_request_noflags (struct udevice *dev,int func); + +/** +* pinctrl_get_periph_id() - get the peripheral ID for a device +* +* This generally looks at the peripheral's device tree node to work out the include/dm/pinctrl.h static inline int pinctrl_generic_set_state(struct udevice *pctldev, · line 281
Quoted 10 lines
include/dm/pinctrl.h +9
-0+* peripheral ID. The return value is normally interpreted as enum periph_id. +* so long as this is defined by the platform (which it should be). +* +* @dev: Pinctrl device to use for decoding +* @periph: Device to check +* @return peripheral ID of @periph, or -ENOENT on error +*/ +int pinctrl_get_periph_id (struct udevice *dev,struct udevice *periph); +#endif /* __PINCTRL_H */ I am guessing these functions are only invoked from .set_state_simple(), If so, should they be exported to struct
pinctrl_ops?Quoted 6 lines
Quoted 2 lines
I expect callbacks are invoked from the core framework (uclass).
They can be involved from other places. In particular you need to call
get_periph_id()to get the peripheral ID for use with clocks.
Quoted 6 lines
In the first place,
pinctrl_get_periph_id()should not be defined in a pinctrl driver.The first argument, pinctrl device, is not needed to calculate the peripheral ID,
and the actual definition is placed under mach-<soc>, right?
So are you suggesting that each SoC provides a function (not in the driver model framework) to get the peripheral ID in the simple pinctrl case? This might be similar to clock_decode_periph_id(const void *blob, int node) in tegra.
In fact if we implement a full clock controller binding (similar to how you have implemented pinctrl) then we can avoid the need for peripheral IDs once driver model is fully up. The need then exists only in SPL, due to code size/memory constraints. It may perhaps also be needed before relocation in U-Boot proper due to execution time constraints but we can limit the number of devices brought up using u-boot,dm-pre-reloc.
It would be good to limit the spread of the peripheral ID and only use it when needed.
I'll take a look at creating a function outside of pinctrl which returns a peripheral ID. That deals with the get_periph_id() method in pinctrl.
However this still leaves the request() method - which takes a peripheral ID. This is needed I think because:the device being set up might not have a udevice in SPL. What do you think?
Regards,
Simon
PATCH v4 3/33 pinctrl: Add the concept of peripheral IDs
2015-08-26 22:20 GMT+09:00 Simon Glass <[email protected]>:
Quoted 121 lines
Hi Masahiro,
Quoted 117 lines · Masahiro Yamada
2015-08-26 13:38 GMT+09:00 Simon Glass <[email protected]>:
Quoted 101 lines
Hi Masahiro,
Quoted 73 lines · Masahiro Yamada
Hi Simon,
2015-08-25 0:12 GMT+09:00 Simon Glass <[email protected]>:
Quoted 68 lines
My original pinctrl patch operating using a peripheral ID enum. This was shared between pinmux and clock and provides an easy way to specify a device that needs to be controlled, even it is does not (yet) have a driver within driver model.
Masahiro's new simple pinctrl gets around this by providing a
set_state_simple()pinctrl method. By passing a device to that call the peripheral ID becomes unnecessary. If the driver needs it, it can calculate it itself and use it internally.However this does not solve the problem for peripheral clocks. The 'pure' solution would be to pass a driver to the clock uclass also. But this requires that all devices should have a driver, and a struct udevide. Also a key optimisation of the clock uclass is allowing a peripheral clock to be set even when there is no device for that clock.
There may be a better way to achive the same goal, but for now it seems expedient to add in peripheral ID to the pinctrl uclass. Two methods are added - one to get the peripheral ID and one to select it. The existing
set_state_simple()is effectively the union of these.Signed-off-by Simon Glass <[email protected]>---
Changes in v4: None
Changes in v3: None
Changes in v2: Nonedrivers/pinctrl/pinctrl-uclass.c | 33 ++++++++++++++++++++++ include/dm/pinctrl.h | 61 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+)drivers/pinctrl/pinctrl-uclass.c +21
-0@@ -9,6 +9,7 @@#include <dm/device.h> #include <dm/lists.h> #include <dm/pinctrl.h> +#include <dm/root.h> #include <dm/uclass.h> #include <linux/err.h> #include <linux/list.h> @@ -36,9 +37,41 @@ int pinctrl_select_state(struct udevice *dev, const char *ignored)return ops->set_state_simple (pctldev, dev); } +int pinctrl_request (struct udevice *dev,int func,int flags) +{ +struct pinctrl_ops *ops =pinctrl_get_ops (dev); + +if (!ops->request) +return -ENOSYS ; + +return ops->request (dev, func, flags); +} + +int pinctrl_request_noflags (struct udevice *dev,int func) +{ +return pinctrl_request (dev, func,0 ); +} + +int pinctrl_get_periph_id (struct udevice *dev,struct udevice *periph) +{ +struct pinctrl_ops *ops =pinctrl_get_ops (dev); + +if (!ops->get_periph_id)Quoted 8 lines
drivers/pinctrl/pinctrl-uclass.c int pinctrl_select_state(struct udevice *dev, const char *ignored) · line 63
Quoted 4 lines
drivers/pinctrl/pinctrl-uclass.c +4
-0+return -ENOSYS ; + +return ops->get_periph_id (dev, periph); +}If
_get_periph_id()is shared between clk and pinctrl (that what I understood
from your statement), where is it defined? Under arch/arm/mach-<soc>/ ?Yes.
Quoted 13 lines
drivers/pinctrl/pinctrl-uclass.c int pinctrl_select_state(struct udevice *dev, const char *ignored) · line 69
Quoted 9 lines
drivers/pinctrl/pinctrl-uclass.c +5
-0+static int pinctrl_post_bind (struct udevice *dev) +{ +/* Scan the bus for devices */ +return dm_scan_fdt_node (dev, gd->fdt_blob, dev->of_offset, false); +}I do not think this work.
Quoted 8 lines
Quoted 4 lines
dm_scan_fdt_node()requires child nodes to be compatible to something for binding.Pin configuration nodes do not have '.compatible' properties.
True in many cases, in which case it does not harm, but Rockchip has them:
My bad.
It is possible a pinctrl device can have other devices under it (in this case, GPIO).
Quoted 6 lines
Quoted 4 lines
So, it turned out my patch should be fixed.
device_bind_driver_to_node()should be called for devices that have no .compatible.OK.
So, dm_scan_fdt_node() should be moved to rk3288_pinctrl_bind(), I think.
Having GPIO nodes under the pinctrl node is a rockchip-specific matter.
Quoted 112 lines
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Quoted 85 lines
drivers/pinctrl/pinctrl-uclass.c +1
-0UCLASS_DRIVER (pinctrl) = { .id =UCLASS_PINCTRL , .name ="pinctrl" , + .post_bind = pinctrl_post_bind, };#else include/dm/pinctrl.h +52
-0@@ -85,10 +85,37 @@ struct pinctrl_ops {int (*pinconf_group_set)(struct udevice *dev,unsigned group_selector,unsigned param,unsigned argument);int (*set_state)(struct udevice *dev,struct udevice *config); +/* for pinctrl-simple */ int (*set_state_simple)(struct udevice *dev,struct udevice *periph); +/** +* request() - Request a particular pinctrl function +* +* This activates the selected function. +* +* @dev: Device to adjust (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @return 0 if OK, -ve on error +*/ +int (*request)(struct udevice *dev,int func,int flags); + +/** +* get_periph_id() - get the peripheral ID for a device +* +* This generally looks at the peripheral's device tree node to work +* out the peripheral ID. The return value is normally interpreted as +* enum periph_id. so long as this is defined by the platform (which it +* should be). +* +* @dev: Pinctrl device to use for decoding +* @periph: Device to check +* @return peripheral ID of @periph, or -ENOENT on error +*/ +int (*get_periph_id)(struct udevice *dev,struct udevice *periph); }; +#define pinctrl_get_ops (dev) ((struct pinctrl_ops *)(dev)->driver->ops) +/** * Generic pin configuration paramters * @@ -217,4 +244,38 @@ static inline int pinctrl_generic_set_state(struct udevice *pctldev, }#endif +/** +* pinctrl_request() - Request a particular pinctrl function +* +* @dev: Device to check (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @flags: Flags (driver-specific) +* @return 0 if OK, -ve on error +*/ +int pinctrl_request (struct udevice *dev,int func,int flags); + +/** +* pinctrl_request_noflags() - Request a particular pinctrl function +* +* This is similar to pinctrl_request() but uses 0 for @flags. +* +* @dev: Device to check (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @return 0 if OK, -ve on error +*/ +int pinctrl_request_noflags (struct udevice *dev,int func); + +/** +* pinctrl_get_periph_id() - get the peripheral ID for a device +* +* This generally looks at the peripheral's device tree node to work out the include/dm/pinctrl.h static inline int pinctrl_generic_set_state(struct udevice *pctldev, · line 281
Quoted 10 lines
include/dm/pinctrl.h +9
-0+* peripheral ID. The return value is normally interpreted as enum periph_id. +* so long as this is defined by the platform (which it should be). +* +* @dev: Pinctrl device to use for decoding +* @periph: Device to check +* @return peripheral ID of @periph, or -ENOENT on error +*/ +int pinctrl_get_periph_id (struct udevice *dev,struct udevice *periph); +#endif /* __PINCTRL_H */ I am guessing these functions are only invoked from .set_state_simple(), If so, should they be exported to struct
pinctrl_ops?Quoted 6 lines
Quoted 2 lines
I expect callbacks are invoked from the core framework (uclass).
They can be involved from other places. In particular you need to call
get_periph_id()to get the peripheral ID for use with clocks.In the first place,
pinctrl_get_periph_id()should not be defined in a pinctrl driver.
Quoted 8 lines
Quoted 3 lines
The first argument, pinctrl device, is not needed to calculate the peripheral ID,
and the actual definition is placed under mach-<soc>, right?So are you suggesting that each SoC provides a function (not in the driver model framework) to get the peripheral ID in the simple pinctrl case? This might be similar to
clock_decode_periph_id(const void *blob, int node)in tegra.
Only for those SoCs that use pinctrl-simple and clk-simple.
Given that the peripheral ID is driver-wide concept that is shared between pinctrl-simple and clk-simple,
the ID decoder should be placed in common location, so that pinctrl-simple should not depends on clk-simple, and vice versa.
Quoted 25 lines
In fact if we implement a full clock controller binding (similar to how you have implemented pinctrl) then we can avoid the need for peripheral IDs once driver model is fully up. The need then exists only in SPL, due to code size/memory constraints. It may perhaps also be needed before relocation in U-Boot proper due to execution time constraints but we can limit the number of devices brought up using u-boot,dm-pre-reloc.
It would be good to limit the spread of the peripheral ID and only use it when needed.
I'll take a look at creating a function outside of pinctrl which returns a peripheral ID. That deals with the
get_periph_id()method in pinctrl.However this still leaves the
request()method - which takes a peripheral ID. This is needed I think because:the device being set up might not have a udevice in SPL. What do you think?Regards,
Simon
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Signature · 2 lines
Best Regards Masahiro Yamada
PATCH v4 3/33 pinctrl: Add the concept of peripheral IDs
Hi Masahiro,
Quoted 127 lines · Masahiro Yamada
2015-08-26 22:20 GMT+09:00 Simon Glass <[email protected]>:
Quoted 126 lines
Hi Masahiro,
Quoted 121 lines · Masahiro Yamada
2015-08-26 13:38 GMT+09:00 Simon Glass <[email protected]>:
Quoted 101 lines
Hi Masahiro,
Quoted 73 lines · Masahiro Yamada
Hi Simon,
2015-08-25 0:12 GMT+09:00 Simon Glass <[email protected]>:
Quoted 68 lines
My original pinctrl patch operating using a peripheral ID enum. This was shared between pinmux and clock and provides an easy way to specify a device that needs to be controlled, even it is does not (yet) have a driver within driver model.
Masahiro's new simple pinctrl gets around this by providing a
set_state_simple()pinctrl method. By passing a device to that call the peripheral ID becomes unnecessary. If the driver needs it, it can calculate it itself and use it internally.However this does not solve the problem for peripheral clocks. The 'pure' solution would be to pass a driver to the clock uclass also. But this requires that all devices should have a driver, and a struct udevide. Also a key optimisation of the clock uclass is allowing a peripheral clock to be set even when there is no device for that clock.
There may be a better way to achive the same goal, but for now it seems expedient to add in peripheral ID to the pinctrl uclass. Two methods are added - one to get the peripheral ID and one to select it. The existing
set_state_simple()is effectively the union of these.Signed-off-by Simon Glass <[email protected]>---
Changes in v4: None
Changes in v3: None
Changes in v2: Nonedrivers/pinctrl/pinctrl-uclass.c | 33 ++++++++++++++++++++++ include/dm/pinctrl.h | 61 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+)drivers/pinctrl/pinctrl-uclass.c +21
-0@@ -9,6 +9,7 @@#include <dm/device.h> #include <dm/lists.h> #include <dm/pinctrl.h> +#include <dm/root.h> #include <dm/uclass.h> #include <linux/err.h> #include <linux/list.h> @@ -36,9 +37,41 @@ int pinctrl_select_state(struct udevice *dev, const char *ignored)return ops->set_state_simple (pctldev, dev); } +int pinctrl_request (struct udevice *dev,int func,int flags) +{ +struct pinctrl_ops *ops =pinctrl_get_ops (dev); + +if (!ops->request) +return -ENOSYS ; + +return ops->request (dev, func, flags); +} + +int pinctrl_request_noflags (struct udevice *dev,int func) +{ +return pinctrl_request (dev, func,0 ); +} + +int pinctrl_get_periph_id (struct udevice *dev,struct udevice *periph) +{ +struct pinctrl_ops *ops =pinctrl_get_ops (dev); + +if (!ops->get_periph_id)Quoted 8 lines
drivers/pinctrl/pinctrl-uclass.c int pinctrl_select_state(struct udevice *dev, const char *ignored) · line 63
Quoted 4 lines
drivers/pinctrl/pinctrl-uclass.c +4
-0+return -ENOSYS ; + +return ops->get_periph_id (dev, periph); +}If
_get_periph_id()is shared between clk and pinctrl (that what I understood
from your statement), where is it defined? Under arch/arm/mach-<soc>/ ?Yes.
Quoted 13 lines
drivers/pinctrl/pinctrl-uclass.c int pinctrl_select_state(struct udevice *dev, const char *ignored) · line 69
Quoted 9 lines
drivers/pinctrl/pinctrl-uclass.c +5
-0+static int pinctrl_post_bind (struct udevice *dev) +{ +/* Scan the bus for devices */ +return dm_scan_fdt_node (dev, gd->fdt_blob, dev->of_offset, false); +}I do not think this work.
Quoted 8 lines
Quoted 4 lines
dm_scan_fdt_node()requires child nodes to be compatible to something for binding.Pin configuration nodes do not have '.compatible' properties.
True in many cases, in which case it does not harm, but Rockchip has them:
My bad.
It is possible a pinctrl device can have other devices under it (in this case, GPIO).
So, it turned out my patch should be fixed.
device_bind_driver_to_node()should be called for devices that have no .compatible.
Quoted 6 lines
Quoted 1 line
OK.
So,
dm_scan_fdt_node()should be moved tork3288_pinctrl_bind(), I think.Having GPIO nodes under the pinctrl node is a rockchip-specific matter.
Does it hurt to try to make it generic? Are you saying that is it wrong?
Quoted 115 lines
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Quoted 105 lines
Quoted 94 lines
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Quoted 78 lines
drivers/pinctrl/pinctrl-uclass.c +1
-0UCLASS_DRIVER (pinctrl) = { .id =UCLASS_PINCTRL , .name ="pinctrl" , + .post_bind = pinctrl_post_bind, };#else include/dm/pinctrl.h +52
-0@@ -85,10 +85,37 @@ struct pinctrl_ops {int (*pinconf_group_set)(struct udevice *dev,unsigned group_selector,unsigned param,unsigned argument);int (*set_state)(struct udevice *dev,struct udevice *config); +/* for pinctrl-simple */ int (*set_state_simple)(struct udevice *dev,struct udevice *periph); +/** +* request() - Request a particular pinctrl function +* +* This activates the selected function. +* +* @dev: Device to adjust (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @return 0 if OK, -ve on error +*/ +int (*request)(struct udevice *dev,int func,int flags); + +/** +* get_periph_id() - get the peripheral ID for a device +* +* This generally looks at the peripheral's device tree node to work +* out the peripheral ID. The return value is normally interpreted as +* enum periph_id. so long as this is defined by the platform (which it +* should be). +* +* @dev: Pinctrl device to use for decoding +* @periph: Device to check +* @return peripheral ID of @periph, or -ENOENT on error +*/ +int (*get_periph_id)(struct udevice *dev,struct udevice *periph); }; +#define pinctrl_get_ops (dev) ((struct pinctrl_ops *)(dev)->driver->ops) +/** * Generic pin configuration paramters * @@ -217,4 +244,38 @@ static inline int pinctrl_generic_set_state(struct udevice *pctldev, }#endif +/** +* pinctrl_request() - Request a particular pinctrl function +* +* @dev: Device to check (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @flags: Flags (driver-specific) +* @return 0 if OK, -ve on error +*/ +int pinctrl_request (struct udevice *dev,int func,int flags); + +/** +* pinctrl_request_noflags() - Request a particular pinctrl function +* +* This is similar to pinctrl_request() but uses 0 for @flags. +* +* @dev: Device to check (UCLASS_PINCTRL) +* @func: Function number (driver-specific) +* @return 0 if OK, -ve on error +*/ +int pinctrl_request_noflags (struct udevice *dev,int func); + +/** +* pinctrl_get_periph_id() - get the peripheral ID for a device +* +* This generally looks at the peripheral's device tree node to work out the include/dm/pinctrl.h static inline int pinctrl_generic_set_state(struct udevice *pctldev, · line 281
Quoted 10 lines
include/dm/pinctrl.h +9
-0+* peripheral ID. The return value is normally interpreted as enum periph_id. +* so long as this is defined by the platform (which it should be). +* +* @dev: Pinctrl device to use for decoding +* @periph: Device to check +* @return peripheral ID of @periph, or -ENOENT on error +*/ +int pinctrl_get_periph_id (struct udevice *dev,struct udevice *periph); +#endif /* __PINCTRL_H */ I am guessing these functions are only invoked from .set_state_simple(), If so, should they be exported to struct
pinctrl_ops?Quoted 6 lines
Quoted 2 lines
I expect callbacks are invoked from the core framework (uclass).
They can be involved from other places. In particular you need to call
get_periph_id()to get the peripheral ID for use with clocks.In the first place,
pinctrl_get_periph_id()should not be defined in a pinctrl driver.Quoted 8 lines
Quoted 3 lines
The first argument, pinctrl device, is not needed to calculate the peripheral ID,
and the actual definition is placed under mach-<soc>, right?So are you suggesting that each SoC provides a function (not in the driver model framework) to get the peripheral ID in the simple pinctrl case? This might be similar to
clock_decode_periph_id(const void *blob, int node)in tegra.
Quoted 7 lines
Only for those SoCs that use pinctrl-simple and clk-simple.
Given that the peripheral ID is driver-wide concept that is shared between pinctrl-simple and clk-simple,
the ID decoder should be placed in common location, so that pinctrl-simple should not depends on clk-simple, and vice versa.
Yes I agree.
However I have not got to this yet and time is marching on.
In order to support generic platforms we would need to be able to supply a conversion function for any SoC. I think the whole peripheral ID thing needs a bit of a closer look so I'd like to do that separately. I suspect there might be another way to achieve this.
Quoted 31 lines
Quoted 22 lines
In fact if we implement a full clock controller binding (similar to how you have implemented pinctrl) then we can avoid the need for peripheral IDs once driver model is fully up. The need then exists only in SPL, due to code size/memory constraints. It may perhaps also be needed before relocation in U-Boot proper due to execution time constraints but we can limit the number of devices brought up using u-boot,dm-pre-reloc.
It would be good to limit the spread of the peripheral ID and only use it when needed.
I'll take a look at creating a function outside of pinctrl which returns a peripheral ID. That deals with the
get_periph_id()method in pinctrl.However this still leaves the
request()method - which takes a peripheral ID. This is needed I think because:the device being set up might not have a udevice in SPL. What do you think?Quoted 6 lines
Regards,
Simon
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Quoted 3 lines
--
Best Regards
Masahiro Yamada
Regards,
Simon
PATCH v4 4/33 mmc: Support bypass mode with the get_mmc_clk() method
In reply to Simon GlassSome SoCs want to adjust the input clock to the DWMMC block as a way of controlling the MMC bus clock. Update the get_mmc_clk() method to support this.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/mmc/dw_mmc.c | 2 +- drivers/mmc/exynos_dw_mmc.c | 2 +- include/dwmmc.h | 16 +++++++++++++++- 3 files changed, 17 insertions(+), 3 deletions(-)
drivers/mmc/dw_mmc.c +1 -1
@@ -266,7 +266,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)* host->bus_hz should be set by user. */ if (host->get_mmc_clk) - sclk = host->get_mmc_clk (host); + sclk = host->get_mmc_clk (host, freq);else if (host->bus_hz) sclk = host->bus_hz;else {
drivers/mmc/exynos_dw_mmc.c +1 -1
@@ -39,7 +39,7 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)dwmci_writel (host,DWMCI_CLKSEL , priv->sdr_timing); } -unsigned int exynos_dwmci_get_clk (struct dwmci_host *host) +unsigned int exynos_dwmci_get_clk (struct dwmci_host *host,uint freq) {unsigned long sclk;int8_t clk_div;
include/dwmmc.h +15 -1
@@ -163,7 +163,21 @@ struct dwmci_host {void (*clksel)(struct dwmci_host *host);void (*board_init)(struct dwmci_host *host); -unsigned int (*get_mmc_clk)(struct dwmci_host *host); + +/** +* Get / set a particular MMC clock frequency +* +* This is used to request the current clock frequency of the clock +* that drives the DWMMC peripheral. The caller will then use this +* information to work out the divider it needs to achieve the +* required MMC bus clock frequency. If you want to handle the +* clock external to DWMMC, use @freq to select the frequency and +* return that value too. Then DWMMC will put itself in bypass mode. +* +* @host: DWMMC host +* @freq: Frequency the host is trying to achieve +*/ +unsigned int (*get_mmc_clk)(struct dwmci_host *host,uint freq);struct mmc_config cfg; };
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 4/33 mmc: Support bypass mode with the get_mmc_clk() method
Hi, Simon.
Best Regards,
Jaehoon Chung
Quoted 70 lines · Simon Glass
Some SoCs want to adjust the input clock to the DWMMC block as a way of controlling the MMC bus clock. Update the
get_mmc_clk()method to support this.Signed-off-by Simon Glass <[email protected]>---
Changes in v4: None
Changes in v3: None
Changes in v2: Nonedrivers/mmc/dw_mmc.c | 2 +- drivers/mmc/exynos_dw_mmc.c | 2 +- include/dwmmc.h | 16 +++++++++++++++- 3 files changed, 17 insertions(+), 3 deletions(-)drivers/mmc/dw_mmc.c +1
-1@@ -266,7 +266,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)* host->bus_hz should be set by user. */ if (host->get_mmc_clk) - sclk = host->get_mmc_clk (host); + sclk = host->get_mmc_clk (host, freq);else if (host->bus_hz) sclk = host->bus_hz;else {drivers/mmc/exynos_dw_mmc.c +1
-1@@ -39,7 +39,7 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)dwmci_writel (host,DWMCI_CLKSEL , priv->sdr_timing); } -unsigned int exynos_dwmci_get_clk (struct dwmci_host *host) +unsigned int exynos_dwmci_get_clk (struct dwmci_host *host,uint freq) {unsigned long sclk;int8_t clk_div;include/dwmmc.h +15
-1@@ -163,7 +163,21 @@ struct dwmci_host {void (*clksel)(struct dwmci_host *host);void (*board_init)(struct dwmci_host *host); -unsigned int (*get_mmc_clk)(struct dwmci_host *host); + +/** +* Get / set a particular MMC clock frequency +* +* This is used to request the current clock frequency of the clock +* that drives the DWMMC peripheral. The caller will then use this +* information to work out the divider it needs to achieve the +* required MMC bus clock frequency. If you want to handle the +* clock external to DWMMC, use @freq to select the frequency and +* return that value too. Then DWMMC will put itself in bypass mode. +* +* @host: DWMMC host +* @freq: Frequency the host is trying to achieve +*/ +unsigned int (*get_mmc_clk)(struct dwmci_host *host,uint freq);struct mmc_config cfg; };
PATCH v4 5/33 dm: do not return pointer if NULL is given to devp of device_bind()
In reply to Simon GlassFrom: Masahiro Yamada <[email protected]>
This is useful when we want to bind a device, but do not need the device pointer.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/core/device.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
drivers/core/device.c +4 -2
@@ -33,7 +33,8 @@ int device_bind(struct udevice *parent, const struct driver *drv,struct uclass *uc;int size, ret =0 ; - *devp =NULL ; +if (devp) + *devp =NULL ;if (!name)return -EINVAL ;
@@ -134,7 +135,8 @@ int device_bind(struct udevice *parent, const struct driver *drv,if (parent)dm_dbg ("Bound device %s to %s\n" , dev->name, parent->name); - *devp = dev; +if (devp) + *devp = dev; dev->flags |=DM_FLAG_BOUND ;
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 6/33 dm: Improve handling of a missing uclass
In reply to Simon GlassWhen a uclass definition is missing, no drivers in that uclass can operate. This can happen if a board has a strange collection of options (e.g. the driver is enabled but the uclass is not).
Unfortunately this is very confusing at present. Starting up driver model results in a -ENOENT error, which is pretty generic. Quite a big of digging is needed to get to the root cause.
To help with this, change the error to a very strange one with no other users in U-Boot. Also add a debug message.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/core/device.c | 4 +++- drivers/core/uclass.c | 7 ++++++- 2 files changed, 9 insertions(+), 2 deletions(-)
drivers/core/device.c +3 -1
@@ -39,8 +39,10 @@ int device_bind(struct udevice *parent, const struct driver *drv,return -EINVAL ; ret =uclass_get (drv->id, &uc); -if (ret) +if (ret) { +debug ("Missing uclass for driver %s\n" , drv->name);return ret; + } dev =calloc (1 ,sizeof (struct udevice ));if (!dev)
drivers/core/uclass.c +6 -1
@@ -58,7 +58,12 @@ static int uclass_add(enum uclass_id id, struct uclass **ucp)if (!uc_drv) {debug ("Cannot find uclass for id %d: please add the UCLASS_DRIVER() declaration for this UCLASS_... id\n" , id); -return -ENOENT ; +/* +* Use a strange error to make this case easier to find. When +* a uclass is not available it can prevent driver model from +* starting up and this failure is otherwise hard to debug. +*/ +return -EPFNOSUPPORT ; } uc =calloc (1 ,sizeof (*uc));if (!uc)
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 7/33 dm: Provide better debugging when a device fails to bind
In reply to Simon GlassAll devices should bind without error. But when they don't, they can cause driver model init to fail. A real situation where this can happen is when there is a missing uclass.
Add a debug() call to dm_scan_fdt_node to make this easier to track.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/core/root.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
drivers/core/root.c +4 -1
@@ -162,8 +162,11 @@ int dm_scan_fdt_node(struct udevice *parent, const void *blob, int offset,continue ; } err =lists_bind_fdt (parent, blob, offset,NULL ); -if (err && !ret) +if (err && !ret) { ret = err; +debug ("%s: ret=%d\n" ,fdt_get_name (blob, offset,NULL ), + ret); + } }if (ret)
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 8/33 arm: reset: Avoid a build error when the reset uclass is enabled
In reply to Simon GlassThere can be only one do_reset(). When CONFIG_RESET is enabled this is provided by the reset uclass, and ARM's version should be disabled.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/lib/Makefile | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/lib/Makefile +2 -0
@@ -47,7 +47,9 @@ obj-y += interrupts_64.o else obj-y += interrupts.o endif +ifndef CONFIG_RESET obj-y += reset.o +endif obj-y += cache.o ifndef CONFIG_ARM64
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 9/33 rockchip: Add serial support
In reply to Simon GlassAdd support for the Rockchip serial device using the ns16550 driver. This uses driver model and device tree for both SPL and U-Boot proper.
---
Changes in v4: None
Changes in v3:
- Update clock rate to always be 24MHz
Changes in v2: None
drivers/serial/Kconfig | 9 +++++++++ drivers/serial/Makefile | 1 + drivers/serial/serial_rockchip.c | 43 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 53 insertions(+) create mode 100644 drivers/serial/serial_rockchip.c
drivers/serial/Kconfig +9 -0
@@ -109,6 +109,15 @@ config DEBUG_UART_SHIFT value. Use this value to specify the shift to use, where 0=byte registers, 2=32-bit word registers, etc. +config ROCKCHIP_SERIAL + bool "Rockchip on-chip UART support" + depends on ARCH_UNIPHIER && DM_SERIAL + help + Select this to enable a debug UART for Rockchip devices. This uses + the ns16550 driver. You will need to #define CONFIG_SYS_NS16550 in + your board config header. The clock input is automatically set to + use the oscillator (24MHz). + config SANDBOX_SERIAL bool "Sandbox UART support" depends on SANDBOX && DM
drivers/serial/Makefile +1 -0
@@ -40,6 +40,7 @@ obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o obj-$(CONFIG_MXS_AUART) += mxs_auart.o +obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
drivers/serial/serial_rockchip.c new file +43 -0
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2.5.0.457.gab17608
PATCH v4 10/33 rockchip: Bring in RK3288 device tree file includes and bindings
In reply to Simon GlassBring in required device tree files from Linux. Since mainline Linux is somewhat behind, use the files from the Chromium tree. We can re-sync once further code is acccepted upstream.
---
Changes in v4: None
Changes in v3:
- Add device tree bindings for CRU and DMC
Changes in v2:
- Tidy up license headers and remove SPL #ifdefs
arch/arm/dts/rk3288-thermal.dtsi | 88 ++ arch/arm/dts/rk3288.dtsi | 1458 ++++++++++++++++++++ .../clock/rockchip,rk3188-cru.txt | 61 + .../clock/rockchip,rk3288-cru.txt | 61 + .../clock/rockchip,rk3288-dmc.txt | 155 +++ doc/device-tree-bindings/clock/rockchip.txt | 77 ++ .../pinctrl/rockchip,pinctrl.txt | 157 +++ .../thermal/rockchip-thermal.txt | 68 + include/dt-bindings/clock/rk3288-cru.h | 370 +++++ include/dt-bindings/clock/rockchip,rk808.h | 11 + include/dt-bindings/pinctrl/rockchip.h | 26 + include/dt-bindings/power-domain/rk3288.h | 11 + 12 files changed, 2543 insertions(+) create mode 100644 arch/arm/dts/rk3288-thermal.dtsi create mode 100644 arch/arm/dts/rk3288.dtsi create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txt create mode 100644 doc/device-tree-bindings/clock/rockchip.txt create mode 100644 doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt create mode 100644 doc/device-tree-bindings/thermal/rockchip-thermal.txt create mode 100644 include/dt-bindings/clock/rk3288-cru.h create mode 100644 include/dt-bindings/clock/rockchip,rk808.h create mode 100644 include/dt-bindings/pinctrl/rockchip.h create mode 100644 include/dt-bindings/power-domain/rk3288.h
arch/arm/dts/rk3288-thermal.dtsi new file +88 -0
@@ -0,0 +1,88 @@ +/* + * Device Tree Source for RK3288 SoC thermal + * + * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <dt-bindings/thermal/thermal.h> + +reserve_thermal: reserve_thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tsadc 0>; + +}; + +cpu_thermal: cpu_thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tsadc 1>; + linux,hwmon; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <100000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT 6>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +gpu_thermal: gpu_thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tsadc 2>; + linux,hwmon; + + trips { + gpu_alert0: gpu_alert0 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <100000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +};
arch/arm/dts/rk3288.dtsi new file +1458 -0
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doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt new file +61 -0
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doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt new file +61 -0
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doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txt new file +155 -0
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doc/device-tree-bindings/clock/rockchip.txt new file +77 -0
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doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt new file +157 -0
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doc/device-tree-bindings/thermal/rockchip-thermal.txt new file +68 -0
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include/dt-bindings/clock/rk3288-cru.h new file +370 -0
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include/dt-bindings/clock/rockchip,rk808.h new file +11 -0
@@ -0,0 +1,11 @@ +/* +* This header provides constants clk index RK808 pmic clkout +*/ +#ifndef _CLK_ROCKCHIP_RK808 +#define _CLK_ROCKCHIP_RK808 + +/* CLOCKOUT index */ +#define RK808_CLKOUT0 0 +#define RK808_CLKOUT1 1 + +#endif
include/dt-bindings/pinctrl/rockchip.h new file +26 -0
@@ -0,0 +1,26 @@ +/* +* Header providing constants for Rockchip pinctrl bindings. +* +* Copyright (c) 2013 MundoReader S.L. +* Author: Heiko Stuebner <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ +#define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ + +#define RK_GPIO0 0 +#define RK_GPIO1 1 +#define RK_GPIO2 2 +#define RK_GPIO3 3 +#define RK_GPIO4 4 +#define RK_GPIO6 6 + +#define RK_FUNC_GPIO 0 +#define RK_FUNC_1 1 +#define RK_FUNC_2 2 +#define RK_FUNC_3 3 +#define RK_FUNC_4 4 + +#endif
include/dt-bindings/power-domain/rk3288.h new file +11 -0
@@ -0,0 +1,11 @@ +#ifndef __DT_BINDINGS_POWER_DOMAIN_RK3288_H__ +#define __DT_BINDINGS_POWER_DOMAIN_RK3288_H__ + +/* RK3288 power domain index */ +#define RK3288_PD_GPU 0 +#define RK3288_PD_VIO 1 +#define RK3288_PD_VIDEO 2 +#define RK3288_PD_HEVC 3 +#define RK3288_PD_PERI 4 + +#endif
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 11/33 rockchip: rk3288: dts: Make core devices available early
In reply to Simon GlassIn SPL we need access to the CRU and other peripherals so we can set up SDRAM. Mark these so that they will remain in the device tree.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/dts/rk3288.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
arch/arm/dts/rk3288.dtsi +15 -0
@@ -16,6 +16,15 @@ interrupt-parent = <&gic>; aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + gpio8 = &gpio8; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2;
@@ -454,6 +463,7 @@ }; dmc: dmc at ff610000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3288-dmc", "syscon"; rockchip,cru = <&cru>; rockchip,grf = <&grf>;
@@ -569,11 +579,13 @@ }; pmu: power-management at ff730000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3288-pmu", "syscon"; reg = <0xff730000 0x100>; }; sgrf: syscon at ff740000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3288-sgrf", "syscon"; reg = <0xff740000 0x1000>; };
@@ -582,6 +594,7 @@ compatible = "rockchip,rk3288-cru"; reg = <0xff760000 0x1000>; rockchip,grf = <&grf>; + u-boot,dm-pre-reloc; #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
@@ -600,6 +613,7 @@ }; grf: syscon at ff770000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3288-grf", "syscon"; reg = <0xff770000 0x1000>; };
@@ -804,6 +818,7 @@ }; noc: syscon at ffac0000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3288-noc", "syscon"; reg = <0xffac0000 0x2000>; };
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 12/33 mkimage: Allow padding to any length
In reply to Simon GlassAt present there is an arbitrary limit of 4KB for padding. Rockchip needs more than that, so remove this restriction.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
tools/mkimage.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-)
tools/mkimage.c +12 -11
@@ -488,12 +488,6 @@ copy_file (int ifd, const char *datafile, int pad)int size;struct image_type_params *tparams =imagetool_get_type (params.type); -if (pad >=sizeof (zeros)) { -fprintf (stderr,"%s: Can't pad to %d\n" , - params.cmdname, pad); -exit (EXIT_FAILURE ); - } -memset (zeros,0 ,sizeof (zeros));if (params.vflag) {
@@ -563,11 +557,18 @@ copy_file (int ifd, const char *datafile, int pad)exit (EXIT_FAILURE ); } }else if (pad >1 ) { -if (write (ifd, (char *)&zeros, pad) != pad) { -fprintf (stderr,"%s: Write error on %s: %s\n" , - params.cmdname, params.imagefile, -strerror (errno)); -exit (EXIT_FAILURE ); +while (pad >0 ) { +int todo =sizeof (zeros); + +if (todo > pad) + todo = pad; +if (write (ifd, (char *)&zeros, todo) != todo) { +fprintf (stderr,"%s: Write error on %s: %s\n" , + params.cmdname, params.imagefile, +strerror (errno)); +exit (EXIT_FAILURE ); + } + pad -= todo; } }
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 12/33 mkimage: Allow padding to any length
Hi Simon,
Quoted 4 lines · Simon Glass
At present there is an arbitrary limit of 4KB for padding. Rockchip needs more than that, so remove this restriction.
Signed-off-by Simon Glass <[email protected]>
PATCH v4 13/33 mkimage: Allow the original file size to be recorded
In reply to Simon GlassAllow the image handler to store the original input file size so that it can reference it later.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
tools/imagetool.h | 1 + 1 file changed, 1 insertion(+)
tools/imagetool.h +1 -0
@@ -60,6 +60,7 @@ struct image_tool_params {const char *comment;/* Comment to add to signature node */ int require_keys;/* 1 to mark signing keys as 'required' */ int file_size;/* Total size of output file */ +int orig_file_size;/* Pad size for file */ };/*
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 13/33 mkimage: Allow the original file size to be recorded
Hi Simon,
Quoted 4 lines · Simon Glass
Allow the image handler to store the original input file size so that it can reference it later.
Signed-off-by Simon Glass <[email protected]>
PATCH v4 14/33 rockchip: Add the rkimage format to mkimage
In reply to Simon GlassRockchip SoCs require certain formats for code that they execute, The simplest format is a 4-byte header at the start of a binary file. Add support for this so that we can create images that the boot ROM understands.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
common/image.c | 1 + include/image.h | 3 ++- tools/Makefile | 3 +++ tools/rkcommon.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ tools/rkcommon.h | 28 ++++++++++++++++++++++ tools/rkimage.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 171 insertions(+), 1 deletion(-) create mode 100644 tools/rkcommon.c create mode 100644 tools/rkcommon.h create mode 100644 tools/rkimage.c
common/image.c +1 -0
@@ -155,6 +155,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_ATMELIMAGE, "atmelimage", "ATMEL ROM-Boot Image",}, { IH_TYPE_X86_SETUP, "x86_setup", "x86 setup.bin", }, { IH_TYPE_LPC32XXIMAGE, "lpc32xximage", "LPC32XX Boot Image", }, + { IH_TYPE_RKIMAGE, "rkimage", "Rockchip Boot Image" }, { -1, "", "", }, };
include/image.h +2 -1
@@ -245,8 +245,9 @@ struct lmb;#define IH_TYPE_X86_SETUP 20/* x86 setup.bin Image */ #define IH_TYPE_LPC32XXIMAGE 21/* x86 setup.bin Image */ #define IH_TYPE_LOADABLE 22/* A list of typeless images */ +#define IH_TYPE_RKIMAGE 23/* Rockchip Boot Image */ -#define IH_TYPE_COUNT 23/* Number of image types */ +#define IH_TYPE_COUNT 24/* Number of image types */ /* * Compression Types
tools/Makefile +3 -0
@@ -64,6 +64,8 @@ RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/rsa/, \ rsa-sign.o rsa-verify.o rsa-checksum.o \ rsa-mod-exp.o) +ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o + # common objs for dumpimage and mkimage dumpimage-mkimage-objs := aisimage.o \ atmelimage.o \
@@ -90,6 +92,7 @@ dumpimage-mkimage-objs := aisimage.o \ os_support.o \ pblimage.o \ pbl_crc32.o \ + $(ROCKCHIP_OBS) \ socfpgaimage.o \ lib/sha1.o \ lib/sha256.o \
tools/rkcommon.c new file +72 -0
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tools/rkcommon.h new file +28 -0
@@ -0,0 +1,28 @@ +/* +* (C) Copyright 2015 Google, Inc +* Written by Simon Glass <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef _RKCOMMON_H +#define _RKCOMMON_H + +enum { +RK_BLK_SIZE =512 , +RK_CODE1_OFFSET =4 , +RK_MAX_CODE1_SIZE =32 <<10 , +}; + +/** +* rkcommon_set_header() - set up the header for a Rockchip boot image +* +* This sets up a 2KB header which can be interpreted by the Rockchip boot ROM. +* +* @buf: Pointer to header place (must be at least 2KB in size) +* @file_size: Size of the file we want the boot ROM to load, in bytes +* @return 0 if OK, -ENOSPC if too large +*/ +int rkcommon_set_header (void *buf,uint file_size); + +#endif
tools/rkimage.c new file +65 -0
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Signature · 1 line
2.5.0.457.gab17608
PATCH v4 15/33 rockchip: Add support for the SD image
In reply to Simon GlassThe Rockchip boot ROM requires a particular file format. It consists of 64KB of zeroes, a 512-byte header encoded with RC4, and then some executable code.
Add support to mkimage so that an SPL image (u-boot-spl-dtb.bin) can be converted to this format.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
common/image.c | 1 + include/image.h | 3 +- tools/Makefile | 2 +- tools/rksd.c | 102 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 106 insertions(+), 2 deletions(-) create mode 100644 tools/rksd.c
common/image.c +1 -0
@@ -156,6 +156,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_X86_SETUP, "x86_setup", "x86 setup.bin", }, { IH_TYPE_LPC32XXIMAGE, "lpc32xximage", "LPC32XX Boot Image", }, { IH_TYPE_RKIMAGE, "rkimage", "Rockchip Boot Image" }, + { IH_TYPE_RKSD, "rksd", "Rockchip SD Boot Image" }, { -1, "", "", }, };
include/image.h +2 -1
@@ -246,8 +246,9 @@ struct lmb;#define IH_TYPE_LPC32XXIMAGE 21/* x86 setup.bin Image */ #define IH_TYPE_LOADABLE 22/* A list of typeless images */ #define IH_TYPE_RKIMAGE 23/* Rockchip Boot Image */ +#define IH_TYPE_RKSD 24/* Rockchip SD card */ -#define IH_TYPE_COUNT 24/* Number of image types */ +#define IH_TYPE_COUNT 25/* Number of image types */ /* * Compression Types
tools/Makefile +1 -1
@@ -64,7 +64,7 @@ RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/rsa/, \ rsa-sign.o rsa-verify.o rsa-checksum.o \ rsa-mod-exp.o) -ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o +ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rksd.o # common objs for dumpimage and mkimage dumpimage-mkimage-objs := aisimage.o \
tools/rksd.c new file +102 -0
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Signature · 1 line
2.5.0.457.gab17608
PATCH v4 16/33 rockchip: Add support for the SPI image
In reply to Simon GlassThe Rockchip boot ROM requires a particular file format for booting from SPI. It consists of a 512-byte header encoded with RC4, some padding and then up to 32KB of executable code in 2KB blocks, separated by 2KB empty blocks.
Add support to mkimage so that an SPL image (u-boot-spl-dtb.bin) can be converted to this format. This allows booting from SPI flash on supported machines.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
common/image.c | 1 + include/image.h | 3 +- tools/rkspi.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 122 insertions(+), 1 deletion(-) create mode 100644 tools/rkspi.c
common/image.c +1 -0
@@ -157,6 +157,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_LPC32XXIMAGE, "lpc32xximage", "LPC32XX Boot Image", }, { IH_TYPE_RKIMAGE, "rkimage", "Rockchip Boot Image" }, { IH_TYPE_RKSD, "rksd", "Rockchip SD Boot Image" }, + { IH_TYPE_RKSPI, "rkspi", "Rockchip SPI Boot Image" }, { -1, "", "", }, };
include/image.h +2 -1
@@ -247,8 +247,9 @@ struct lmb;#define IH_TYPE_LOADABLE 22/* A list of typeless images */ #define IH_TYPE_RKIMAGE 23/* Rockchip Boot Image */ #define IH_TYPE_RKSD 24/* Rockchip SD card */ +#define IH_TYPE_RKSPI 25/* Rockchip SD card */ -#define IH_TYPE_COUNT 25/* Number of image types */ +#define IH_TYPE_COUNT 26/* Number of image types */ /* * Compression Types
tools/rkspi.c new file +119 -0
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Signature · 1 line
2.5.0.457.gab17608
PATCH v4 17/33 rockchip: gpio: Add rockchip GPIO driver
In reply to Simon GlassThis supports RK3288 at present. It does not implement functions or support for pull up/down.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/gpio.h | 28 +++++++ drivers/gpio/Kconfig | 9 +++ drivers/gpio/Makefile | 1 + drivers/gpio/rk_gpio.c | 123 ++++++++++++++++++++++++++++++ 4 files changed, 161 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/gpio.h create mode 100644 drivers/gpio/rk_gpio.c
arch/arm/include/asm/arch-rockchip/gpio.h new file +28 -0
@@ -0,0 +1,28 @@ +/* +* (C) Copyright 2015 Google, Inc +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef _ASM_ARCH_GPIO_H +#define _ASM_ARCH_GPIO_H + +struct rockchip_gpio_regs { +u32 swport_dr; +u32 swport_ddr; +u32 reserved0[(0x30 -0x08 ) /4 ]; +u32 inten; +u32 intmask; +u32 inttype_level; +u32 int_polarity; +u32 int_status; +u32 int_rawstatus; +u32 debounce; +u32 porta_eoi; +u32 ext_port; +u32 reserved1[(0x60 -0x54 ) /4 ]; +u32 ls_sync; +}; +check_member (rockchip_gpio_regs, ls_sync,0x60 ); + +#endif
drivers/gpio/Kconfig +9 -0
@@ -21,6 +21,15 @@ config LPC32XX_GPIO help Support for the LPC32XX GPIO driver. +config ROCKCHIP_GPIO + bool "Rockchip GPIO driver" + depends on DM_GPIO + help + Support GPIO access on Rockchip SoCs. The GPIOs are arranged into + a number of banks (different for each SoC type) each with 32 GPIOs. + The GPIOs for a device are defined in the device tree with one node + for each bank. + config SANDBOX_GPIO bool "Enable sandbox GPIO driver" depends on SANDBOX && DM && DM_GPIO
drivers/gpio/Makefile +1 -0
@@ -20,6 +20,7 @@ obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o obj-$(CONFIG_PCA953X) += pca953x.o obj-$(CONFIG_PCA9698) += pca9698.o +obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o obj-$(CONFIG_S5P) += s5p_gpio.o obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o obj-$(CONFIG_SPEAR_GPIO) += spear_gpio.o
drivers/gpio/rk_gpio.c new file +123 -0
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Signature · 1 line
2.5.0.457.gab17608
PATCH v4 18/33 rockchip: Add basic peripheral and clock definitions
In reply to Simon GlassAdd header files for the peripherals and clocks supported on Rockchip platforms. The particular implementation (and register set) for each is SoC-specific, but it seems that the naming can be generic.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/clock.h | 45 ++++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/hardware.h | 20 ++++++++++ arch/arm/include/asm/arch-rockchip/periph.h | 54 +++++++++++++++++++++++++++ 3 files changed, 119 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/clock.h create mode 100644 arch/arm/include/asm/arch-rockchip/hardware.h create mode 100644 arch/arm/include/asm/arch-rockchip/periph.h
arch/arm/include/asm/arch-rockchip/clock.h new file +45 -0
@@ -0,0 +1,45 @@ +/* +* (C) Copyright 2015 Google, Inc +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef _ASM_ARCH_CLOCK_H +#define _ASM_ARCH_CLOCK_H + +/* define pll mode */ +#define RKCLK_PLL_MODE_SLOW 0 +#define RKCLK_PLL_MODE_NORMAL 1 + +enum { +ROCKCHIP_SYSCON_NOC , +ROCKCHIP_SYSCON_GRF , +ROCKCHIP_SYSCON_SGRF , +ROCKCHIP_SYSCON_PMU , +}; + +/* Standard Rockchip clock numbers */ +enum rk_clk_id { +CLK_OSC , +CLK_ARM , +CLK_DDR , +CLK_CODEC , +CLK_GENERAL , +CLK_NEW , + +CLK_COUNT , +}; + +static inline int rk_pll_id (enum rk_clk_id clk_id) +{ +return clk_id -1 ; +} + +/** +* rockchip_get_cru() - get a pointer to the clock/reset unit registers +* +* @return pointer to registers, or -ve error on error +*/ +void *rockchip_get_cru (void ); + +#endif
arch/arm/include/asm/arch-rockchip/hardware.h new file +20 -0
@@ -0,0 +1,20 @@ +/* +* Copyright 2015 Google, Inc +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +#define RK_CLRSETBITS (clr, set) ((((clr) | (set)) << 16) | set) +#define RK_SETBITS (set) RK_CLRSETBITS(0, set) +#define RK_CLRBITS (clr) RK_CLRSETBITS(clr, 0) + +#define TIMER7_BASE 0xff810020 + +#define rk_clrsetreg (addr, clr, set) writel((clr) << 16 | (set), addr) +#define rk_clrreg (addr, clr) writel((clr) << 16, addr) +#define rk_setreg (addr, set) writel(set, addr) + +#endif
arch/arm/include/asm/arch-rockchip/periph.h new file +54 -0
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Signature · 1 line
2.5.0.457.gab17608
PATCH v4 19/33 power: Add support for ACT8846 PMIC
In reply to Simon GlassAdd a driver for the ACT8846 PMIC. This supports several LDOs and BUCKs and is connected to the I2C bus. This driver supports using a regulator driver to access the regulators.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/power/pmic/Kconfig | 9 +++++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/act8846.c | 90 ++++++++++++++++++++++++++++++++++++++++++++ include/power/act8846_pmic.h | 37 ++++++++++++++++++ 4 files changed, 137 insertions(+) create mode 100644 drivers/power/pmic/act8846.c create mode 100644 include/power/act8846_pmic.h
drivers/power/pmic/Kconfig +9 -0
@@ -10,6 +10,15 @@ config DM_PMIC - 'drivers/power/pmic/pmic-uclass.c' - 'include/power/pmic.h' +config PMIC_ACT8846 + bool "Enable support for the active-semi 8846 PMIC" + depends on DM_PMIC && DM_I2C + ---help--- + This PMIC includes 4 DC/DC step-down buck regulators and 8 low-dropout + regulators (LDOs). It also provides some GPIO, reset and battery + functions. It uses an I2C interface and is designed for use with + tablets and smartphones. + config DM_PMIC_PFUZE100 bool "Enable Driver Model for PMIC PFUZE100" depends on DM_PMIC
drivers/power/pmic/Makefile +1 -0
@@ -9,6 +9,7 @@ obj-$(CONFIG_DM_PMIC) += pmic-uclass.o obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o +obj-$(CONFIG_PMIC_ACT8846) += act8846.o obj-$(CONFIG_PMIC_TPS65090) += tps65090.o obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
drivers/power/pmic/act8846.c new file +90 -0
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include/power/act8846_pmic.h new file +37 -0
@@ -0,0 +1,37 @@ +/* +* Copyright (C) 2015 Google, Inc +* Written by Simon Glass <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef _PMIC_ACT8846_H_ +#define _PMIC_ACT8846_H_ + +#include <asm/gpio.h> + +#define ACT8846_NUM_OF_REGS 12 + +#define BUCK_VOL_MASK 0x3f +#define LDO_VOL_MASK 0x3f + +#define BUCK_EN_MASK 0x80 +#define LDO_EN_MASK 0x80 + +#define VOL_MIN_IDX 0x00 +#define VOL_MAX_IDX 0x3f + +struct act8846_reg_table { +char *name; +char reg_ctl; +char reg_vol; +}; + +struct pmic_act8846 { +struct pmic *pmic; +int node;/*device tree node*/ +struct gpio_desc pwr_hold; +struct udevice *dev; +}; + +#endif
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 20/33 power: regulator: Add a driver for ACT8846 regulators
In reply to Simon GlassAdd a full regulator driver for the ACT8846. This provides easy access to voltage and current settings for each regulator.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/power/regulator/Kconfig | 9 +++ drivers/power/regulator/Makefile | 1 + drivers/power/regulator/act8846.c | 155 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 165 insertions(+) create mode 100644 drivers/power/regulator/act8846.c
drivers/power/regulator/Kconfig +9 -0
@@ -16,6 +16,15 @@ config DM_REGULATOR for this purpose if PMIC I/O driver is implemented or dm_scan_fdt_node() otherwise. Detailed information can be found in the header file. +config REGULATOR_ACT8846 + bool "Enable driver for ACT8846 regulator" + depends on DM_REGULATOR && PMIC_ACT8846 + ---help--- + Enable support for the regulator functions of the ACT8846 PMIC. The + driver implements get/set api for the various BUCKS and LDOS supported + by the PMIC device. This driver is controlled by a device tree node + which includes voltage limits. + config DM_REGULATOR_PFUZE100 bool "Enable Driver Model for REGULATOR PFUZE100" depends on DM_REGULATOR && DM_PMIC_PFUZE100
drivers/power/regulator/Makefile +1 -0
@@ -6,6 +6,7 @@ # obj-$(CONFIG_DM_REGULATOR) += regulator-uclass.o +obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o obj-$(CONFIG_DM_REGULATOR_FIXED) += fixed.o
drivers/power/regulator/act8846.c new file +155 -0
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2.5.0.457.gab17608
PATCH v4 21/33 rockchip: rk3288: Add clock driver
In reply to Simon GlassAdd a driver for setting up and modifying the various PLLs and peripheral clocks on the RK3288.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 185 +++++++ drivers/clk/Makefile | 1 + drivers/clk/clk_rk3288.c | 618 ++++++++++++++++++++++++ 3 files changed, 804 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3288.h create mode 100644 drivers/clk/clk_rk3288.c
arch/arm/include/asm/arch-rockchip/cru_rk3288.h new file +185 -0
@@ -0,0 +1,185 @@ +/* +* (C) Copyright 2015 Google, Inc +* +* (C) Copyright 2008-2014 Rockchip Electronics +* Peter, Software Engineering, <[email protected]>. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ +#ifndef _ASM_ARCH_CRU_RK3288_H +#define _ASM_ARCH_CRU_RK3288_H + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (1800 * 1000000) +#define GPLL_HZ (594 * 1000000) +#define CPLL_HZ (384 * 1000000) +#define NPLL_HZ (384 * 1000000) + +/* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */ +#define PD_BUS_ACLK_HZ 297000000 +#define PD_BUS_HCLK_HZ 148500000 +#define PD_BUS_PCLK_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +struct rk3288_cru { +struct rk3288_pll { +u32 con0; +u32 con1; +u32 con2; +u32 con3; + } pll[5 ]; +u32 cru_mode_con; +u32 reserved0[3 ]; +u32 cru_clksel_con[43 ]; +u32 reserved1[21 ]; +u32 cru_clkgate_con[19 ]; +u32 reserved2; +u32 cru_glb_srst_fst_value; +u32 cru_glb_srst_snd_value; +u32 cru_softrst_con[12 ]; +u32 cru_misc_con; +u32 cru_glb_cnt_th; +u32 cru_glb_rst_con; +u32 reserved3; +u32 cru_glb_rst_st; +u32 reserved4; +u32 cru_sdmmc_con[2 ]; +u32 cru_sdio0_con[2 ]; +u32 cru_sdio1_con[2 ]; +u32 cru_emmc_con[2 ]; +}; +check_member (rk3288_cru, cru_emmc_con[1 ],0x021c ); + +/* CRU_CLKSEL11_CON */ +enum { +HSICPHY_DIV_SHIFT =8 , +HSICPHY_DIV_MASK =0x3f , + +MMC0_PLL_SHIFT =6 , +MMC0_PLL_MASK =3 , +MMC0_PLL_SELECT_CODEC =0 , +MMC0_PLL_SELECT_GENERAL , +MMC0_PLL_SELECT_24MHZ , + +MMC0_DIV_SHIFT =0 , +MMC0_DIV_MASK =0x3f , +}; + +/* CRU_CLKSEL12_CON */ +enum { +EMMC_PLL_SHIFT =0xe , +EMMC_PLL_MASK =3 , +EMMC_PLL_SELECT_CODEC =0 , +EMMC_PLL_SELECT_GENERAL , +EMMC_PLL_SELECT_24MHZ , + +EMMC_DIV_SHIFT =8 , +EMMC_DIV_MASK =0x3f , + +SDIO0_PLL_SHIFT =6 , +SDIO0_PLL_MASK =3 , +SDIO0_PLL_SELECT_CODEC =0 , +SDIO0_PLL_SELECT_GENERAL , +SDIO0_PLL_SELECT_24MHZ , + +SDIO0_DIV_SHIFT =0 , +SDIO0_DIV_MASK =0x3f , +}; + +/* CRU_CLKSEL25_CON */ +enum { +SPI1_PLL_SHIFT =0xf , +SPI1_PLL_MASK =1 , +SPI1_PLL_SELECT_CODEC =0 , +SPI1_PLL_SELECT_GENERAL , + +SPI1_DIV_SHIFT =8 , +SPI1_DIV_MASK =0x7f , + +SPI0_PLL_SHIFT =7 , +SPI0_PLL_MASK =1 , +SPI0_PLL_SELECT_CODEC =0 , +SPI0_PLL_SELECT_GENERAL , + +SPI0_DIV_SHIFT =0 , +SPI0_DIV_MASK =0x7f , +}; + +/* CRU_CLKSEL39_CON */ +enum { +ACLK_HEVC_PLL_SHIFT =0xe , +ACLK_HEVC_PLL_MASK =3 , +ACLK_HEVC_PLL_SELECT_CODEC =0 , +ACLK_HEVC_PLL_SELECT_GENERAL , +ACLK_HEVC_PLL_SELECT_NEW , + +ACLK_HEVC_DIV_SHIFT =8 , +ACLK_HEVC_DIV_MASK =0x1f , + +SPI2_PLL_SHIFT =7 , +SPI2_PLL_MASK =1 , +SPI2_PLL_SELECT_CODEC =0 , +SPI2_PLL_SELECT_GENERAL , + +SPI2_DIV_SHIFT =0 , +SPI2_DIV_MASK =0x7f , +}; + +/* CRU_MODE_CON */ +enum { +NPLL_WORK_SHIFT =0xe , +NPLL_WORK_MASK =3 , +NPLL_WORK_SLOW =0 , +NPLL_WORK_NORMAL , +NPLL_WORK_DEEP , + +GPLL_WORK_SHIFT =0xc , +GPLL_WORK_MASK =3 , +GPLL_WORK_SLOW =0 , +GPLL_WORK_NORMAL , +GPLL_WORK_DEEP , + +CPLL_WORK_SHIFT =8 , +CPLL_WORK_MASK =3 , +CPLL_WORK_SLOW =0 , +CPLL_WORK_NORMAL , +CPLL_WORK_DEEP , + +DPLL_WORK_SHIFT =4 , +DPLL_WORK_MASK =3 , +DPLL_WORK_SLOW =0 , +DPLL_WORK_NORMAL , +DPLL_WORK_DEEP , + +APLL_WORK_SHIFT =0 , +APLL_WORK_MASK =3 , +APLL_WORK_SLOW =0 , +APLL_WORK_NORMAL , +APLL_WORK_DEEP , +}; + +/* CRU_APLL_CON0 */ +enum { +CLKR_SHIFT =8 , +CLKR_MASK =0x3f , + +CLKOD_SHIFT =0 , +CLKOD_MASK =0xf , +}; + +/* CRU_APLL_CON1 */ +enum { +LOCK_SHIFT =0x1f , +LOCK_MASK =1 , +LOCK_UNLOCK =0 , +LOCK_LOCK , + +CLKF_SHIFT =0 , +CLKF_MASK =0x1fff , +}; + +#endif
drivers/clk/Makefile +1 -0
@@ -6,4 +6,5 @@ # obj-$(CONFIG_CLK) += clk-uclass.o +obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_SANDBOX) += clk_sandbox.o
drivers/clk/clk_rk3288.c new file +618 -0
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Signature · 1 line
2.5.0.457.gab17608
PATCH v4 22/33 rockchip: rk3288: Add header files for PMU and GRF
In reply to Simon GlassPMU is the power management unit and GRF is the general register file. Both are heavily used in U-Boot. Add header files with register definitions.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 768 ++++++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/pmu_rk3288.h | 89 +++ 2 files changed, 857 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3288.h
arch/arm/include/asm/arch-rockchip/grf_rk3288.h new file +768 -0
@@ -0,0 +1,768 @@ +/* +* (C) Copyright 2015 Google, Inc +* Copyright 2014 Rockchip Inc. +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef _ASM_ARCH_GRF_RK3288_H +#define _ASM_ARCH_GRF_RK3288_H + +struct rk3288_grf_gpio_lh { +u32 l; +u32 h; +}; + +struct rk3288_grf { +u32 reserved[3 ]; +u32 gpio1d_iomux; +u32 gpio2a_iomux; +u32 gpio2b_iomux; + +u32 gpio2c_iomux; +u32 reserved2; +u32 gpio3a_iomux; +u32 gpio3b_iomux; + +u32 gpio3c_iomux; +u32 gpio3dl_iomux; +u32 gpio3dh_iomux; +u32 gpio4al_iomux; + +u32 gpio4ah_iomux; +u32 gpio4bl_iomux; +u32 reserved3; +u32 gpio4c_iomux; + +u32 gpio4d_iomux; +u32 reserved4; +u32 gpio5b_iomux; +u32 gpio5c_iomux; + +u32 reserved5; +u32 gpio6a_iomux; +u32 gpio6b_iomux; +u32 gpio6c_iomux; +u32 reserved6; +u32 gpio7a_iomux; +u32 gpio7b_iomux; +u32 gpio7cl_iomux; +u32 gpio7ch_iomux; +u32 reserved7; +u32 gpio8a_iomux; +u32 gpio8b_iomux; +u32 reserved8[30 ]; +struct rk3288_grf_gpio_lh gpio_sr[8 ]; +u32 gpio1_p[8 ][4 ]; +u32 gpio1_e[8 ][4 ]; +u32 gpio_smt; +u32 soc_con0; +u32 soc_con1; +u32 soc_con2; +u32 soc_con3; +u32 soc_con4; +u32 soc_con5; +u32 soc_con6; +u32 soc_con7; +u32 soc_con8; +u32 soc_con9; +u32 soc_con10; +u32 soc_con11; +u32 soc_con12; +u32 soc_con13; +u32 soc_con14; +u32 soc_status[22 ]; +u32 reserved9[2 ]; +u32 peridmac_con[4 ]; +u32 ddrc0_con0; +u32 ddrc1_con0; +u32 cpu_con[5 ]; +u32 reserved10[3 ]; +u32 cpu_status0; +u32 reserved11; +u32 uoc0_con[5 ]; +u32 uoc1_con[5 ]; +u32 uoc2_con[4 ]; +u32 uoc3_con[2 ]; +u32 uoc4_con[2 ]; +u32 pvtm_con[3 ]; +u32 pvtm_status[3 ]; +u32 io_vsel; +u32 saradc_testbit; +u32 tsadc_testbit_l; +u32 tsadc_testbit_h; +u32 os_reg[4 ]; +u32 reserved12; +u32 soc_con15; +u32 soc_con16; +}; + +struct rk3288_sgrf { +u32 soc_con0; +u32 soc_con1; +u32 soc_con2; +u32 soc_con3; +u32 soc_con4; +u32 soc_con5; +u32 reserved1[(0x20 -0x18 )/4 ]; +u32 busdmac_con[2 ]; +u32 reserved2[(0x40 -0x28 )/4 ]; +u32 cpu_con[3 ]; +u32 reserved3[(0x50 -0x4c )/4 ]; +u32 soc_con6; +u32 soc_con7; +u32 soc_con8; +u32 soc_con9; +u32 soc_con10; +u32 soc_con11; +u32 soc_con12; +u32 soc_con13; +u32 soc_con14; +u32 soc_con15; +u32 soc_con16; +u32 soc_con17; +u32 soc_con18; +u32 soc_con19; +u32 soc_con20; +u32 soc_con21; +u32 reserved4[(0x100 -0x90 )/4 ]; +u32 soc_status[2 ]; +u32 reserved5[(0x120 -0x108 )/4 ]; +u32 fast_boot_addr; +}; + +/* GRF_GPIO1D_IOMUX */ +enum { +GPIO1D3_SHIFT =6 , +GPIO1D3_MASK =1 , +GPIO1D3_GPIO =0 , +GPIO1D3_LCDC0_DCLK , + +GPIO1D2_SHIFT =4 , +GPIO1D2_MASK =1 , +GPIO1D2_GPIO =0 , +GPIO1D2_LCDC0_DEN , + +GPIO1D1_SHIFT =2 , +GPIO1D1_MASK =1 , +GPIO1D1_GPIO =0 , +GPIO1D1_LCDC0_VSYNC , + +GPIO1D0_SHIFT =0 , +GPIO1D0_MASK =1 , +GPIO1D0_GPIO =0 , +GPIO1D0_LCDC0_HSYNC , +}; + +/* GRF_GPIO2C_IOMUX */ +enum { +GPIO2C1_SHIFT =2 , +GPIO2C1_MASK =1 , +GPIO2C1_GPIO =0 , +GPIO2C1_I2C3CAM_SDA , + +GPIO2C0_SHIFT =0 , +GPIO2C0_MASK =1 , +GPIO2C0_GPIO =0 , +GPIO2C0_I2C3CAM_SCL , +}; + +/* GRF_GPIO3A_IOMUX */ +enum { +GPIO3A7_SHIFT =14 , +GPIO3A7_MASK =3 , +GPIO3A7_GPIO =0 , +GPIO3A7_FLASH0_DATA7 , +GPIO3A7_EMMC_DATA7 , + +GPIO3A6_SHIFT =12 , +GPIO3A6_MASK =3 , +GPIO3A6_GPIO =0 , +GPIO3A6_FLASH0_DATA6 , +GPIO3A6_EMMC_DATA6 , + +GPIO3A5_SHIFT =10 , +GPIO3A5_MASK =3 , +GPIO3A5_GPIO =0 , +GPIO3A5_FLASH0_DATA5 , +GPIO3A5_EMMC_DATA5 , + +GPIO3A4_SHIFT =8 , +GPIO3A4_MASK =3 , +GPIO3A4_GPIO =0 , +GPIO3A4_FLASH0_DATA4 , +GPIO3A4_EMMC_DATA4 , + +GPIO3A3_SHIFT =6 , +GPIO3A3_MASK =3 , +GPIO3A3_GPIO =0 , +GPIO3A3_FLASH0_DATA3 , +GPIO3A3_EMMC_DATA3 , + +GPIO3A2_SHIFT =4 , +GPIO3A2_MASK =3 , +GPIO3A2_GPIO =0 , +GPIO3A2_FLASH0_DATA2 , +GPIO3A2_EMMC_DATA2 , + +GPIO3A1_SHIFT =2 , +GPIO3A1_MASK =3 , +GPIO3A1_GPIO =0 , +GPIO3A1_FLASH0_DATA1 , +GPIO3A1_EMMC_DATA1 , + +GPIO3A0_SHIFT =0 , +GPIO3A0_MASK =3 , +GPIO3A0_GPIO =0 , +GPIO3A0_FLASH0_DATA0 , +GPIO3A0_EMMC_DATA0 , +}; + +/* GRF_GPIO3B_IOMUX */ +enum { +GPIO3B7_SHIFT =14 , +GPIO3B7_MASK =1 , +GPIO3B7_GPIO =0 , +GPIO3B7_FLASH0_CSN1 , + +GPIO3B6_SHIFT =12 , +GPIO3B6_MASK =1 , +GPIO3B6_GPIO =0 , +GPIO3B6_FLASH0_CSN0 , + +GPIO3B5_SHIFT =10 , +GPIO3B5_MASK =1 , +GPIO3B5_GPIO =0 , +GPIO3B5_FLASH0_WRN , + +GPIO3B4_SHIFT =8 , +GPIO3B4_MASK =1 , +GPIO3B4_GPIO =0 , +GPIO3B4_FLASH0_CLE , + +GPIO3B3_SHIFT =6 , +GPIO3B3_MASK =1 , +GPIO3B3_GPIO =0 , +GPIO3B3_FLASH0_ALE , + +GPIO3B2_SHIFT =4 , +GPIO3B2_MASK =1 , +GPIO3B2_GPIO =0 , +GPIO3B2_FLASH0_RDN , + +GPIO3B1_SHIFT =2 , +GPIO3B1_MASK =3 , +GPIO3B1_GPIO =0 , +GPIO3B1_FLASH0_WP , +GPIO3B1_EMMC_PWREN , + +GPIO3B0_SHIFT =0 , +GPIO3B0_MASK =1 , +GPIO3B0_GPIO =0 , +GPIO3B0_FLASH0_RDY , +}; + +/* GRF_GPIO3C_IOMUX */ +enum { +GPIO3C2_SHIFT =4 , +GPIO3C2_MASK =3 , +GPIO3C2_GPIO =0 , +GPIO3C2_FLASH0_DQS , +GPIO3C2_EMMC_CLKOUT , + +GPIO3C1_SHIFT =2 , +GPIO3C1_MASK =3 , +GPIO3C1_GPIO =0 , +GPIO3C1_FLASH0_CSN3 , +GPIO3C1_EMMC_RSTNOUT , + +GPIO3C0_SHIFT =0 , +GPIO3C0_MASK =3 , +GPIO3C0_GPIO =0 , +GPIO3C0_FLASH0_CSN2 , +GPIO3C0_EMMC_CMD , +}; + +/* GRF_GPIO4C_IOMUX */ +enum { +GPIO4C7_SHIFT =14 , +GPIO4C7_MASK =1 , +GPIO4C7_GPIO =0 , +GPIO4C7_SDIO0_DATA3 , + +GPIO4C6_SHIFT =12 , +GPIO4C6_MASK =1 , +GPIO4C6_GPIO =0 , +GPIO4C6_SDIO0_DATA2 , + +GPIO4C5_SHIFT =10 , +GPIO4C5_MASK =1 , +GPIO4C5_GPIO =0 , +GPIO4C5_SDIO0_DATA1 , + +GPIO4C4_SHIFT =8 , +GPIO4C4_MASK =1 , +GPIO4C4_GPIO =0 , +GPIO4C4_SDIO0_DATA0 , + +GPIO4C3_SHIFT =6 , +GPIO4C3_MASK =1 , +GPIO4C3_GPIO =0 , +GPIO4C3_UART0BT_RTSN , + +GPIO4C2_SHIFT =4 , +GPIO4C2_MASK =1 , +GPIO4C2_GPIO =0 , +GPIO4C2_UART0BT_CTSN , + +GPIO4C1_SHIFT =2 , +GPIO4C1_MASK =1 , +GPIO4C1_GPIO =0 , +GPIO4C1_UART0BT_SOUT , + +GPIO4C0_SHIFT =0 , +GPIO4C0_MASK =1 , +GPIO4C0_GPIO =0 , +GPIO4C0_UART0BT_SIN , +}; + +/* GRF_GPIO5B_IOMUX */ +enum { +GPIO5B7_SHIFT =14 , +GPIO5B7_MASK =3 , +GPIO5B7_GPIO =0 , +GPIO5B7_SPI0_RXD , +GPIO5B7_TS0_DATA7 , +GPIO5B7_UART4EXP_SIN , + +GPIO5B6_SHIFT =12 , +GPIO5B6_MASK =3 , +GPIO5B6_GPIO =0 , +GPIO5B6_SPI0_TXD , +GPIO5B6_TS0_DATA6 , +GPIO5B6_UART4EXP_SOUT , + +GPIO5B5_SHIFT =10 , +GPIO5B5_MASK =3 , +GPIO5B5_GPIO =0 , +GPIO5B5_SPI0_CSN0 , +GPIO5B5_TS0_DATA5 , +GPIO5B5_UART4EXP_RTSN , + +GPIO5B4_SHIFT =8 , +GPIO5B4_MASK =3 , +GPIO5B4_GPIO =0 , +GPIO5B4_SPI0_CLK , +GPIO5B4_TS0_DATA4 , +GPIO5B4_UART4EXP_CTSN , + +GPIO5B3_SHIFT =6 , +GPIO5B3_MASK =3 , +GPIO5B3_GPIO =0 , +GPIO5B3_UART1BB_RTSN , +GPIO5B3_TS0_DATA3 , + +GPIO5B2_SHIFT =4 , +GPIO5B2_MASK =3 , +GPIO5B2_GPIO =0 , +GPIO5B2_UART1BB_CTSN , +GPIO5B2_TS0_DATA2 , + +GPIO5B1_SHIFT =2 , +GPIO5B1_MASK =3 , +GPIO5B1_GPIO =0 , +GPIO5B1_UART1BB_SOUT , +GPIO5B1_TS0_DATA1 , + +GPIO5B0_SHIFT =0 , +GPIO5B0_MASK =3 , +GPIO5B0_GPIO =0 , +GPIO5B0_UART1BB_SIN , +GPIO5B0_TS0_DATA0 , +}; + +/* GRF_GPIO5C_IOMUX */ +enum { +GPIO5C3_SHIFT =6 , +GPIO5C3_MASK =1 , +GPIO5C3_GPIO =0 , +GPIO5C3_TS0_ERR , + +GPIO5C2_SHIFT =4 , +GPIO5C2_MASK =1 , +GPIO5C2_GPIO =0 , +GPIO5C2_TS0_CLK , + +GPIO5C1_SHIFT =2 , +GPIO5C1_MASK =1 , +GPIO5C1_GPIO =0 , +GPIO5C1_TS0_VALID , + +GPIO5C0_SHIFT =0 , +GPIO5C0_MASK =3 , +GPIO5C0_GPIO =0 , +GPIO5C0_SPI0_CSN1 , +GPIO5C0_TS0_SYNC , +}; + +/* GRF_GPIO6B_IOMUX */ +enum { +GPIO6B3_SHIFT =6 , +GPIO6B3_MASK =1 , +GPIO6B3_GPIO =0 , +GPIO6B3_SPDIF_TX , + +GPIO6B2_SHIFT =4 , +GPIO6B2_MASK =1 , +GPIO6B2_GPIO =0 , +GPIO6B2_I2C1AUDIO_SCL , + +GPIO6B1_SHIFT =2 , +GPIO6B1_MASK =1 , +GPIO6B1_GPIO =0 , +GPIO6B1_I2C1AUDIO_SDA , + +GPIO6B0_SHIFT =0 , +GPIO6B0_MASK =1 , +GPIO6B0_GPIO =0 , +GPIO6B0_I2S_CLK , +}; + +/* GRF_GPIO6C_IOMUX */ +enum { +GPIO6C6_SHIFT =12 , +GPIO6C6_MASK =1 , +GPIO6C6_GPIO =0 , +GPIO6C6_SDMMC0_DECTN , + +GPIO6C5_SHIFT =10 , +GPIO6C5_MASK =1 , +GPIO6C5_GPIO =0 , +GPIO6C5_SDMMC0_CMD , + +GPIO6C4_SHIFT =8 , +GPIO6C4_MASK =3 , +GPIO6C4_GPIO =0 , +GPIO6C4_SDMMC0_CLKOUT , +GPIO6C4_JTAG_TDO , + +GPIO6C3_SHIFT =6 , +GPIO6C3_MASK =3 , +GPIO6C3_GPIO =0 , +GPIO6C3_SDMMC0_DATA3 , +GPIO6C3_JTAG_TCK , + +GPIO6C2_SHIFT =4 , +GPIO6C2_MASK =3 , +GPIO6C2_GPIO =0 , +GPIO6C2_SDMMC0_DATA2 , +GPIO6C2_JTAG_TDI , + +GPIO6C1_SHIFT =2 , +GPIO6C1_MASK =3 , +GPIO6C1_GPIO =0 , +GPIO6C1_SDMMC0_DATA1 , +GPIO6C1_JTAG_TRSTN , + +GPIO6C0_SHIFT =0 , +GPIO6C0_MASK =3 , +GPIO6C0_GPIO =0 , +GPIO6C0_SDMMC0_DATA0 , +GPIO6C0_JTAG_TMS , +}; + +/* GRF_GPIO7A_IOMUX */ +enum { +GPIO7A7_SHIFT =14 , +GPIO7A7_MASK =3 , +GPIO7A7_GPIO =0 , +GPIO7A7_UART3GPS_SIN , +GPIO7A7_GPS_MAG , +GPIO7A7_HSADCT1_DATA0 , + +GPIO7A1_SHIFT =2 , +GPIO7A1_MASK =1 , +GPIO7A1_GPIO =0 , +GPIO7A1_PWM_1 , + +GPIO7A0_SHIFT =0 , +GPIO7A0_MASK =3 , +GPIO7A0_GPIO =0 , +GPIO7A0_PWM_0 , +GPIO7A0_VOP0_PWM , +GPIO7A0_VOP1_PWM , +}; + +/* GRF_GPIO7B_IOMUX */ +enum { +GPIO7B7_SHIFT =14 , +GPIO7B7_MASK =3 , +GPIO7B7_GPIO =0 , +GPIO7B7_ISP_SHUTTERTRIG , +GPIO7B7_SPI1_TXD , + +GPIO7B6_SHIFT =12 , +GPIO7B6_MASK =3 , +GPIO7B6_GPIO =0 , +GPIO7B6_ISP_PRELIGHTTRIG , +GPIO7B6_SPI1_RXD , + +GPIO7B5_SHIFT =10 , +GPIO7B5_MASK =3 , +GPIO7B5_GPIO =0 , +GPIO7B5_ISP_FLASHTRIGOUT , +GPIO7B5_SPI1_CSN0 , + +GPIO7B4_SHIFT =8 , +GPIO7B4_MASK =3 , +GPIO7B4_GPIO =0 , +GPIO7B4_ISP_SHUTTEREN , +GPIO7B4_SPI1_CLK , + +GPIO7B3_SHIFT =6 , +GPIO7B3_MASK =3 , +GPIO7B3_GPIO =0 , +GPIO7B3_USB_DRVVBUS1 , +GPIO7B3_EDP_HOTPLUG , + +GPIO7B2_SHIFT =4 , +GPIO7B2_MASK =3 , +GPIO7B2_GPIO =0 , +GPIO7B2_UART3GPS_RTSN , +GPIO7B2_USB_DRVVBUS0 , + +GPIO7B1_SHIFT =2 , +GPIO7B1_MASK =3 , +GPIO7B1_GPIO =0 , +GPIO7B1_UART3GPS_CTSN , +GPIO7B1_GPS_RFCLK , +GPIO7B1_GPST1_CLK , + +GPIO7B0_SHIFT =0 , +GPIO7B0_MASK =3 , +GPIO7B0_GPIO =0 , +GPIO7B0_UART3GPS_SOUT , +GPIO7B0_GPS_SIG , +GPIO7B0_HSADCT1_DATA1 , +}; + +/* GRF_GPIO7CL_IOMUX */ +enum { +GPIO7C3_SHIFT =12 , +GPIO7C3_MASK =3 , +GPIO7C3_GPIO =0 , +GPIO7C3_I2C5HDMI_SDA , +GPIO7C3_EDPHDMII2C_SDA , + +GPIO7C2_SHIFT =8 , +GPIO7C2_MASK =1 , +GPIO7C2_GPIO =0 , +GPIO7C2_I2C4TP_SCL , + +GPIO7C1_SHIFT =4 , +GPIO7C1_MASK =1 , +GPIO7C1_GPIO =0 , +GPIO7C1_I2C4TP_SDA , + +GPIO7C0_SHIFT =0 , +GPIO7C0_MASK =3 , +GPIO7C0_GPIO =0 , +GPIO7C0_ISP_FLASHTRIGIN , +GPIO7C0_EDPHDMI_CECINOUTT1 , +}; + +/* GRF_GPIO7CH_IOMUX */ +enum { +GPIO7C7_SHIFT =12 , +GPIO7C7_MASK =7 , +GPIO7C7_GPIO =0 , +GPIO7C7_UART2DBG_SOUT , +GPIO7C7_UART2DBG_SIROUT , +GPIO7C7_PWM_3 , +GPIO7C7_EDPHDMI_CECINOUT , + +GPIO7C6_SHIFT =8 , +GPIO7C6_MASK =3 , +GPIO7C6_GPIO =0 , +GPIO7C6_UART2DBG_SIN , +GPIO7C6_UART2DBG_SIRIN , +GPIO7C6_PWM_2 , + +GPIO7C4_SHIFT =0 , +GPIO7C4_MASK =3 , +GPIO7C4_GPIO =0 , +GPIO7C4_I2C5HDMI_SCL , +GPIO7C4_EDPHDMII2C_SCL , +}; + +/* GRF_GPIO8A_IOMUX */ +enum { +GPIO8A7_SHIFT =14 , +GPIO8A7_MASK =3 , +GPIO8A7_GPIO =0 , +GPIO8A7_SPI2_CSN0 , +GPIO8A7_SC_DETECT , +GPIO8A7_RESERVE , + +GPIO8A6_SHIFT =12 , +GPIO8A6_MASK =3 , +GPIO8A6_GPIO =0 , +GPIO8A6_SPI2_CLK , +GPIO8A6_SC_IO , +GPIO8A6_RESERVE , + +GPIO8A5_SHIFT =10 , +GPIO8A5_MASK =3 , +GPIO8A5_GPIO =0 , +GPIO8A5_I2C2SENSOR_SCL , +GPIO8A5_SC_CLK , + +GPIO8A4_SHIFT =8 , +GPIO8A4_MASK =3 , +GPIO8A4_GPIO =0 , +GPIO8A4_I2C2SENSOR_SDA , +GPIO8A4_SC_RST , + +GPIO8A3_SHIFT =6 , +GPIO8A3_MASK =3 , +GPIO8A3_GPIO =0 , +GPIO8A3_SPI2_CSN1 , +GPIO8A3_SC_IOT1 , + +GPIO8A2_SHIFT =4 , +GPIO8A2_MASK =1 , +GPIO8A2_GPIO =0 , +GPIO8A2_SC_DETECTT1 , + +GPIO8A1_SHIFT =2 , +GPIO8A1_MASK =3 , +GPIO8A1_GPIO =0 , +GPIO8A1_PS2_DATA , +GPIO8A1_SC_VCC33V , + +GPIO8A0_SHIFT =0 , +GPIO8A0_MASK =3 , +GPIO8A0_GPIO =0 , +GPIO8A0_PS2_CLK , +GPIO8A0_SC_VCC18V , +}; + +/* GRF_GPIO8B_IOMUX */ +enum { +GPIO8B1_SHIFT =2 , +GPIO8B1_MASK =3 , +GPIO8B1_GPIO =0 , +GPIO8B1_SPI2_TXD , +GPIO8B1_SC_CLK , + +GPIO8B0_SHIFT =0 , +GPIO8B0_MASK =3 , +GPIO8B0_GPIO =0 , +GPIO8B0_SPI2_RXD , +GPIO8B0_SC_RST , +}; + +/* GRF_SOC_CON0 */ +enum { +PAUSE_MMC_PERI_SHIFT =0xf , +PAUSE_MMC_PERI_MASK =1 , + +PAUSE_EMEM_PERI_SHIFT =0xe , +PAUSE_EMEM_PERI_MASK =1 , + +PAUSE_USB_PERI_SHIFT =0xd , +PAUSE_USB_PERI_MASK =1 , + +GRF_FORCE_JTAG_SHIFT =0xc , +GRF_FORCE_JTAG_MASK =1 , + +GRF_CORE_IDLE_REQ_MODE_SEL1_SHIFT =0xb , +GRF_CORE_IDLE_REQ_MODE_SEL1_MASK =1 , + +GRF_CORE_IDLE_REQ_MODE_SEL0_SHIFT =0xa , +GRF_CORE_IDLE_REQ_MODE_SEL0_MASK =1 , + +DDR1_16BIT_EN_SHIFT =9 , +DDR1_16BIT_EN_MASK =1 , + +DDR0_16BIT_EN_SHIFT =8 , +DDR0_16BIT_EN_MASK =1 , + +VCODEC_SHIFT =7 , +VCODEC_MASK =1 , +VCODEC_SELECT_VEPU_ACLK =0 , +VCODEC_SELECT_VDPU_ACLK , + +UPCTL1_C_ACTIVE_IN_SHIFT =6 , +UPCTL1_C_ACTIVE_IN_MASK =1 , +UPCTL1_C_ACTIVE_IN_MAY =0 , +UPCTL1_C_ACTIVE_IN_WILL , + +UPCTL0_C_ACTIVE_IN_SHIFT =5 , +UPCTL0_C_ACTIVE_IN_MASK =1 , +UPCTL0_C_ACTIVE_IN_MAY =0 , +UPCTL0_C_ACTIVE_IN_WILL , + +MSCH1_MAINDDR3_SHIFT =4 , +MSCH1_MAINDDR3_MASK =1 , +MSCH1_MAINDDR3_DDR3 =1 , + +MSCH0_MAINDDR3_SHIFT =3 , +MSCH0_MAINDDR3_MASK =1 , +MSCH0_MAINDDR3_DDR3 =1 , + +MSCH1_MAINPARTIALPOP_SHIFT =2 , +MSCH1_MAINPARTIALPOP_MASK =1 , + +MSCH0_MAINPARTIALPOP_SHIFT =1 , +MSCH0_MAINPARTIALPOP_MASK =1 , +}; + +/* GRF_SOC_CON2 */ +enum { +UPCTL1_LPDDR3_ODT_EN_SHIFT =0xd , +UPCTL1_LPDDR3_ODT_EN_MASK =1 , +UPCTL1_LPDDR3_ODT_EN_ODT =1 , + +UPCTL1_BST_DIABLE_SHIFT =0xc , +UPCTL1_BST_DIABLE_MASK =1 , +UPCTL1_BST_DIABLE_DISABLE =1 , + +LPDDR3_EN1_SHIFT =0xb , +LPDDR3_EN1_MASK =1 , +LPDDR3_EN1_LPDDR3 =1 , + +UPCTL0_LPDDR3_ODT_EN_SHIFT =0xa , +UPCTL0_LPDDR3_ODT_EN_MASK =1 , +UPCTL0_LPDDR3_ODT_EN_ODT_ENABLE =1 , + +UPCTL0_BST_DIABLE_SHIFT =9 , +UPCTL0_BST_DIABLE_MASK =1 , +UPCTL0_BST_DIABLE_DISABLE =1 , + +LPDDR3_EN0_SHIFT =8 , +LPDDR3_EN0_MASK =1 , +LPDDR3_EN0_LPDDR3 =1 , + +GRF_POC_FLASH0_CTRL_SHIFT =7 , +GRF_POC_FLASH0_CTRL_MASK =1 , +GRF_POC_FLASH0_CTRL_GPIO3C_3 =0 , +GRF_POC_FLASH0_CTRL_GRF_IO_VSEL , + +SIMCARD_MUX_SHIFT =6 , +SIMCARD_MUX_MASK =1 , +SIMCARD_MUX_USE_A =1 , +SIMCARD_MUX_USE_B =0 , + +GRF_SPDIF_2CH_EN_SHIFT =1 , +GRF_SPDIF_2CH_EN_MASK =1 , +GRF_SPDIF_2CH_EN_8CH =0 , +GRF_SPDIF_2CH_EN_2CH , + +PWM_SHIFT =0 , +PWM_MASK =1 , +PWM_RK =1 , +PWM_PWM =0 , +}; + +#endif
arch/arm/include/asm/arch-rockchip/pmu_rk3288.h new file +89 -0
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Signature · 1 line
2.5.0.457.gab17608
PATCH v4 23/33 rockchip: rk3288: Add SoC reset driver
In reply to Simon GlassWe can reset the SoC using some CRU (clock/reset unit) registers. Add support for this.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/rk3288/Makefile | 7 +++++ arch/arm/mach-rockchip/rk3288/reset_rk3288.c | 47 ++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3288/Makefile create mode 100644 arch/arm/mach-rockchip/rk3288/reset_rk3288.c
arch/arm/mach-rockchip/rk3288/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +# +# Copyright (c) 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += reset_rk3288.o
arch/arm/mach-rockchip/rk3288/reset_rk3288.c new file +47 -0
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Signature · 1 line
2.5.0.457.gab17608
PATCH v4 24/33 rockchip: rk3288: Add a simple syscon driver
In reply to Simon GlassAdd a driver that provides access to system controllers.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/rk3288/Makefile | 1 + arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
arch/arm/mach-rockchip/rk3288/Makefile +1 -0
@@ -5,3 +5,4 @@ # obj-y += reset_rk3288.o +obj-y += syscon_rk3288.o
arch/arm/mach-rockchip/rk3288/syscon_rk3288.c new file +25 -0
@@ -0,0 +1,25 @@ +/* +* Copyright (C) 2015 Google, Inc +* Written by Simon Glass <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> + +static const struct udevice_id rk3288_syscon_ids[] = { + { .compatible ="rockchip,rk3288-noc" , .data =ROCKCHIP_SYSCON_NOC }, + { .compatible ="rockchip,rk3288-grf" , .data =ROCKCHIP_SYSCON_GRF }, + { .compatible ="rockchip,rk3288-sgrf" , .data =ROCKCHIP_SYSCON_SGRF }, + { .compatible ="rockchip,rk3288-pmu" , .data =ROCKCHIP_SYSCON_PMU }, + { } +}; + +U_BOOT_DRIVER (syscon_rk3288) = { + .name ="rk3288_syscon" , + .id =UCLASS_SYSCON , + .of_match = rk3288_syscon_ids, +};
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 25/33 rockchip: rk3288: Add pinctrl driver
In reply to Simon GlassAdd a driver which supports pin multiplexing setup for the most commonly used peripherals.
---
Changes in v4:
- Add a set_state_simple() method
- Rename pinctrl.h to dm/pinctrl.h
Changes in v3: None
Changes in v2: None
drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/rockchip/Makefile | 8 + drivers/pinctrl/rockchip/pinctrl_rk3288.c | 441 ++++++++++++++++++++++++++++++ 4 files changed, 459 insertions(+) create mode 100644 drivers/pinctrl/rockchip/Makefile create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3288.c
drivers/pinctrl/Kconfig +9 -0
@@ -58,6 +58,15 @@ config SPL_PINCONF if PINCTRL || SPL_PINCTRL +config ROCKCHIP_PINCTRL + bool "Rockchip pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip SoCs. The driver is + controlled by a device tree node which contains both the GPIO + definitions and pin control functions for each available multiplex + function. + config PINCTRL_SANDBOX bool "Sandbox pinctrl driver"
drivers/pinctrl/Makefile +1 -0
@@ -1,4 +1,5 @@ obj-y += pinctrl-uclass.o obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
drivers/pinctrl/rockchip/Makefile new file +8 -0
@@ -0,0 +1,8 @@ +# +# Copyright (c) 2015 Google, Inc +# Written by Simon Glass <[email protected]> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ROCKCHIP_PINCTRL) += pinctrl_rk3288.o
drivers/pinctrl/rockchip/pinctrl_rk3288.c new file +441 -0
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Signature · 1 line
2.5.0.457.gab17608
PATCH v4 26/33 rockchip: rk3288: Add SDRAM init
In reply to Simon GlassAdd code to set up the SDRAM in SPL, ready for loading U-Boot. This uses device tree for configuration so should be able to support other RAM configurations. It may be possible to generalise the code to support other SoCs at some point.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/ddr_rk3288.h | 484 +++++++++++++ arch/arm/include/asm/arch-rockchip/sdram.h | 92 +++ arch/arm/mach-rockchip/rk3288/Makefile | 1 + arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 878 ++++++++++++++++++++++++ 4 files changed, 1455 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/sdram.h create mode 100644 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
arch/arm/include/asm/arch-rockchip/ddr_rk3288.h new file +484 -0
@@ -0,0 +1,484 @@ +/* +* (C) Copyright 2015 Google, Inc +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef _ASM_ARCH_DDR_RK3288_H +#define _ASM_ARCH_DDR_RK3288_H + +struct rk3288_ddr_pctl { +u32 scfg; +u32 sctl; +u32 stat; +u32 intrstat; +u32 reserved0[12 ]; +u32 mcmd; +u32 powctl; +u32 powstat; +u32 cmdtstat; +u32 tstaten; +u32 reserved1[3 ]; +u32 mrrcfg0; +u32 mrrstat0; +u32 mrrstat1; +u32 reserved2[4 ]; +u32 mcfg1; +u32 mcfg; +u32 ppcfg; +u32 mstat; +u32 lpddr2zqcfg; +u32 reserved3; +u32 dtupdes; +u32 dtuna; +u32 dtune; +u32 dtuprd0; +u32 dtuprd1; +u32 dtuprd2; +u32 dtuprd3; +u32 dtuawdt; +u32 reserved4[3 ]; +u32 togcnt1u; +u32 tinit; +u32 trsth; +u32 togcnt100n; +u32 trefi; +u32 tmrd; +u32 trfc; +u32 trp; +u32 trtw; +u32 tal; +u32 tcl; +u32 tcwl; +u32 tras; +u32 trc; +u32 trcd; +u32 trrd; +u32 trtp; +u32 twr; +u32 twtr; +u32 texsr; +u32 txp; +u32 txpdll; +u32 tzqcs; +u32 tzqcsi; +u32 tdqs; +u32 tcksre; +u32 tcksrx; +u32 tcke; +u32 tmod; +u32 trstl; +u32 tzqcl; +u32 tmrr; +u32 tckesr; +u32 tdpd; +u32 reserved5[14 ]; +u32 ecccfg; +u32 ecctst; +u32 eccclr; +u32 ecclog; +u32 reserved6[28 ]; +u32 dtuwactl; +u32 dturactl; +u32 dtucfg; +u32 dtuectl; +u32 dtuwd0; +u32 dtuwd1; +u32 dtuwd2; +u32 dtuwd3; +u32 dtuwdm; +u32 dturd0; +u32 dturd1; +u32 dturd2; +u32 dturd3; +u32 dtulfsrwd; +u32 dtulfsrrd; +u32 dtueaf; +u32 dfitctrldelay; +u32 dfiodtcfg; +u32 dfiodtcfg1; +u32 dfiodtrankmap; +u32 dfitphywrdata; +u32 dfitphywrlat; +u32 reserved7[2 ]; +u32 dfitrddataen; +u32 dfitphyrdlat; +u32 reserved8[2 ]; +u32 dfitphyupdtype0; +u32 dfitphyupdtype1; +u32 dfitphyupdtype2; +u32 dfitphyupdtype3; +u32 dfitctrlupdmin; +u32 dfitctrlupdmax; +u32 dfitctrlupddly; +u32 reserved9; +u32 dfiupdcfg; +u32 dfitrefmski; +u32 dfitctrlupdi; +u32 reserved10[4 ]; +u32 dfitrcfg0; +u32 dfitrstat0; +u32 dfitrwrlvlen; +u32 dfitrrdlvlen; +u32 dfitrrdlvlgateen; +u32 dfiststat0; +u32 dfistcfg0; +u32 dfistcfg1; +u32 reserved11; +u32 dfitdramclken; +u32 dfitdramclkdis; +u32 dfistcfg2; +u32 dfistparclr; +u32 dfistparlog; +u32 reserved12[3 ]; +u32 dfilpcfg0; +u32 reserved13[3 ]; +u32 dfitrwrlvlresp0; +u32 dfitrwrlvlresp1; +u32 dfitrwrlvlresp2; +u32 dfitrrdlvlresp0; +u32 dfitrrdlvlresp1; +u32 dfitrrdlvlresp2; +u32 dfitrwrlvldelay0; +u32 dfitrwrlvldelay1; +u32 dfitrwrlvldelay2; +u32 dfitrrdlvldelay0; +u32 dfitrrdlvldelay1; +u32 dfitrrdlvldelay2; +u32 dfitrrdlvlgatedelay0; +u32 dfitrrdlvlgatedelay1; +u32 dfitrrdlvlgatedelay2; +u32 dfitrcmd; +u32 reserved14[46 ]; +u32 ipvr; +u32 iptr; +}; +check_member (rk3288_ddr_pctl, iptr,0x03fc ); + +struct rk3288_ddr_publ_datx { +u32 dxgcr; +u32 dxgsr[2 ]; +u32 dxdllcr; +u32 dxdqtr; +u32 dxdqstr; +u32 reserved[10 ]; +}; + +struct rk3288_ddr_publ { +u32 ridr; +u32 pir; +u32 pgcr; +u32 pgsr; +u32 dllgcr; +u32 acdllcr; +u32 ptr[3 ]; +u32 aciocr; +u32 dxccr; +u32 dsgcr; +u32 dcr; +u32 dtpr[3 ]; +u32 mr[4 ]; +u32 odtcr; +u32 dtar; +u32 dtdr[2 ]; +u32 reserved1[24 ]; +u32 dcuar; +u32 dcudr; +u32 dcurr; +u32 dculr; +u32 dcugcr; +u32 dcutpr; +u32 dcusr[2 ]; +u32 reserved2[8 ]; +u32 bist[17 ]; +u32 reserved3[15 ]; +u32 zq0cr[2 ]; +u32 zq0sr[2 ]; +u32 zq1cr[2 ]; +u32 zq1sr[2 ]; +u32 zq2cr[2 ]; +u32 zq2sr[2 ]; +u32 zq3cr[2 ]; +u32 zq3sr[2 ]; +struct rk3288_ddr_publ_datx datx8[4 ]; +}; +check_member (rk3288_ddr_publ, datx8[3 ].dxdqstr,0x0294 ); + +struct rk3288_msch { +u32 coreid; +u32 revisionid; +u32 ddrconf; +u32 ddrtiming; +u32 ddrmode; +u32 readlatency; +u32 reserved1[8 ]; +u32 activate; +u32 devtodev; +}; +check_member (rk3288_msch, devtodev,0x003c ); + +/* PCT_DFISTCFG0 */ +#define DFI_INIT_START (1 << 0) + +/* PCT_DFISTCFG1 */ +#define DFI_DRAM_CLK_SR_EN (1 << 0) +#define DFI_DRAM_CLK_DPD_EN (1 << 1) + +/* PCT_DFISTCFG2 */ +#define DFI_PARITY_INTR_EN (1 << 0) +#define DFI_PARITY_EN (1 << 1) + +/* PCT_DFILPCFG0 */ +#define TLP_RESP_TIME_SHIFT 16 +#define LP_SR_EN (1 << 8) +#define LP_PD_EN (1 << 0) + +/* PCT_DFITCTRLDELAY */ +#define TCTRL_DELAY_TIME_SHIFT 0 + +/* PCT_DFITPHYWRDATA */ +#define TPHY_WRDATA_TIME_SHIFT 0 + +/* PCT_DFITPHYRDLAT */ +#define TPHY_RDLAT_TIME_SHIFT 0 + +/* PCT_DFITDRAMCLKDIS */ +#define TDRAM_CLK_DIS_TIME_SHIFT 0 + +/* PCT_DFITDRAMCLKEN */ +#define TDRAM_CLK_EN_TIME_SHIFT 0 + +/* PCTL_DFIODTCFG */ +#define RANK0_ODT_WRITE_SEL (1 << 3) +#define RANK1_ODT_WRITE_SEL (1 << 11) + +/* PCTL_DFIODTCFG1 */ +#define ODT_LEN_BL8_W_SHIFT 16 + +/* PUBL_ACDLLCR */ +#define ACDLLCR_DLLDIS (1 << 31) +#define ACDLLCR_DLLSRST (1 << 30) + +/* PUBL_DXDLLCR */ +#define DXDLLCR_DLLDIS (1 << 31) +#define DXDLLCR_DLLSRST (1 << 30) + +/* PUBL_DLLGCR */ +#define DLLGCR_SBIAS (1 << 30) + +/* PUBL_DXGCR */ +#define DQSRTT (1 << 9) +#define DQRTT (1 << 10) + +/* PIR */ +#define PIR_INIT (1 << 0) +#define PIR_DLLSRST (1 << 1) +#define PIR_DLLLOCK (1 << 2) +#define PIR_ZCAL (1 << 3) +#define PIR_ITMSRST (1 << 4) +#define PIR_DRAMRST (1 << 5) +#define PIR_DRAMINIT (1 << 6) +#define PIR_QSTRN (1 << 7) +#define PIR_RVTRN (1 << 8) +#define PIR_ICPC (1 << 16) +#define PIR_DLLBYP (1 << 17) +#define PIR_CTLDINIT (1 << 18) +#define PIR_CLRSR (1 << 28) +#define PIR_LOCKBYP (1 << 29) +#define PIR_ZCALBYP (1 << 30) +#define PIR_INITBYP (1u << 31) + +/* PGCR */ +#define PGCR_DFTLMT_SHIFT 3 +#define PGCR_DFTCMP_SHIFT 2 +#define PGCR_DQSCFG_SHIFT 1 +#define PGCR_ITMDMD_SHIFT 0 + +/* PGSR */ +#define PGSR_IDONE (1 << 0) +#define PGSR_DLDONE (1 << 1) +#define PGSR_ZCDONE (1 << 2) +#define PGSR_DIDONE (1 << 3) +#define PGSR_DTDONE (1 << 4) +#define PGSR_DTERR (1 << 5) +#define PGSR_DTIERR (1 << 6) +#define PGSR_DFTERR (1 << 7) +#define PGSR_RVERR (1 << 8) +#define PGSR_RVEIRR (1 << 9) + +/* PTR0 */ +#define PRT_ITMSRST_SHIFT 18 +#define PRT_DLLLOCK_SHIFT 6 +#define PRT_DLLSRST_SHIFT 0 + +/* PTR1 */ +#define PRT_DINIT0_SHIFT 0 +#define PRT_DINIT1_SHIFT 19 + +/* PTR2 */ +#define PRT_DINIT2_SHIFT 0 +#define PRT_DINIT3_SHIFT 17 + +/* DCR */ +#define DDRMD_LPDDR 0 +#define DDRMD_DDR 1 +#define DDRMD_DDR2 2 +#define DDRMD_DDR3 3 +#define DDRMD_LPDDR2_LPDDR3 4 +#define DDRMD_MASK 7 +#define DDRMD_SHIFT 0 +#define PDQ_MASK 7 +#define PDQ_SHIFT 4 + +/* DXCCR */ +#define DQSNRES_MASK 0xf +#define DQSNRES_SHIFT 8 +#define DQSRES_MASK 0xf +#define DQSRES_SHIFT 4 + +/* DTPR */ +#define TDQSCKMAX_SHIFT 27 +#define TDQSCKMAX_MASK 7 +#define TDQSCK_SHIFT 24 +#define TDQSCK_MASK 7 + +/* DSGCR */ +#define DQSGX_SHIFT 5 +#define DQSGX_MASK 7 +#define DQSGE_SHIFT 8 +#define DQSGE_MASK 7 + +/* SCTL */ +#define INIT_STATE 0 +#define CFG_STATE 1 +#define GO_STATE 2 +#define SLEEP_STATE 3 +#define WAKEUP_STATE 4 + +/* STAT */ +#define LP_TRIG_SHIFT 4 +#define LP_TRIG_MASK 7 +#define PCTL_STAT_MSK 7 +#define INIT_MEM 0 +#define CONFIG 1 +#define CONFIG_REQ 2 +#define ACCESS 3 +#define ACCESS_REQ 4 +#define LOW_POWER 5 +#define LOW_POWER_ENTRY_REQ 6 +#define LOW_POWER_EXIT_REQ 7 + +/* ZQCR*/ +#define PD_OUTPUT_SHIFT 0 +#define PU_OUTPUT_SHIFT 5 +#define PD_ONDIE_SHIFT 10 +#define PU_ONDIE_SHIFT 15 +#define ZDEN_SHIFT 28 + +/* DDLGCR */ +#define SBIAS_BYPASS (1 << 23) + +/* MCFG */ +#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24 +#define PD_IDLE_SHIFT 8 +#define MDDR_EN (2 << 22) +#define LPDDR2_EN (3 << 22) +#define DDR2_EN (0 << 5) +#define DDR3_EN (1 << 5) +#define LPDDR2_S2 (0 << 6) +#define LPDDR2_S4 (1 << 6) +#define MDDR_LPDDR2_BL_2 (0 << 20) +#define MDDR_LPDDR2_BL_4 (1 << 20) +#define MDDR_LPDDR2_BL_8 (2 << 20) +#define MDDR_LPDDR2_BL_16 (3 << 20) +#define DDR2_DDR3_BL_4 0 +#define DDR2_DDR3_BL_8 1 +#define TFAW_SHIFT 18 +#define PD_EXIT_SLOW (0 << 17) +#define PD_EXIT_FAST (1 << 17) +#define PD_TYPE_SHIFT 16 +#define BURSTLENGTH_SHIFT 20 + +/* POWCTL */ +#define POWER_UP_START (1 << 0) + +/* POWSTAT */ +#define POWER_UP_DONE (1 << 0) + +/* MCMD */ +enum { +DESELECT_CMD =0 , +PREA_CMD , +REF_CMD , +MRS_CMD , +ZQCS_CMD , +ZQCL_CMD , +RSTL_CMD , +MRR_CMD =8 , +DPDE_CMD , +}; + +#define LPDDR2_MA_SHIFT 4 +#define LPDDR2_MA_MASK 0xff +#define LPDDR2_OP_SHIFT 12 +#define LPDDR2_OP_MASK 0xff + +#define START_CMD (1u << 31) + +/* DEVTODEV */ +#define BUSWRTORD_SHIFT 4 +#define BUSRDTOWR_SHIFT 2 +#define BUSRDTORD_SHIFT 0 + +/* mr1 for ddr3 */ +#define DDR3_DLL_DISABLE 1 + +/* +*TODO([email protected]): We use a PMU register to store SDRAM information for +* passing from SPL to U-Boot. It would probably be better to use a normal C +* structure in SRAM. +* +* sys_reg bitfield struct +* [31] row_3_4_ch1 +* [30] row_3_4_ch0 +* [29:28] chinfo +* [27] rank_ch1 +* [26:25] col_ch1 +* [24] bk_ch1 +* [23:22] cs0_row_ch1 +* [21:20] cs1_row_ch1 +* [19:18] bw_ch1 +* [17:16] dbw_ch1; +* [15:13] ddrtype +* [12] channelnum +* [11] rank_ch0 +* [10:9] col_ch0 +* [8] bk_ch0 +* [7:6] cs0_row_ch0 +* [5:4] cs1_row_ch0 +* [3:2] bw_ch0 +* [1:0] dbw_ch0 +*/ +#define SYS_REG_DDRTYPE_SHIFT 13 +#define SYS_REG_DDRTYPE_MASK 7 +#define SYS_REG_NUM_CH_SHIFT 12 +#define SYS_REG_NUM_CH_MASK 1 +#define SYS_REG_ROW_3_4_SHIFT (ch) (30 + (ch)) +#define SYS_REG_ROW_3_4_MASK 1 +#define SYS_REG_CHINFO_SHIFT (ch) (28 + (ch)) +#define SYS_REG_RANK_SHIFT (ch) (11 + (ch) * 16) +#define SYS_REG_RANK_MASK 1 +#define SYS_REG_COL_SHIFT (ch) (9 + (ch) * 16) +#define SYS_REG_COL_MASK 3 +#define SYS_REG_BK_SHIFT (ch) (8 + (ch) * 16) +#define SYS_REG_BK_MASK 1 +#define SYS_REG_CS0_ROW_SHIFT (ch) (6 + (ch) * 16) +#define SYS_REG_CS0_ROW_MASK 3 +#define SYS_REG_CS1_ROW_SHIFT (ch) (4 + (ch) * 16) +#define SYS_REG_CS1_ROW_MASK 3 +#define SYS_REG_BW_SHIFT (ch) (2 + (ch) * 16) +#define SYS_REG_BW_MASK 3 +#define SYS_REG_DBW_SHIFT (ch) ((ch) * 16) +#define SYS_REG_DBW_MASK 3 + +#endif
arch/arm/include/asm/arch-rockchip/sdram.h new file +92 -0
92 lines not on this page · raw message
arch/arm/mach-rockchip/rk3288/Makefile +1 -0
@@ -5,4 +5,5 @@ # obj-y += reset_rk3288.o +obj-y += sdram_rk3288.o obj-y += syscon_rk3288.o
arch/arm/mach-rockchip/rk3288/sdram_rk3288.c new file +878 -0
878 lines not on this page · raw message
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 27/33 rockchip: Add an MMC driver
In reply to Simon GlassAdd an MMC driver which supports RK3288, but may also support other SoCs. It uses the Designware MMC device.
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/mmc/Kconfig | 9 +++++ drivers/mmc/Makefile | 1 + drivers/mmc/rockchip_mmc.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 108 insertions(+) create mode 100644 drivers/mmc/rockchip_mmc.c
drivers/mmc/Kconfig +9 -0
@@ -10,6 +10,15 @@ config DM_MMC appear as block devices in U-Boot and can support filesystems such as EXT4 and FAT. +config ROCKCHIP_MMC + bool "Rockchip SD/MMC controller support" + depends on DM && OF_CONTROL + help + This enables support for the Rockchip SD/MMM controller, which is + based on Designware IP. The device is compatible with SD 3.0, + SDIO 3.0 and MMC 4.5 and supports common eMMC chips as well as + removeable SD and micro-SD cards. + config SH_SDHI bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support" depends on RMOBILE
drivers/mmc/Makefile +1 -0
@@ -29,6 +29,7 @@ obj-$(CONFIG_MXS_MMC) += mxsmmc.o obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o obj-$(CONFIG_X86) += pci_mmc.o obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o +obj-$(CONFIG_ROCKCHIP_MMC) += rockchip_mmc.o obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o obj-$(CONFIG_S3C_SDI) += s3c_sdi.o obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
drivers/mmc/rockchip_mmc.c new file +98 -0
98 lines not on this page · raw message
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 27/33 rockchip: Add an MMC driver
Hi, Simon.
Quoted 2 lines · Simon Glass
Add an MMC driver which supports RK3288, but may also support other SoCs. It uses the Designware MMC device.
It's based on designware controller. then how about using "_dw_mmc" as postfix?
Quoted 20 lines
Signed-off-by Simon Glass <[email protected]>---
Changes in v4: None
Changes in v3: None
Changes in v2: Nonedrivers/mmc/Kconfig | 9 +++++ drivers/mmc/Makefile | 1 + drivers/mmc/rockchip_mmc.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 108 insertions(+) create mode 100644 drivers/mmc/rockchip_mmc.cdrivers/mmc/Kconfig +0
-0@@ -10,6 +10,15 @@ config DM_MMC appear as block devices in U-Boot and can support filesystems such
drivers/mmc/Kconfig config DM_MMC · line 20
Quoted 10 lines
drivers/mmc/Kconfig +8
-0as EXT4 and FAT. +config ROCKCHIP_MMC + bool "Rockchip SD/MMC controller support" + depends on DM && OF_CONTROL + help + This enables support for the Rockchip SD/MMM controller, which is + based on Designware IP. The device is compatible with SD 3.0, + SDIO 3.0 and MMC 4.5 and supports common eMMC chips as well as + removeable SD and micro-SD cards.
I think it's not good that described spec version.
In future, Rockchip can support upper version than SD3.0, SDIO3.0 and MMC4.5.
Quoted 37 lines
drivers/mmc/Kconfig +1
-0+ config SH_SDHI bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support" depends on RMOBILEdrivers/mmc/Makefile +1
-0@@ -29,6 +29,7 @@ obj-$(CONFIG_MXS_MMC) += mxsmmc.o obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o obj-$(CONFIG_X86) += pci_mmc.o obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o +obj-$(CONFIG_ROCKCHIP_MMC) += rockchip_mmc.o obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o obj-$(CONFIG_S3C_SDI) += s3c_sdi.o obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.odrivers/mmc/rockchip_mmc.c new file +15
-0@@ -0,0 +1,98 @@ +/* +* Copyright (c) 2013 Google, Inc +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dwmmc.h> +#include <errno.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/periph.h> +#include <linux/err.h>
drivers/mmc/rockchip_mmc.c line 25
Quoted 10 lines
drivers/mmc/rockchip_mmc.c new file +10
-0+ +DECLARE_GLOBAL_DATA_PTR ; + +struct rockchip_mmc_priv { +struct udevice *clk; +struct rk3288_grf *grf; +struct dwmci_host host; +}; + +static uint rockchip_mmc_get_mmc_clk (struct dwmci_host *host,uint freq)
Well, how about using "dwmci" instead of "mmc". it's just my preference. :) (Since it has used function name as "dwmci" in other dwmmc file.)
Quoted 74 lines
drivers/mmc/rockchip_mmc.c new file +73
-0+{ +struct udevice *dev = host->priv; +struct rockchip_mmc_priv *priv =dev_get_priv (dev); +int ret; + + ret =clk_set_periph_rate (priv->clk,PERIPH_ID_SDMMC0 + host->dev_index, + freq); +if (ret <0 ) { +debug ("%s: err=%d\n" , __func__, ret); +return ret; + } + +return freq; +} + +static int rockchip_mmc_ofdata_to_platdata (struct udevice *dev) +{ +struct rockchip_mmc_priv *priv =dev_get_priv (dev); +struct dwmci_host *host = &priv->host; + + host->name = dev->name; + host->ioaddr = (void *)dev_get_addr (dev); + host->buswidth =fdtdec_get_int (gd->fdt_blob, dev->of_offset, +"bus-width" ,4 ); + host->get_mmc_clk = rockchip_mmc_get_mmc_clk; + host->priv = dev; + +/* TODO(sjg at chromium.org): Remove the need for this hack */ + host->dev_index = (ulong )host->ioaddr ==0xff0f0000 ?0 :1 ; + +return 0 ; +} + +int rockchip_mmc_probe (struct udevice *dev) +{ +struct mmc_uclass_priv *upriv =dev_get_uclass_priv (dev); +struct rockchip_mmc_priv *priv =dev_get_priv (dev); +struct dwmci_host *host = &priv->host; +u32 minmax[2 ]; +int ret; + + priv->grf =syscon_get_first_range (ROCKCHIP_SYSCON_GRF ); +if (IS_ERR (priv->grf)) +return PTR_ERR (priv->grf); + ret =uclass_get_device (UCLASS_CLK ,CLK_GENERAL , &priv->clk); +if (ret) +return ret; + + ret =fdtdec_get_int_array (gd->fdt_blob, dev->of_offset, +"clock-freq-min-max" , minmax,2 ); +if (!ret) + ret =add_dwmci (host, minmax[1 ], minmax[0 ]); +if (ret) +return ret; + + upriv->mmc = host->mmc; + +return 0 ; +} + +static const struct udevice_id rockchip_mmc_ids[] = { + { .compatible ="rockchip,rk3288-dw-mshc" }, + { } +}; + +U_BOOT_DRIVER (rockchip_mmc_drv) = { + .name ="rockchip_mmc" , + .id =UCLASS_MMC , + .of_match = rockchip_mmc_ids, + .ofdata_to_platdata = rockchip_mmc_ofdata_to_platdata, + .probe = rockchip_mmc_probe, + .priv_auto_alloc_size =sizeof (struct dwmci_host ), +};
PATCH v4 27/33 rockchip: Add an MMC driver
Hi Jaehoon,
Quoted 8 lines · Jaehoon Chung
Hi, Simon.
Quoted 2 lines · Simon Glass
Add an MMC driver which supports RK3288, but may also support other SoCs. It uses the Designware MMC device.
It's based on designware controller. then how about using "
_dw_mmc" as postfix?
OK done
Quoted 23 lines
Quoted 23 lines
Signed-off-by Simon Glass <[email protected]>---
Changes in v4: None
Changes in v3: None
Changes in v2: Nonedrivers/mmc/Kconfig | 9 +++++ drivers/mmc/Makefile | 1 + drivers/mmc/rockchip_mmc.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 108 insertions(+) create mode 100644 drivers/mmc/rockchip_mmc.cdrivers/mmc/Kconfig +0
-0@@ -10,6 +10,15 @@ config DM_MMC appear as block devices in U-Boot and can support filesystems such as EXT4 and FAT.
Quoted 11 lines
drivers/mmc/Kconfig config DM_MMC · line 20
Quoted 8 lines
drivers/mmc/Kconfig +8
-0+config ROCKCHIP_MMC + bool "Rockchip SD/MMC controller support" + depends on DM && OF_CONTROL + help + This enables support for the Rockchip SD/MMM controller, which is + based on Designware IP. The device is compatible with SD 3.0, + SDIO 3.0 and MMC 4.5 and supports common eMMC chips as well as + removeable SD and micro-SD cards.I think it's not good that described spec version.
In future, Rockchip can support upper version than SD3.0, SDIO3.0 and MMC4.5.
Do you mean that Rockchip can support MMC 5, for example? I tweaked the help a little based on your comments.
Quoted 43 lines
Quoted 43 lines
drivers/mmc/Kconfig +1
-0+ config SH_SDHI bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support" depends on RMOBILEdrivers/mmc/Makefile +1
-0@@ -29,6 +29,7 @@ obj-$(CONFIG_MXS_MMC) += mxsmmc.o obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o obj-$(CONFIG_X86) += pci_mmc.o obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o +obj-$(CONFIG_ROCKCHIP_MMC) += rockchip_mmc.o obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o obj-$(CONFIG_S3C_SDI) += s3c_sdi.o obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.odrivers/mmc/rockchip_mmc.c new file +20
-0@@ -0,0 +1,98 @@ +/* +* Copyright (c) 2013 Google, Inc +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dwmmc.h> +#include <errno.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/periph.h> +#include <linux/err.h> + +DECLARE_GLOBAL_DATA_PTR ; + +struct rockchip_mmc_priv { +struct udevice *clk;
Quoted 8 lines
drivers/mmc/rockchip_mmc.c line 25
Quoted 5 lines
drivers/mmc/rockchip_mmc.c new file +5
-0+struct rk3288_grf *grf; +struct dwmci_host host; +}; + +static uint rockchip_mmc_get_mmc_clk (struct dwmci_host *host,uint freq)Well, how about using "dwmci" instead of "mmc". it's just my preference. :) (Since it has used function name as "dwmci" in other dwmmc file.)
OK done
Quoted 67 lines
Quoted 67 lines
drivers/mmc/rockchip_mmc.c new file +66
-0+{ +struct udevice *dev = host->priv; +struct rockchip_mmc_priv *priv =dev_get_priv (dev); +int ret; + + ret =clk_set_periph_rate (priv->clk,PERIPH_ID_SDMMC0 + host->dev_index, + freq); +if (ret <0 ) { +debug ("%s: err=%d\n" , __func__, ret); +return ret; + } + +return freq; +} + +static int rockchip_mmc_ofdata_to_platdata (struct udevice *dev) +{ +struct rockchip_mmc_priv *priv =dev_get_priv (dev); +struct dwmci_host *host = &priv->host; + + host->name = dev->name; + host->ioaddr = (void *)dev_get_addr (dev); + host->buswidth =fdtdec_get_int (gd->fdt_blob, dev->of_offset, +"bus-width" ,4 ); + host->get_mmc_clk = rockchip_mmc_get_mmc_clk; + host->priv = dev; + +/* TODO(sjg at chromium.org): Remove the need for this hack */ + host->dev_index = (ulong )host->ioaddr ==0xff0f0000 ?0 :1 ; + +return 0 ; +} + +int rockchip_mmc_probe (struct udevice *dev) +{ +struct mmc_uclass_priv *upriv =dev_get_uclass_priv (dev); +struct rockchip_mmc_priv *priv =dev_get_priv (dev); +struct dwmci_host *host = &priv->host; +u32 minmax[2 ]; +int ret; + + priv->grf =syscon_get_first_range (ROCKCHIP_SYSCON_GRF ); +if (IS_ERR (priv->grf)) +return PTR_ERR (priv->grf); + ret =uclass_get_device (UCLASS_CLK ,CLK_GENERAL , &priv->clk); +if (ret) +return ret; + + ret =fdtdec_get_int_array (gd->fdt_blob, dev->of_offset, +"clock-freq-min-max" , minmax,2 ); +if (!ret) + ret =add_dwmci (host, minmax[1 ], minmax[0 ]); +if (ret) +return ret; + + upriv->mmc = host->mmc; + +return 0 ; +} + +static const struct udevice_id rockchip_mmc_ids[] = { + { .compatible ="rockchip,rk3288-dw-mshc" }, + { } +}; + +U_BOOT_DRIVER (rockchip_mmc_drv) = {
Quoted 9 lines
drivers/mmc/rockchip_mmc.c line 98
Quoted 8 lines
drivers/mmc/rockchip_mmc.c new file +7
-0+ .name = "rockchip_mmc", + .id = UCLASS_MMC, + .of_match = rockchip_mmc_ids, + .ofdata_to_platdata = rockchip_mmc_ofdata_to_platdata, + .probe = rockchip_mmc_probe, + .priv_auto_alloc_size = sizeof(struct dwmci_host), +};
Regards,
Simon
PATCH v4 27/33 rockchip: Add an MMC driver
In reply to Simon GlassHi Simon,
Quoted 141 lines · Simon Glass
Add an MMC driver which supports RK3288, but may also support other SoCs. It uses the Designware MMC device.
Signed-off-by Simon Glass <[email protected]>---
Changes in v4: None
Changes in v3: None
Changes in v2: Nonedrivers/mmc/Kconfig | 9 +++++ drivers/mmc/Makefile | 1 + drivers/mmc/rockchip_mmc.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 108 insertions(+) create mode 100644 drivers/mmc/rockchip_mmc.cdrivers/mmc/Kconfig +9
-0@@ -10,6 +10,15 @@ config DM_MMC appear as block devices in U-Boot and can support filesystems such as EXT4 and FAT. +config ROCKCHIP_MMC + bool "Rockchip SD/MMC controller support" + depends on DM && OF_CONTROL + help + This enables support for the Rockchip SD/MMM controller, which is + based on Designware IP. The device is compatible with SD 3.0, + SDIO 3.0 and MMC 4.5 and supports common eMMC chips as well as + removeable SD and micro-SD cards. + config SH_SDHI bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support" depends on RMOBILEdrivers/mmc/Makefile +1
-0@@ -29,6 +29,7 @@ obj-$(CONFIG_MXS_MMC) += mxsmmc.o obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o obj-$(CONFIG_X86) += pci_mmc.o obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o +obj-$(CONFIG_ROCKCHIP_MMC) += rockchip_mmc.o obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o obj-$(CONFIG_S3C_SDI) += s3c_sdi.o obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.odrivers/mmc/rockchip_mmc.c new file +87
-0@@ -0,0 +1,98 @@ +/* +* Copyright (c) 2013 Google, Inc +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dwmmc.h> +#include <errno.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/periph.h> +#include <linux/err.h> + +DECLARE_GLOBAL_DATA_PTR ; + +struct rockchip_mmc_priv { +struct udevice *clk; +struct rk3288_grf *grf; +struct dwmci_host host; +}; + +static uint rockchip_mmc_get_mmc_clk (struct dwmci_host *host,uint freq) +{ +struct udevice *dev = host->priv; +struct rockchip_mmc_priv *priv =dev_get_priv (dev); +int ret; + + ret =clk_set_periph_rate (priv->clk,PERIPH_ID_SDMMC0 + host->dev_index, + freq); +if (ret <0 ) { +debug ("%s: err=%d\n" , __func__, ret); +return ret; + } + +return freq; +} + +static int rockchip_mmc_ofdata_to_platdata (struct udevice *dev) +{ +struct rockchip_mmc_priv *priv =dev_get_priv (dev); +struct dwmci_host *host = &priv->host; + + host->name = dev->name; + host->ioaddr = (void *)dev_get_addr (dev); + host->buswidth =fdtdec_get_int (gd->fdt_blob, dev->of_offset, +"bus-width" ,4 ); + host->get_mmc_clk = rockchip_mmc_get_mmc_clk; + host->priv = dev; + +/* TODO(sjg at chromium.org): Remove the need for this hack */ + host->dev_index = (ulong )host->ioaddr ==0xff0f0000 ?0 :1 ; + +return 0 ; +} + +int rockchip_mmc_probe (struct udevice *dev) +{ +struct mmc_uclass_priv *upriv =dev_get_uclass_priv (dev); +struct rockchip_mmc_priv *priv =dev_get_priv (dev); +struct dwmci_host *host = &priv->host; +u32 minmax[2 ]; +int ret; + + priv->grf =syscon_get_first_range (ROCKCHIP_SYSCON_GRF ); +if (IS_ERR (priv->grf)) +return PTR_ERR (priv->grf); + ret =uclass_get_device (UCLASS_CLK ,CLK_GENERAL , &priv->clk); +if (ret) +return ret; + + ret =fdtdec_get_int_array (gd->fdt_blob, dev->of_offset, +"clock-freq-min-max" , minmax,2 ); +if (!ret) + ret =add_dwmci (host, minmax[1 ], minmax[0 ]); +if (ret) +return ret; + + upriv->mmc = host->mmc; + +return 0 ; +} + +static const struct udevice_id rockchip_mmc_ids[] = { + { .compatible ="rockchip,rk3288-dw-mshc" },
drivers/mmc/rockchip_mmc.c line 97
Quoted 10 lines
drivers/mmc/rockchip_mmc.c new file +10
-0+ { } +}; + +U_BOOT_DRIVER (rockchip_mmc_drv) = { + .name ="rockchip_mmc" , + .id =UCLASS_MMC , + .of_match = rockchip_mmc_ids, + .ofdata_to_platdata = rockchip_mmc_ofdata_to_platdata, + .probe = rockchip_mmc_probe, + .priv_auto_alloc_size =sizeof (struct dwmci_host ),
Shouldn't that be "sizeof(struct rockchip_mmc_priv)" here instead? (I mentioned that already before, just not sure whether that mail got lost or I was just talking nonsense back then).
Cheers,
Andre.
PATCH v4 27/33 rockchip: Add an MMC driver
Hi Andre,
Quoted 18 lines · Andre Przywara
Hi Simon,
Quoted 15 lines · Simon Glass
Add an MMC driver which supports RK3288, but may also support other SoCs. It uses the Designware MMC device.
Signed-off-by Simon Glass <[email protected]>---
Changes in v4: None
Changes in v3: None
Changes in v2: Nonedrivers/mmc/Kconfig | 9 +++++ drivers/mmc/Makefile | 1 + drivers/mmc/rockchip_mmc.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 108 insertions(+) create mode 100644 drivers/mmc/rockchip_mmc.c
[snip]
Quoted 11 lines
drivers/mmc/rockchip_mmc.c line 97
Quoted 7 lines
drivers/mmc/rockchip_mmc.c new file +7
-0+U_BOOT_DRIVER (rockchip_mmc_drv) = { + .name ="rockchip_mmc" , + .id =UCLASS_MMC , + .of_match = rockchip_mmc_ids, + .ofdata_to_platdata = rockchip_mmc_ofdata_to_platdata, + .probe = rockchip_mmc_probe, + .priv_auto_alloc_size =sizeof (struct dwmci_host ),Shouldn't that be "
sizeof(struct rockchip_mmc_priv)" here instead? (I mentioned that already before, just not sure whether that mail got lost or I was just talking nonsense back then).
Yes it should, thank you for catching that!
Regards,
Simon
PATCH v4 28/33 rockchip: Add core SoC start-up code
In reply to Simon GlassAdd code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code.
---
Changes in v4:
- Rename pinctrl.h to dm/pinctrl.h
- Use CONFIG_SPL_LED instead of CONFIG_SPL_LED_SUPPORT
Changes in v3: None
Changes in v2: None
arch/arm/Kconfig | 10 ++ arch/arm/Makefile | 1 + arch/arm/mach-rockchip/Kconfig | 41 +++++ arch/arm/mach-rockchip/Makefile | 13 ++ arch/arm/mach-rockchip/board-spl.c | 290 ++++++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/board.c | 46 ++++++ arch/arm/mach-rockchip/common.c | 28 ++++ arch/arm/mach-rockchip/rk3288/Kconfig | 6 + 8 files changed, 435 insertions(+) create mode 100644 arch/arm/mach-rockchip/Kconfig create mode 100644 arch/arm/mach-rockchip/Makefile create mode 100644 arch/arm/mach-rockchip/board-spl.c create mode 100644 arch/arm/mach-rockchip/board.c create mode 100644 arch/arm/mach-rockchip/common.c create mode 100644 arch/arm/mach-rockchip/rk3288/Kconfig
arch/arm/Kconfig +10 -0
@@ -827,6 +827,14 @@ config TARGET_STM32F429_DISCOVERY bool "Support STM32F429 Discovery" select CPU_V7M +config ARCH_ROCKCHIP + bool "Support Rockchip SoCs" + select SUPPORT_SPL + select SPL + select OF_CONTROL + select CPU_V7 + select DM + endchoice source "arch/arm/mach-at91/Kconfig"
@@ -861,6 +869,8 @@ source "arch/arm/mach-orion5x/Kconfig" source "arch/arm/cpu/armv7/rmobile/Kconfig" +source "arch/arm/mach-rockchip/Kconfig" + source "arch/arm/cpu/armv7/s5pc1xx/Kconfig" source "arch/arm/mach-socfpga/Kconfig"
arch/arm/Makefile +1 -0
@@ -55,6 +55,7 @@ machine-$(CONFIG_ARCH_NOMADIK) += nomadik # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X machine-$(CONFIG_ORION5X) += orion5x machine-$(CONFIG_ARCH_SOCFPGA) += socfpga +machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_TEGRA) += tegra machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_VERSATILE) += versatile
arch/arm/mach-rockchip/Kconfig new file +41 -0
41 lines not on this page · raw message
arch/arm/mach-rockchip/Makefile new file +13 -0
@@ -0,0 +1,13 @@ +# +# Copyright (c) 2014 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += board-spl.o +else +obj-y += board.o +endif +obj-y += common.o +obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
arch/arm/mach-rockchip/board-spl.c new file +290 -0
290 lines not on this page · raw message
arch/arm/mach-rockchip/board.c new file +46 -0
46 lines not on this page · raw message
arch/arm/mach-rockchip/common.c new file +28 -0
@@ -0,0 +1,28 @@ +/* +* (C) Copyright 2015 Google, Inc +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <linux/err.h> + +void *rockchip_get_cru (void ) +{ +struct udevice *dev; +fdt_addr_t addr; +int ret; + + ret =uclass_get_device (UCLASS_CLK ,0 , &dev); +if (ret) +return ERR_PTR (ret); + + addr =dev_get_addr (dev); +if (addr ==FDT_ADDR_T_NONE ) +return ERR_PTR (-EINVAL ); + +return (void *)addr; +}
arch/arm/mach-rockchip/rk3288/Kconfig new file +6 -0
@@ -0,0 +1,6 @@ +if ROCKCHIP_RK3288 + +config SYS_SOC + default "rockchip" + +endif
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 29/33 rockchip: Add I2C driver
In reply to Simon GlassAdd an I2C driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also.
---
Changes in v4:
- Rename pinctrl.h to dm/pinctrl.h
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/i2c.h | 70 ++++++ drivers/i2c/Kconfig | 9 + drivers/i2c/Makefile | 1 + drivers/i2c/rk_i2c.c | 391 +++++++++++++++++++++++++++++++ 4 files changed, 471 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/i2c.h create mode 100644 drivers/i2c/rk_i2c.c
arch/arm/include/asm/arch-rockchip/i2c.h new file +70 -0
@@ -0,0 +1,70 @@ +/* +* (C) Copyright 2012 SAMSUNG Electronics +* Jaehoon Chung <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __ASM_ARCH_I2C_H +#define __ASM_ARCH_I2C_H + +struct i2c_regs { +u32 con; +u32 clkdiv; +u32 mrxaddr; +u32 mrxraddr; +u32 mtxcnt; +u32 mrxcnt; +u32 ien; +u32 ipd; +u32 fcnt; +u32 reserved0[0x37 ]; +u32 txdata[8 ]; +u32 reserved1[0x38 ]; +u32 rxdata[8 ]; +}; + +/* Control register */ +#define I2C_CON_EN (1 << 0) +#define I2C_CON_MOD (mod) ((mod) << 1) +#define I2C_MODE_TX 0x00 +#define I2C_MODE_TRX 0x01 +#define I2C_MODE_RX 0x02 +#define I2C_MODE_RRX 0x03 +#define I2C_CON_MASK (3 << 1) + +#define I2C_CON_START (1 << 3) +#define I2C_CON_STOP (1 << 4) +#define I2C_CON_LASTACK (1 << 5) +#define I2C_CON_ACTACK (1 << 6) + +/* Clock dividor register */ +#define I2C_CLKDIV_VAL (divl, divh) \ + (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000)) + +/* the slave address accessed for master rx mode */ +#define I2C_MRXADDR_SET (vld, addr) (((vld) << 24) | (addr)) + +/* the slave register address accessed for master rx mode */ +#define I2C_MRXRADDR_SET (vld, raddr) (((vld) << 24) | (raddr)) + +/* interrupt enable register */ +#define I2C_BTFIEN (1 << 0) +#define I2C_BRFIEN (1 << 1) +#define I2C_MBTFIEN (1 << 2) +#define I2C_MBRFIEN (1 << 3) +#define I2C_STARTIEN (1 << 4) +#define I2C_STOPIEN (1 << 5) +#define I2C_NAKRCVIEN (1 << 6) + +/* interrupt pending register */ +#define I2C_BTFIPD (1 << 0) +#define I2C_BRFIPD (1 << 1) +#define I2C_MBTFIPD (1 << 2) +#define I2C_MBRFIPD (1 << 3) +#define I2C_STARTIPD (1 << 4) +#define I2C_STOPIPD (1 << 5) +#define I2C_NAKRCVIPD (1 << 6) +#define I2C_IPD_ALL_CLEAN 0x7f + +#endif
drivers/i2c/Kconfig +9 -0
@@ -58,6 +58,15 @@ config DM_I2C_GPIO bindings are supported. Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt +config SYS_I2C_ROCKCHIP + bool "Rockchip I2C driver" + depends on DM_I2C + help + Add support for the Rockchip I2C driver. This is used with various + Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips + have several I2C ports and all are provided, controled by the + device tree. + config SYS_I2C_SANDBOX bool "Sandbox I2C driver" depends on SANDBOX && DM_I2C
drivers/i2c/Makefile +1 -0
@@ -31,6 +31,7 @@ obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o +obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
drivers/i2c/rk_i2c.c new file +391 -0
391 lines not on this page · raw message
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 30/33 rockchip: Add SPI driver
In reply to Simon GlassAdd a SPI driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also.
---
Changes in v4:
- Rename pinctrl.h to dm/pinctrl.h
Changes in v3: None
Changes in v2: None
drivers/spi/Kconfig | 9 ++ drivers/spi/Makefile | 1 + drivers/spi/rk_spi.c | 375 +++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/spi/rk_spi.h | 121 +++++++++++++++++ 4 files changed, 506 insertions(+) create mode 100644 drivers/spi/rk_spi.c create mode 100644 drivers/spi/rk_spi.h
drivers/spi/Kconfig +9 -0
@@ -58,6 +58,15 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config ROCKCHIP_SPI + bool "Rockchip SPI driver" + depends on DM_SPI + help + Enable the Rockchip SPI driver, used to access SPI NOR flash and + other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs. + This uses driver model and requires a device tree binding to + operate. + config SANDBOX_SPI bool "Sandbox SPI driver" depends on SANDBOX && DM
drivers/spi/Makefile +1 -0
@@ -39,6 +39,7 @@ obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o +obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o obj-$(CONFIG_SH_SPI) += sh_spi.o obj-$(CONFIG_SH_QSPI) += sh_qspi.o
drivers/spi/rk_spi.c new file +375 -0
375 lines not on this page · raw message
drivers/spi/rk_spi.h new file +121 -0
121 lines not on this page · raw message
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 30/33 rockchip: Add SPI driver
Hi Simon,
Quoted 25 lines · Simon Glass
Add a SPI driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also.
Signed-off-by Simon Glass <[email protected]>---
Changes in v4:
- Renamepinctrl.htodm/pinctrl.hChanges in v3: None
Changes in v2: Nonedrivers/spi/Kconfig | 9 ++ drivers/spi/Makefile | 1 + drivers/spi/rk_spi.c | 375 +++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/spi/rk_spi.h | 121 +++++++++++++++++ 4 files changed, 506 insertions(+) create mode 100644 drivers/spi/rk_spi.c create mode 100644 drivers/spi/rk_spi.hdrivers/spi/Kconfig +0
-0
drivers/spi/Kconfig config ICH_SPI · line 63
Quoted 6 lines
drivers/spi/Kconfig +3
-0@@ -58,6 +58,15 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config ROCKCHIP_SPI + bool "Rockchip SPI driver" + depends on DM_SPI
It's already in DM_SPI if this is not required, please check.
Quoted 118 lines
drivers/spi/Kconfig +6
-0+ help + Enable the Rockchip SPI driver, used to access SPI NOR flash and + other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs. + This uses driver model and requires a device tree binding to + operate. + config SANDBOX_SPI bool "Sandbox SPI driver" depends on SANDBOX && DMdrivers/spi/Makefile +1
-0@@ -39,6 +39,7 @@ obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o +obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o obj-$(CONFIG_SH_SPI) += sh_spi.o obj-$(CONFIG_SH_QSPI) += sh_qspi.odrivers/spi/rk_spi.c new file +91
-0@@ -0,0 +1,375 @@ +/* +* spi driver for rockchip +* +* (C) Copyright 2015 Google, Inc +* +* (C) Copyright 2008-2013 Rockchip Electronics +* Peter, Software Engineering, <[email protected]>. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <errno.h> +#include <spi.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/periph.h> +#include <dm/pinctrl.h> +#include "rk_spi.h" + +DECLARE_GLOBAL_DATA_PTR ; + +struct rockchip_spi_platdata { +enum periph_id periph_id; +struct udevice *pinctrl; +s32 frequency;/* Default clock frequency, -1 for none */ +fdt_addr_t base; +uint deactivate_delay_us;/* Delay to wait after deactivate */ +}; + +struct rockchip_spi_priv { +struct rockchip_spi *regs; +struct udevice *clk_gpll; +unsigned int max_freq; +unsigned int mode; +enum periph_id periph_id;/* Peripheral ID for this device */ +ulong last_transaction_us;/* Time of last transaction end */ +u8 bits_per_word;/* max 16 bits per word */ +u8 n_bytes; +unsigned int speed_hz; +unsigned int tmode; +uint input_rate; +}; + +#define SPI_FIFO_DEPTH 32 + +static void rkspi_dump_regs (struct rockchip_spi *regs) +{ +debug ("RK SPI registers:\n" ); +debug ("=================================\n" ); +debug ("ctrl0: \t\t0x%08x\n" ,readl (®s->ctrlr0)); +debug ("ctrl1: \t\t0x%08x\n" ,readl (®s->ctrlr1)); +debug ("ssienr: \t\t0x%08x\n" ,readl (®s->enr)); +debug ("ser: \t\t0x%08x\n" ,readl (®s->ser)); +debug ("baudr: \t\t0x%08x\n" ,readl (®s->baudr)); +debug ("txftlr: \t\t0x%08x\n" ,readl (®s->txftlr)); +debug ("rxftlr: \t\t0x%08x\n" ,readl (®s->rxftlr)); +debug ("txflr: \t\t0x%08x\n" ,readl (®s->txflr)); +debug ("rxflr: \t\t0x%08x\n" ,readl (®s->rxflr)); +debug ("sr: \t\t0x%08x\n" ,readl (®s->sr)); +debug ("imr: \t\t0x%08x\n" ,readl (®s->imr)); +debug ("isr: \t\t0x%08x\n" ,readl (®s->isr)); +debug ("dmacr: \t\t0x%08x\n" ,readl (®s->dmacr)); +debug ("dmatdlr: \t0x%08x\n" ,readl (®s->dmatdlr)); +debug ("dmardlr: \t0x%08x\n" ,readl (®s->dmardlr)); +debug ("=================================\n" ); +} + +static void rkspi_enable_chip (struct rockchip_spi *regs,bool enable) +{ +writel (enable ?1 :0 , ®s->enr); +} + +static void rkspi_set_clk (struct rockchip_spi_priv *priv,uint speed) +{ +uint clk_div; + + clk_div = priv->input_rate / speed; + clk_div = (clk_div +1 ) &0xfffe ; +debug ("spi speed %u, div %u\n" , speed, clk_div); + +writel (clk_div, &priv->regs->baudr); +} + +static int rkspi_wait_till_not_busy (struct rockchip_spi *regs) +{ +unsigned int delay =1000 ; +
drivers/spi/rk_spi.c line 101
Quoted 10 lines
drivers/spi/rk_spi.c new file +10
-0+while (delay--) { +if (!(readl (®s->sr) &SR_BUSY )) +return 0 ; + +udelay (1 ); + } +debug ("RK SPI: Status keeps busy for 1000us after a read/write!\n" ); + +return -ETIMEDOUT ; +}
I just made some comments about, this busy loop and debug prints, pleas look at [1] it once if you missed.
Quoted 402 lines
drivers/spi/rk_spi.c new file +274
-0+ +static void spi_cs_activate (struct rockchip_spi *regs,uint cs) +{ +debug ("activate cs%u\n" , cs); +writel (1 << cs, ®s->ser); +} + +static void spi_cs_deactivate (struct rockchip_spi *regs,uint cs) +{ +debug ("deactivate cs%u\n" , cs); +writel (0 , ®s->ser); +} + +static int rockchip_spi_ofdata_to_platdata (struct udevice *bus) +{ +struct rockchip_spi_platdata *plat = bus->platdata; +const void *blob = gd->fdt_blob; +int node = bus->of_offset; +int ret; + + plat->base =dev_get_addr (bus); + ret =uclass_get_device (UCLASS_PINCTRL ,0 , &plat->pinctrl); +if (ret) +return ret; + ret =pinctrl_get_periph_id (plat->pinctrl, bus); + +if (ret <0 ) { +debug ("%s: Could not get peripheral ID for %s: %d\n" , __func__, + bus->name, ret); +return -FDT_ERR_NOTFOUND ; + } + plat->periph_id = ret; + + plat->frequency =fdtdec_get_int (blob, node,"spi-max-frequency" , +50000000 ); + plat->deactivate_delay_us =fdtdec_get_int (blob, node, +"spi-deactivate-delay" ,0 ); +debug ("%s: base=%x, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n" , + __func__, plat->base, plat->periph_id, plat->frequency, + plat->deactivate_delay_us); + +return 0 ; +} + +static int rockchip_spi_probe (struct udevice *bus) +{ +struct rockchip_spi_platdata *plat =dev_get_platdata (bus); +struct rockchip_spi_priv *priv =dev_get_priv (bus); +int ret; + +debug ("%s: probe\n" , __func__); + priv->regs = (struct rockchip_spi *)plat->base; + + priv->last_transaction_us =timer_get_us (); + priv->max_freq = plat->frequency; + priv->periph_id = plat->periph_id; + ret =uclass_get_device (UCLASS_CLK ,CLK_GENERAL , &priv->clk_gpll); +if (ret) { +debug ("%s: Failed to find CLK_GENERAL: %d\n" , __func__, ret); +return ret; + } + +/* +* Use 99 MHz as our clock since it divides nicely into 594 MHz which +* is the assumed speed for CLK_GENERAL. +*/ + ret =clk_set_periph_rate (priv->clk_gpll, plat->periph_id,99000000 ); +if (ret <0 ) { +debug ("%s: Failed to set clock: %d\n" , __func__, ret); +return ret; + } + priv->input_rate = ret; +debug ("%s: rate = %u\n" , __func__, priv->input_rate); + priv->bits_per_word =8 ; + priv->tmode =TMOD_TR ;/* Tx & Rx */ + +return 0 ; +} + +static int rockchip_spi_claim_bus (struct udevice *dev) +{ +struct udevice *bus = dev->parent; +struct rockchip_spi_platdata *plat =dev_get_platdata (bus); +struct rockchip_spi_priv *priv =dev_get_priv (bus); +struct rockchip_spi *regs = priv->regs; +struct dm_spi_slave_platdata *slave_plat =dev_get_parent_platdata (dev); +u8 spi_dfs, spi_tf; +uint ctrlr0; +int ret; + +/* Disable the SPI hardware */ +rkspi_enable_chip (regs,0 ); + +switch (priv->bits_per_word) { +case 8 : + priv->n_bytes =1 ; + spi_dfs =DFS_8BIT ; + spi_tf =HALF_WORD_OFF ; +break ; +case 16 : + priv->n_bytes =2 ; + spi_dfs =DFS_16BIT ; + spi_tf =HALF_WORD_ON ; +break ; +default : +debug ("%s: unsupported bits: %dbits\n" , __func__, + priv->bits_per_word); +return -EPROTONOSUPPORT ; + } + +rkspi_set_clk (priv, priv->speed_hz); + +/* Operation Mode */ + ctrlr0 =OMOD_MASTER <<OMOD_SHIFT ; + +/* Data Frame Size */ + ctrlr0 |= spi_dfs &DFS_MASK <<DFS_SHIFT ; + +/* set SPI mode 0..3 */ +if (priv->mode &SPI_CPOL ) + ctrlr0 |=SCOL_HIGH <<SCOL_SHIFT ; +if (priv->mode &SPI_CPHA ) + ctrlr0 |=SCPH_TOGSTA <<SCPH_SHIFT ; + +/* Chip Select Mode */ + ctrlr0 |=CSM_KEEP <<CSM_SHIFT ; + +/* SSN to Sclk_out delay */ + ctrlr0 |=SSN_DELAY_ONE <<SSN_DELAY_SHIFT ; + +/* Serial Endian Mode */ + ctrlr0 |=SEM_LITTLE <<SEM_SHIFT ; + +/* First Bit Mode */ + ctrlr0 |=FBM_MSB <<FBM_SHIFT ; + +/* Byte and Halfword Transform */ + ctrlr0 |= (spi_tf &HALF_WORD_MASK ) <<HALF_WORD_TX_SHIFT ; + +/* Rxd Sample Delay */ + ctrlr0 |=0 <<RXDSD_SHIFT ; + +/* Frame Format */ + ctrlr0 |=FRF_SPI <<FRF_SHIFT ; + +/* Tx and Rx mode */ + ctrlr0 |= (priv->tmode &TMOD_MASK ) <<TMOD_SHIFT ; + +writel (ctrlr0, ®s->ctrlr0); + + ret =pinctrl_request (plat->pinctrl, priv->periph_id, slave_plat->cs); +if (ret) { +debug ("%s: Cannot request pinctrl: %d\n" , __func__, ret); +return ret; + } + +return 0 ; +} + +static int rockchip_spi_release_bus (struct udevice *dev) +{ +return 0 ; +} + +static int rockchip_spi_xfer (struct udevice *dev,unsigned int bitlen, +const void *dout,void *din,unsigned long flags) +{ +struct udevice *bus = dev->parent; +struct rockchip_spi_priv *priv =dev_get_priv (bus); +struct rockchip_spi *regs = priv->regs; +struct dm_spi_slave_platdata *slave_plat =dev_get_parent_platdata (dev); +int len = bitlen >>3 ; +const u8 *out = dout; +u8 *in = din; +int toread, towrite; +int ret; + +debug ("%s: dout=%p, din=%p, len=%x, flags=%lx\n" , __func__, dout, din, + len, flags); +if (0 ) +rkspi_dump_regs (regs); + +/* Assert CS before transfer */ +if (flags &SPI_XFER_BEGIN ) +spi_cs_activate (regs, slave_plat->cs); + +while (len >0 ) { +int todo =min (len,0xffff ); + +rkspi_enable_chip (regs, true); +writel (todo -1 , ®s->ctrlr1); +rkspi_enable_chip (regs, true); + + toread = todo; + towrite = todo; +while (toread || towrite) { +u32 status =readl (®s->sr); + +if (towrite && !(status &SR_TF_FULL )) { +writel (out ? *out++ :0 , regs->txdr); + towrite--; + } +if (toread && !(status &SR_RF_EMPT )) { +u32 byte =readl (regs->rxdr); + +if (in) + *in++ = byte; + toread--; + } + } + ret =rkspi_wait_till_not_busy (regs); +if (ret) +break ; + len -= todo; + } + +/* Deassert CS after transfer */ +if (flags &SPI_XFER_END ) +spi_cs_deactivate (regs, slave_plat->cs); + +rkspi_enable_chip (regs, false); + +return ret; +} + +static int rockchip_spi_set_speed (struct udevice *bus,uint speed) +{ +struct rockchip_spi_priv *priv =dev_get_priv (bus); + +if (speed >48000000 ) +return -EINVAL ; +if (speed > priv->max_freq) + speed = priv->max_freq; + priv->speed_hz = speed; + +return 0 ; +} + +static int rockchip_spi_set_mode (struct udevice *bus,uint mode) +{ +struct rockchip_spi_priv *priv =dev_get_priv (bus); + + priv->mode = mode; + +return 0 ; +} + +static const struct dm_spi_ops rockchip_spi_ops = { + .claim_bus = rockchip_spi_claim_bus, + .release_bus = rockchip_spi_release_bus, + .xfer = rockchip_spi_xfer, + .set_speed = rockchip_spi_set_speed, + .set_mode = rockchip_spi_set_mode, +/* +* cs_info is not needed, since we require all chip selects to be +* in the device tree explicitly +*/ +}; + +static const struct udevice_id rockchip_spi_ids[] = { + { .compatible ="rockchip,rk3288-spi" }, + { } +}; + +U_BOOT_DRIVER (rockchip_spi) = { + .name ="rockchip_spi" , + .id =UCLASS_SPI , + .of_match = rockchip_spi_ids, + .ops = &rockchip_spi_ops, + .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata, + .platdata_auto_alloc_size =sizeof (struct rockchip_spi_platdata ), + .priv_auto_alloc_size =sizeof (struct rockchip_spi_priv ), + .probe = rockchip_spi_probe, +};drivers/spi/rk_spi.h new file +121
-1@@ -0,0 +1,121 @@ +/* +* SPI driver for rockchip +* +* (C) Copyright 2015 Google, Inc +* +* (C) Copyright 2008-2013 Rockchip Electronics +* Peter, Software Engineering, <[email protected]>. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __RK_SPI_H +#define __RK_SPI_H + +struct rockchip_spi { +u32 ctrlr0; +u32 ctrlr1; +u32 enr; +u32 ser; +u32 baudr; +u32 txftlr; +u32 rxftlr; +u32 txflr; +u32 rxflr; +u32 sr; +u32 ipr; +u32 imr; +u32 isr; +u32 risr; +u32 icr; +u32 dmacr; +u32 dmatdlr; +u32 dmardlr;/* 0x44 */ +u32 reserved[0xef ]; +u32 txdr[0x100 ];/* 0x400 */ +u32 rxdr[0x100 ];/* 0x800 */ +}; + +/* CTRLR0 */ +enum { +DFS_SHIFT =0 ,/* Data Frame Size */ +DFS_MASK =3 , +DFS_4BIT =0 , +DFS_8BIT , +DFS_16BIT , +DFS_RESV , + +CFS_SHIFT =2 ,/* Control Frame Size */ +CFS_MASK =0xf , + +SCPH_SHIFT =6 ,/* Serial Clock Phase */ +SCPH_MASK =1 , +SCPH_TOGMID =0 ,/* SCLK toggles in middle of first data bit */ +SCPH_TOGSTA ,/* SCLK toggles at start of first data bit */ + +SCOL_SHIFT =7 ,/* Serial Clock Polarity */ +SCOL_MASK =1 , +SCOL_LOW =0 ,/* Inactive state of serial clock is low */ +SCOL_HIGH ,/* Inactive state of serial clock is high */ + +CSM_SHIFT =8 ,/* Chip Select Mode */ +CSM_MASK =0x3 , +CSM_KEEP =0 ,/* ss_n stays low after each frame */ +CSM_HALF ,/* ss_n high for half sclk_out cycles */ +CSM_ONE ,/* ss_n high for one sclk_out cycle */ +CSM_RESV , + +SSN_DELAY_SHIFT =10 ,/* SSN to Sclk_out delay */ +SSN_DELAY_MASK =1 , +SSN_DELAY_HALF =0 ,/* 1/2 sclk_out cycle */ +SSN_DELAY_ONE =1 ,/* 1 sclk_out cycle */ + +SEM_SHIFT =11 ,/* Serial Endian Mode */ +SEM_MASK =1 , +SEM_LITTLE =0 ,/* little endian */ +SEM_BIG ,/* big endian */ + +FBM_SHIFT =12 ,/* First Bit Mode */ +FBM_MASK =1 , +FBM_MSB =0 ,/* first bit is MSB */ +FBM_LSB ,/* first bit in LSB */ + +HALF_WORD_TX_SHIFT =13 ,/* Byte and Halfword Transform */ +HALF_WORD_MASK =1 , +HALF_WORD_ON =0 ,/* apb 16bit write/read, spi 8bit write/read */ +HALF_WORD_OFF ,/* apb 8bit write/read, spi 8bit write/read */ + +RXDSD_SHIFT =14 ,/* Rxd Sample Delay, in cycles */ +RXDSD_MASK =3 , + +FRF_SHIFT =16 ,/* Frame Format */ +FRF_MASK =3 , +FRF_SPI =0 ,/* Motorola SPI */ +FRF_SSP ,/* Texas Instruments SSP*/ +FRF_MICROWIRE ,/* National Semiconductors Microwire */ +FRF_RESV , + +TMOD_SHIFT =18 ,/* Transfer Mode */ +TMOD_MASK =3 , +TMOD_TR =0 ,/* xmit & recv */ +TMOD_TO ,/* xmit only */ +TMOD_RO ,/* recv only */ +TMOD_RESV , + +OMOD_SHIFT =20 ,/* Operation Mode */ +OMOD_MASK =1 , +OMOD_MASTER =0 ,/* Master Mode */ +OMOD_SLAVE ,/* Slave Mode */ +}; + +/* SR */ +enum { +SR_MASK =0x7f , +SR_BUSY =1 <<0 , +SR_TF_FULL =1 <<1 , +SR_TF_EMPT =1 <<2 , +SR_RF_EMPT =1 <<3 , +SR_RF_FULL =1 <<4 , +}; + +#endif /* __RK_SPI_H */ --
Quoted 1 line
2.5.0.457.gab17608
thanks!
Signature · 1 line
Jagan | openedev.
PATCH v4 30/33 rockchip: Add SPI driver
Hi Jagan,
Quoted 31 lines · Jagan Teki
Hi Simon,
Quoted 28 lines · Simon Glass
Add a SPI driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also.
Signed-off-by Simon Glass <[email protected]>---
Changes in v4:
- Renamepinctrl.htodm/pinctrl.hChanges in v3: None
Changes in v2: Nonedrivers/spi/Kconfig | 9 ++ drivers/spi/Makefile | 1 + drivers/spi/rk_spi.c | 375 +++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/spi/rk_spi.h | 121 +++++++++++++++++ 4 files changed, 506 insertions(+) create mode 100644 drivers/spi/rk_spi.c create mode 100644 drivers/spi/rk_spi.hdrivers/spi/Kconfig +0
-0@@ -58,6 +58,15 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core.
Quoted 5 lines
drivers/spi/Kconfig config ICH_SPI · line 63
Quoted 3 lines
drivers/spi/Kconfig +3
-0+config ROCKCHIP_SPI + bool "Rockchip SPI driver" + depends on DM_SPIIt's already in
DM_SPIif this is not required, please check.
Yes this can be dropped.
[snip]
Quoted 19 lines
Quoted 5 lines
drivers/spi/Kconfig +5
-0+ +static int rkspi_wait_till_not_busy(struct rockchip_spi *regs) +{ + unsigned int delay = 1000; +drivers/spi/Kconfig config ICH_SPI
Quoted 10 lines
drivers/spi/Kconfig +10
-0+ while (delay--) { + if (!(readl(®s->sr) & SR_BUSY)) + return 0; + + udelay(1); + } + debug("RK SPI: Status keeps busy for 1000us after a read/write!\n"); + + return -ETIMEDOUT; +}I just made some comments about, this busy loop and debug prints, pleas look at [1] it once if you missed.
Quoted 2 lines
Sorry, yes I left behind quite a few comments. I've gone back and tidied these up.
Regards,
Simon
PATCH v4 31/33 rockchip: Add basic support for firefly-rk3288
In reply to Simon GlassThe Firefly RK3288 is a suitable target board for initial mainline Rockchip support. It includes a good set of peripherals, a recent SoC and it is readily available.
This adds only some basic files required to allow the baord to display a serial message in SPL and hang.
---
Changes in v4:
- Adjust the defconfig file to suit mainline
Changes in v3:
- Make use of additional features since version 2
Changes in v2:
- Drop use of CONFIG_USE_PRIVATE_LIBGCC=y
- Tidy up license headers and remove SPL #ifdefs
arch/arm/dts/Makefile | 2 + arch/arm/dts/rk3288-firefly.dts | 75 +++++ arch/arm/dts/rk3288-firefly.dtsi | 457 ++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 10 + board/firefly/firefly-rk3288/Kconfig | 15 + board/firefly/firefly-rk3288/MAINTAINERS | 6 + board/firefly/firefly-rk3288/Makefile | 7 + board/firefly/firefly-rk3288/firefly-rk3288.c | 7 + configs/firefly-rk3288_defconfig | 43 +++ include/configs/firefly-rk3288.h | 15 + include/configs/rk3288_common.h | 98 ++++++ 11 files changed, 735 insertions(+) create mode 100644 arch/arm/dts/rk3288-firefly.dts create mode 100644 arch/arm/dts/rk3288-firefly.dtsi create mode 100644 board/firefly/firefly-rk3288/Kconfig create mode 100644 board/firefly/firefly-rk3288/MAINTAINERS create mode 100644 board/firefly/firefly-rk3288/Makefile create mode 100644 board/firefly/firefly-rk3288/firefly-rk3288.c create mode 100644 configs/firefly-rk3288_defconfig create mode 100644 include/configs/firefly-rk3288.h create mode 100644 include/configs/rk3288_common.h
arch/arm/dts/Makefile +2 -0
@@ -15,6 +15,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5420-peach-pit.dtb \ exynos5800-peach-pi.dtb \ exynos5422-odroidxu3.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += \ + rk3288-firefly.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \
arch/arm/dts/rk3288-firefly.dts new file +75 -0
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arch/arm/dts/rk3288-firefly.dtsi new file +457 -0
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arch/arm/mach-rockchip/rk3288/Kconfig +10 -0
@@ -1,6 +1,16 @@ if ROCKCHIP_RK3288 +config TARGET_FIREFLY_RK3288 + bool "Firefly-RK3288" + help + Firefly is a RK3288-based development board with 2 USB ports, + HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It + also includes on-board eMMC and 1GB of SDRAM. Expansion connectors + provide access to display pins, I2C, SPI, UART and GPIOs. + config SYS_SOC default "rockchip" +source "board/firefly/firefly-rk3288/Kconfig" + endif
board/firefly/firefly-rk3288/Kconfig new file +15 -0
@@ -0,0 +1,15 @@ +if TARGET_FIREFLY_RK3288 + +config SYS_BOARD + default "firefly-rk3288" + +config SYS_VENDOR + default "firefly" + +config SYS_CONFIG_NAME + default "firefly-rk3288" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif
board/firefly/firefly-rk3288/MAINTAINERS new file +6 -0
@@ -0,0 +1,6 @@ +FIREFLY +M: Simon Glass <[email protected]> +S: Maintained +F: board/firefly/firefly-rk3288 +F: include/configs/firefly-rk3288.h +F: configs/firefly-rk3288_defconfig
board/firefly/firefly-rk3288/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += firefly-rk3288.o
board/firefly/firefly-rk3288/firefly-rk3288.c new file +7 -0
@@ -0,0 +1,7 @@ +/* +* (C) Copyright 2015 Google, Inc +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h>
configs/firefly-rk3288_defconfig new file +43 -0
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include/configs/firefly-rk3288.h new file +15 -0
@@ -0,0 +1,15 @@ +/* +* (C) Copyright 2015 Google, Inc +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/rk3288_common.h> + +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_LED_SUPPORT + +#endif
include/configs/rk3288_common.h new file +98 -0
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Signature · 1 line
2.5.0.457.gab17608
PATCH v4 32/33 rockchip: Add basic support for jerry
In reply to Simon GlassThis builds and displays an SPL message, but does not function beyond that.
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Tidy up license headers and remove SPL #ifdefs
arch/arm/dts/Makefile | 3 +- arch/arm/dts/cros-ec-sbs.dtsi | 16 + arch/arm/dts/rk3288-jerry.dts | 203 +++++++ arch/arm/dts/rk3288-veyron-chromebook.dtsi | 200 +++++++ arch/arm/dts/rk3288-veyron.dtsi | 844 +++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 10 + board/google/chromebook_jerry/Kconfig | 15 + board/google/chromebook_jerry/MAINTAINERS | 6 + board/google/chromebook_jerry/Makefile | 7 + board/google/chromebook_jerry/jerry.c | 7 + board/google/common/Makefile | 2 +- configs/chromebook_jerry_defconfig | 43 ++ include/configs/chromebook_jerry.h | 16 + 13 files changed, 1370 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/cros-ec-sbs.dtsi create mode 100644 arch/arm/dts/rk3288-jerry.dts create mode 100644 arch/arm/dts/rk3288-veyron-chromebook.dtsi create mode 100644 arch/arm/dts/rk3288-veyron.dtsi create mode 100644 board/google/chromebook_jerry/Kconfig create mode 100644 board/google/chromebook_jerry/MAINTAINERS create mode 100644 board/google/chromebook_jerry/Makefile create mode 100644 board/google/chromebook_jerry/jerry.c create mode 100644 configs/chromebook_jerry_defconfig create mode 100644 include/configs/chromebook_jerry.h
arch/arm/dts/Makefile +2 -1
@@ -16,7 +16,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5800-peach-pi.dtb \ exynos5422-odroidxu3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ - rk3288-firefly.dtb + rk3288-firefly.dtb \ + rk3288-jerry.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \
arch/arm/dts/cros-ec-sbs.dtsi new file +16 -0
@@ -0,0 +1,16 @@ +/* + * Smart battery dts fragment for devices that use cros-ec-sbs + * + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 +*/ + +&i2c_tunnel { + battery: sbs-battery at b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <1>; + }; +};
arch/arm/dts/rk3288-jerry.dts new file +203 -0
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arch/arm/dts/rk3288-veyron-chromebook.dtsi new file +200 -0
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arch/arm/dts/rk3288-veyron.dtsi new file +844 -0
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arch/arm/mach-rockchip/rk3288/Kconfig +10 -0
@@ -8,9 +8,19 @@ config TARGET_FIREFLY_RK3288 also includes on-board eMMC and 1GB of SDRAM. Expansion connectors provide access to display pins, I2C, SPI, UART and GPIOs. +config TARGET_CHROMEBOOK_JERRY + bool "Google/Rockchip Veyron-Jerry Chromebook" + help + Jerry is a RK3288-based clamshell device with 2 USB 3.0 ports, + HDMI, an 11.9 inch EDP display, micro-SD card, touchpad and + WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to + the keyboard and battery functions. + config SYS_SOC default "rockchip" +source "board/google/chromebook_jerry/Kconfig" + source "board/firefly/firefly-rk3288/Kconfig" endif
board/google/chromebook_jerry/Kconfig new file +15 -0
@@ -0,0 +1,15 @@ +if TARGET_CHROMEBOOK_JERRY + +config SYS_BOARD + default "chromebook_jerry" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "chromebook_jerry" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif
board/google/chromebook_jerry/MAINTAINERS new file +6 -0
@@ -0,0 +1,6 @@ +CHROMEBOOK JERRY BOARD +M: Simon Glass <[email protected]> +S: Maintained +F: board/google/chromebook_jerry/ +F: include/configs/chromebook_jerry.h +F: configs/chromebook_jerry_defconfig
board/google/chromebook_jerry/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += jerry.o
board/google/chromebook_jerry/jerry.c new file +7 -0
@@ -0,0 +1,7 @@ +/* +* (C) Copyright 2015 Google, Inc +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h>
board/google/common/Makefile +1 -1
@@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += early_init.o +obj-$(CONFIG_X86) += early_init.o
configs/chromebook_jerry_defconfig new file +43 -0
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include/configs/chromebook_jerry.h new file +16 -0
@@ -0,0 +1,16 @@ +/* +* (C) Copyright 2015 Google, Inc +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/rk3288_common.h> + +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD + +#endif
Signature · 1 line
2.5.0.457.gab17608
PATCH v4 33/33 rockchip: Add a simple README
In reply to Simon GlassAdd a few notes on how to try out the Rockchip support so far.
---
Changes in v4:
- Tweak the cover letter a little, drop mention of patches already applied
Changes in v3:
- Add various new patches to get RK3288 booting to a prompt
- Update README to mention available drivers
Changes in v2: None
doc/README.rockchip | 246 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 246 insertions(+) create mode 100644 doc/README.rockchip
doc/README.rockchip new file +246 -0
@@ -0,0 +1,246 @@ +# +# Copyright (C) 2015 Google. Inc +# Written by Simon Glass <[email protected]> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +U-Boot on Rockchip +================== + +There are several repositories available with versions of U-Boot that support +many Rockchip devices [1] [2]. + +The current mainline support is experimental only and is not useful for +anything. It should provide a base on which to build. + +So far only support for the RK3288 is provided. + + +Prerequisites +============= + +You will need: + + - Firefly RK3288 baord + - Power connection to 5V using the supplied micro-USB power cable + - Separate USB serial cable attached to your computer and the Firefly + (connect to the micro-USB connector below the logo) + - rkflashtool [3] + - openssl (sudo apt-get install openssl) + - Serial UART connection [4] + - Suitable ARM cross compiler, e.g.: + sudo apt-get install gcc-4.7-arm-linux-gnueabi + + +Building +======== + +At present three RK3288 boards are supported: + + - Firefly RK3288 - use firefly-rk3288 configuration + - Radxa Rock Pro - also uses firefly-rk3288 configuration + - Haier Chromebook - use chromebook_jerry configuration + +For example: + + CROSS_COMPILE=arm-linux-gnueabi- make O=firefly firefly-rk3288_defconfig all + +(or you can use another cross compiler if you prefer) + +Note that the Radxa Rock Pro uses the Firefly configuration for now as +device tree files are not yet available for the Rock Pro. Clearly the two +have hardware differences, so this approach will break down as more drivers +are added. + + +Writing to the board with USB +============================= + +For USB to work you must get your board into ROM boot mode, either by erasing +your MMC or (perhaps) holding the recovery button when you boot the board. +To erase your MMC, you can boot into Linux and type (as root) + + dd if=/dev/zero of=/dev/mmcblk0 bs=1M + +Connect your board's OTG port to your computer. + +To create a suitable image and write it to the board: + + ./firefly-rk3288/tools/mkimage -T rkimage -d ./firefly-rk3288/spl/u-boot-spl-dtb.bin out + cat out | openssl rc4 -K 7c4e0304550509072d2c7b38170d1711 | rkflashtool l + +If all goes well you should something like: + + U-Boot SPL 2015.07-rc1-00383-ge345740-dirty (Jun 03 2015 - 10:06:49) + Card did not respond to voltage select! + spl: mmc init failed with error: -17 + ### ERROR ### Please RESET the board ### + +You will need to reset the board before each time you try. Yes, that's all +it does so far. If support for the Rockchip USB protocol or DFU were added +in SPL then we could in principle load U-Boot and boot to a prompt from USB +as several other platforms do. However it does not seem to be possible to +use the existing boot ROM code from SPL. + + +Booting from an SD card +======================= + +To write an image that boots from an SD card (assumed to be /dev/sdc): + + ./firefly-rk3288/tools/mkimage -T rksd -d firefly-rk3288/spl/u-boot-spl-dtb.bin out + sudo dd if=out of=/dev/sdc + sudo dd if=firefly-rk3288/u-boot-dtb.img of=/dev/sdc seek=256 + +This puts the Rockchip header and SPL image first and then places the U-Boot +image at block 256 (i.e. 128KB from the start of the SD card). This +corresponds with this setting in U-Boot: + + #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256 + +Put this SD (or micro-SD) card into your board and reset it. You should see +something like: + + U-Boot SPL 2015.07-rc1-00383-ge345740-dirty (Jun 03 2015 - 11:04:40) + + + U-Boot 2015.07-rc1-00383-ge345740-dirty (Jun 03 2015 - 11:04:40) + + DRAM: 2 GiB + MMC: + Using default environment + + In: serial at ff690000 + Out: serial at ff690000 + Err: serial at ff690000 + => + + +Booting from SPI +================ + +To write an image that boots from SPI flash (e.g. for the Haier Chromebook): + + ./chromebook_jerry/tools/mkimage -T rkspi -d chromebook_jerry/spl/u-boot-spl-dtb.bin out + dd if=spl.bin of=out.bin bs=128K conv=sync + cat chromebook_jerry/u-boot-dtb.img out.bin + dd if=out.bin of=out.bin.pad bs=4M conv=sync + +This converts the SPL image to the required SPI format by adding the Rockchip +header and skipping every 2KB block. Then the U-Boot image is written at +offset 128KB and the whole image is padded to 4MB which is the SPI flash size. +The position of U-Boot is controlled with this setting in U-Boot: + + #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) + +If you have a Dediprog em100pro connected then you can write the image with: + + sudo em100 -s -c GD25LQ32 -d out.bin.pad -r + +When booting you should see something like: + + U-Boot SPL 2015.07-rc2-00215-g9a58220-dirty (Jun 23 2015 - 12:11:32) + + + U-Boot 2015.07-rc2-00215-g9a58220-dirty (Jun 23 2015 - 12:11:32 -0600) + + Model: Google Jerry + DRAM: 2 GiB + MMC: + Using default environment + + In: serial at ff690000 + Out: serial at ff690000 + Err: serial@ff690000 + => + + +Future work +=========== + +Immediate priorities are: + +- MMC support (in U-Boot itself) +- GPIO (driver exists but is lightly tested) +- I2C (driver exists but is non-functional) +- USB host +- USB device +- PMIC and regulators (only ACT8846 is supported at present) +- LCD and HDMI +- Run CPU at full speed +- Ethernet +- NAND flash +- Support for other Rockchip parts +- Boot U-Boot proper over USB OTG (at present only SPL works) + + +Development Notes +================= + +There are plenty of patches in the links below to help with this work. + +[1] https://github.com/rkchrome/uboot.git +[2] https://github.com/linux-rockchip/u-boot-rockchip.git branch u-boot-rk3288 +[3] https://github.com/linux-rockchip/rkflashtool.git +[4] http://wiki.t-firefly.com/index.php/Firefly-RK3288/Serial_debug/en + +rkimage +------- + +rkimage.c produces an SPL image suitable for sending directly to the boot ROM +over USB OTG. This is a very simple format - just the string RK32 (as 4 bytes) +followed by u-boot-spl-dtb.bin. + +The boot ROM loads image to 0xff704000 which is in the internal SRAM. The SRAM +starts at 0xff700000 and extends to 0xff718000 where we put the stack. + +rksd +---- + +rksd.c produces an image consisting of 32KB of empty space, a header and +u-boot-spl-dtb.bin. The header is defined by 'struct header0_info' although +most of the fields are unused by U-Boot. We just need to specify the +signature, a flag and the block offset and size of the SPL image. + +The header occupies a single block but we pad it out to 4 blocks. The header +is encoding using RC4 with the key 7c4e0304550509072d2c7b38170d1711. The SPL +image can be encoded too but we don't do that. + +The maximum size of u-boot-spl-dtb.bin which the boot ROM will read is 32KB, +or 0x40 blocks. This is a severe and annoying limitation. There may be a way +around this limitation, since there is plenty of SRAM, but at present the +board refuses to boot if this limit is exceeded. + +The image produced is padded up to a block boundary (512 bytes). It should be +written to the start of an SD card using dd. + +Since this image is set to load U-Boot from the SD card at block offset, +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, dd should be used to write +u-boot-dtb.img to the SD card at that offset. See above for instructions. + +rkspi +----- + +rkspi.c produces an image consisting of a header and u-boot-spl-dtb.bin. The +resulting image is then spread out so that only the first 2KB of each 4KB +sector is used. The header is the same as with rksd and the maximum size is +also 32KB (before spreading). The image should be written to the start of +SPI flash. + +See above for instructions on how to write a SPI image. + + +Device tree and driver model +---------------------------- + +Where possible driver model is used to provide a structure to the +functionality. Device tree is used for configuration. However these have an +overhead and in SPL with a 32KB size limit some shortcuts have been taken. +In general all Rockchip drivers should use these features, with SPL-specific +modifications where required. + + +-- +Simon Glass <[email protected]> +24 June 2015
Signature · 1 line
2.5.0.457.gab17608
v4 cover dm: Introduce Rockchip RK3288 support
In reply to Simon Glass+Masahiro for pnictrl discussion
Quoted 308 lines · Simon Glass
The Rockchip RK3288 is based on a quad-core Cortex-A17 CPU and has a good set of peripherals. Various full-featured U-Boot ports are available and this is an attempt to bring those features into mainline. With this series the Firefly RK3288 can boot to a prompt from an SD card.
Since much of the code is generic, this also supports the Radxa Rock 2. Since there is no device tree available for that yet, it uses the same config and device tree as the Firefly. This works because not all peripherals are supported, so the differences don't matter.
Support for booting from USB OTG is also provided, using the on-chip boot ROM and the rkflashtool utility. This can boot as far as SPL, but there is no support for reading U-Boot proper from USB as yet. This requires implementing a suitable protocol (perhaps DFU or Rockchip's proprietary one) in SPL.
Support is also provided for the Hisense Chromebook, which is based on the same SoC. In this case it boots from SPI rather than an SD card.
This seriea makes use of driver model including a number of recently added uclasses:
- Clocks - setting and getting PLL and peripheral clocks
- Pinctrl - adjusting pin multiplexing settings
- Reset - reseting the board or SoC
- RAM - setting up RAM controllers and detecting the available RAM
- MMC - MMC controllers (using the existing block device framework)
- LEDs - turning LEDs on and off, with only a GPIO driver so farThis series avoids hard-coding RK3288-specific code into the build. There is a
CONFIG_ROCKCHIP_RK3288but it only *adds* support for RK3288. In principle another CONFIG could add support for a different Rockchip SoC with only the device tree selecting which one U-Boot works on.Support is provided in mkimage to build these image types:
- rkimage - suitable for packaging up SPL to be sent to the boot ROM over USB OTG
- rksd - suitable for writing to an SD cardMuch of the source and ideas for this series came from downstream Rockchip U-Boot trees. SDRAM init came from Coreboot. In most cases it has been pretty heavily cleaned up / rewritten to meet U-Boot style and remove hard-coding of things.
Drivers are provided for:
- Clocks
- Pinctrl
- SoC reset
- DDR3 SDRAM
- I2C
- SPI
- GPIOs
- LEDs using GPIOS
- MMC
- Firefly main PMIC (ACT8846) and included regulatorsThese are lightly tested and doubtless some problems exist with some, particularly I2C.
One problem with device tree is that U-Boot has no way of dropping features it does not need or use. For SPL this problem needs to be solved and this series uses a new 'fdtgrep' tool for this. The 45KB Firefly device tree reduces to a 6KB bytes when unused material is removed. SDRAM timings are also in the device tree.
There is a large amount of additional work to bring other Rockchip drivers and features into mainline U-Boot, so this is only a start.
Note: This series sits on top of Masahiro's RFC pinctrl series. I wanted to get a new version out while we wait for this to make it to mainline. You can find this series at u-boot-dm/rockchip-working.
Changes in v4:
- Add aset_state_simple()method
- Adjust the defconfig file to suit mainline
- Renamepinctrl.htodm/pinctrl.h
- Tweak the cover letter a little, drop mention of patches already applied
- UseCONFIG_SPL_LEDinstead ofCONFIG_SPL_LED_SUPPORTChanges in v3:
- Add device tree bindings for CRU and DMC
- Add various new patches to get RK3288 booting to a prompt
- Make use of additional features since version 2
- Update README to mention available drivers
- Update clock rate to always be 24MHzChanges in v2:
- Drop use ofCONFIG_USE_PRIVATE_LIBGCC=y
- Tidy up license headers and remove SPL #ifdefsMasahiro Yamada (1):
dm: do not return pointer if NULL is given to devp ofdevice_bind()Simon Glass (32):
pinctrl: Correct build errors in thepinctrl_simple
pinctrl: Add help text toKconfig
pinctrl: Add the concept of peripheral IDs
mmc: Support bypass mode with theget_mmc_clk()method
dm: Improve handling of a missing uclass
dm: Provide better debugging when a device fails to bind
arm: reset: Avoid a build error when the reset uclass is enabled
rockchip: Add serial support
rockchip: Bring in RK3288 device tree file includes and bindings
rockchip: rk3288: dts: Make core devices available early
mkimage: Allow padding to any length
mkimage: Allow the original file size to be recorded
rockchip: Add the rkimage format to mkimage
rockchip: Add support for the SD image
rockchip: Add support for the SPI image
rockchip: gpio: Add rockchip GPIO driver
rockchip: Add basic peripheral and clock definitions
power: Add support for ACT8846 PMIC
power: regulator: Add a driver for ACT8846 regulators
rockchip: rk3288: Add clock driver
rockchip: rk3288: Add header files for PMU and GRF
rockchip: rk3288: Add SoC reset driver
rockchip: rk3288: Add a simple syscon driver
rockchip: rk3288: Add pinctrl driver
rockchip: rk3288: Add SDRAM init
rockchip: Add an MMC driver
rockchip: Add core SoC start-up code
rockchip: Add I2C driver
rockchip: Add SPI driver
rockchip: Add basic support for firefly-rk3288
rockchip: Add basic support for jerry
rockchip: Add a simple READMEarch/arm/Kconfig | 10 + arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 3 + arch/arm/dts/cros-ec-sbs.dtsi | 16 + arch/arm/dts/rk3288-firefly.dts | 75 + arch/arm/dts/rk3288-firefly.dtsi | 457 ++++++ arch/arm/dts/rk3288-jerry.dts | 203 +++ arch/arm/dts/rk3288-thermal.dtsi | 88 ++ arch/arm/dts/rk3288-veyron-chromebook.dtsi | 200 +++ arch/arm/dts/rk3288-veyron.dtsi | 844 +++++++++++ arch/arm/dts/rk3288.dtsi | 1473 ++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/clock.h | 45 + arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 185 +++ arch/arm/include/asm/arch-rockchip/ddr_rk3288.h | 484 +++++++ arch/arm/include/asm/arch-rockchip/gpio.h | 28 + arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 768 ++++++++++ arch/arm/include/asm/arch-rockchip/hardware.h | 20 + arch/arm/include/asm/arch-rockchip/i2c.h | 70 + arch/arm/include/asm/arch-rockchip/periph.h | 54 + arch/arm/include/asm/arch-rockchip/pmu_rk3288.h | 89 ++ arch/arm/include/asm/arch-rockchip/sdram.h | 92 ++ arch/arm/lib/Makefile | 2 + arch/arm/mach-rockchip/Kconfig | 41 + arch/arm/mach-rockchip/Makefile | 13 + arch/arm/mach-rockchip/board-spl.c | 290 ++++ arch/arm/mach-rockchip/board.c | 46 + arch/arm/mach-rockchip/common.c | 28 + arch/arm/mach-rockchip/rk3288/Kconfig | 26 + arch/arm/mach-rockchip/rk3288/Makefile | 9 + arch/arm/mach-rockchip/rk3288/reset_rk3288.c | 47 + arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 878 ++++++++++++ arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 25 + board/firefly/firefly-rk3288/Kconfig | 15 + board/firefly/firefly-rk3288/MAINTAINERS | 6 + board/firefly/firefly-rk3288/Makefile | 7 + board/firefly/firefly-rk3288/firefly-rk3288.c | 7 + board/google/chromebook_jerry/Kconfig | 15 + board/google/chromebook_jerry/MAINTAINERS | 6 + board/google/chromebook_jerry/Makefile | 7 + board/google/chromebook_jerry/jerry.c | 7 + board/google/common/Makefile | 2 +- common/image.c | 3 + configs/chromebook_jerry_defconfig | 43 + configs/firefly-rk3288_defconfig | 43 + doc/README.rockchip | 246 ++++ .../clock/rockchip,rk3188-cru.txt | 61 + .../clock/rockchip,rk3288-cru.txt | 61 + .../clock/rockchip,rk3288-dmc.txt | 155 ++ doc/device-tree-bindings/clock/rockchip.txt | 77 + .../pinctrl/rockchip,pinctrl.txt | 157 +++ .../thermal/rockchip-thermal.txt | 68 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3288.c | 618 ++++++++ drivers/core/device.c | 10 +- drivers/core/root.c | 5 +- drivers/core/uclass.c | 7 +- drivers/gpio/Kconfig | 9 + drivers/gpio/Makefile | 1 + drivers/gpio/rk_gpio.c | 123 ++ drivers/i2c/Kconfig | 9 + drivers/i2c/Makefile | 1 + drivers/i2c/rk_i2c.c | 391 ++++++ drivers/mmc/Kconfig | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/dw_mmc.c | 2 +- drivers/mmc/exynos_dw_mmc.c | 2 +- drivers/mmc/rockchip_mmc.c | 98 ++ drivers/pinctrl/Kconfig | 22 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-uclass.c | 41 +- drivers/pinctrl/rockchip/Makefile | 8 + drivers/pinctrl/rockchip/pinctrl_rk3288.c | 441 ++++++ drivers/power/pmic/Kconfig | 9 + drivers/power/pmic/Makefile | 1 + drivers/power/pmic/act8846.c | 90 ++ drivers/power/regulator/Kconfig | 9 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/act8846.c | 155 ++ drivers/serial/Kconfig | 9 + drivers/serial/Makefile | 1 + drivers/serial/serial_rockchip.c | 43 + drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/rk_spi.c | 375 +++++ drivers/spi/rk_spi.h | 121 ++ include/configs/chromebook_jerry.h | 16 + include/configs/firefly-rk3288.h | 15 + include/configs/rk3288_common.h | 98 ++ include/dm/pinctrl.h | 61 + include/dt-bindings/clock/rk3288-cru.h | 370 +++++ include/dt-bindings/clock/rockchip,rk808.h | 11 + include/dt-bindings/pinctrl/rockchip.h | 26 + include/dt-bindings/power-domain/rk3288.h | 11 + include/dwmmc.h | 16 +- include/image.h | 5 +- include/power/act8846_pmic.h | 37 + tools/Makefile | 3 + tools/imagetool.h | 1 + tools/mkimage.c | 23 +- tools/rkcommon.c | 72 + tools/rkcommon.h | 28 + tools/rkimage.c | 65 + tools/rksd.c | 102 ++ tools/rkspi.c | 119 ++ 104 files changed, 11274 insertions(+), 25 deletions(-) create mode 100644 arch/arm/dts/cros-ec-sbs.dtsi create mode 100644 arch/arm/dts/rk3288-firefly.dts create mode 100644 arch/arm/dts/rk3288-firefly.dtsi create mode 100644 arch/arm/dts/rk3288-jerry.dts create mode 100644 arch/arm/dts/rk3288-thermal.dtsi create mode 100644 arch/arm/dts/rk3288-veyron-chromebook.dtsi create mode 100644 arch/arm/dts/rk3288-veyron.dtsi create mode 100644 arch/arm/dts/rk3288.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/clock.h create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/gpio.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/hardware.h create mode 100644 arch/arm/include/asm/arch-rockchip/i2c.h create mode 100644 arch/arm/include/asm/arch-rockchip/periph.h create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/sdram.h create mode 100644 arch/arm/mach-rockchip/Kconfig create mode 100644 arch/arm/mach-rockchip/Makefile create mode 100644 arch/arm/mach-rockchip/board-spl.c create mode 100644 arch/arm/mach-rockchip/board.c create mode 100644 arch/arm/mach-rockchip/common.c create mode 100644 arch/arm/mach-rockchip/rk3288/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3288/Makefile create mode 100644 arch/arm/mach-rockchip/rk3288/reset_rk3288.c create mode 100644 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c create mode 100644 arch/arm/mach-rockchip/rk3288/syscon_rk3288.c create mode 100644 board/firefly/firefly-rk3288/Kconfig create mode 100644 board/firefly/firefly-rk3288/MAINTAINERS create mode 100644 board/firefly/firefly-rk3288/Makefile create mode 100644 board/firefly/firefly-rk3288/firefly-rk3288.c create mode 100644 board/google/chromebook_jerry/Kconfig create mode 100644 board/google/chromebook_jerry/MAINTAINERS create mode 100644 board/google/chromebook_jerry/Makefile create mode 100644 board/google/chromebook_jerry/jerry.c create mode 100644 configs/chromebook_jerry_defconfig create mode 100644 configs/firefly-rk3288_defconfig create mode 100644 doc/README.rockchip create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txt create mode 100644 doc/device-tree-bindings/clock/rockchip.txt create mode 100644 doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt create mode 100644 doc/device-tree-bindings/thermal/rockchip-thermal.txt create mode 100644 drivers/clk/clk_rk3288.c create mode 100644 drivers/gpio/rk_gpio.c create mode 100644 drivers/i2c/rk_i2c.c create mode 100644 drivers/mmc/rockchip_mmc.c create mode 100644 drivers/pinctrl/rockchip/Makefile create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3288.c create mode 100644 drivers/power/pmic/act8846.c create mode 100644 drivers/power/regulator/act8846.c create mode 100644 drivers/serial/serial_rockchip.c create mode 100644 drivers/spi/rk_spi.c create mode 100644 drivers/spi/rk_spi.h create mode 100644 include/configs/chromebook_jerry.h create mode 100644 include/configs/firefly-rk3288.h create mode 100644 include/configs/rk3288_common.h create mode 100644 include/dt-bindings/clock/rk3288-cru.h create mode 100644 include/dt-bindings/clock/rockchip,rk808.h create mode 100644 include/dt-bindings/pinctrl/rockchip.h create mode 100644 include/dt-bindings/power-domain/rk3288.h create mode 100644 include/power/act8846_pmic.h create mode 100644 tools/rkcommon.c create mode 100644 tools/rkcommon.h create mode 100644 tools/rkimage.c create mode 100644 tools/rksd.c create mode 100644 tools/rkspi.c--
2.5.0.457.gab17608
v4 cover dm: Introduce Rockchip RK3288 support
In reply to Simon GlassQuoted 10 lines · Simon Glass
The Rockchip RK3288 is based on a quad-core Cortex-A17 CPU and has a good
set of peripherals. Various full-featured U-Boot ports are available and
this is an attempt to bring those features into mainline. With this series
the Firefly RK3288 can boot to a prompt from an SD card.Since much of the code is generic, this also supports the Radxa Rock 2.
Tested this series on a Radxa Rock 2 (square baseboard)
Overal the code looks great to me as well, but i didn't have the time to do an in-depth. Hence not doing an reviewed-by
Thanks for your work!
Signature · 2 lines
Sjoerd Simons Collabora Ltd.
v4 cover dm: Introduce Rockchip RK3288 support
Hi Sjoerd,
Quoted 12 lines · Sjoerd Simons
Quoted 10 lines · Simon Glass
The Rockchip RK3288 is based on a quad-core Cortex-A17 CPU and has a good
set of peripherals. Various full-featured U-Boot ports are available and
this is an attempt to bring those features into mainline. With this series
the Firefly RK3288 can boot to a prompt from an SD card.Since much of the code is generic, this also supports the Radxa Rock 2.
Quoted 8 lines
Tested this series on a Radxa Rock 2 (square baseboard)
Tested-by Sjoerd Simons <[email protected]>Overal the code looks great to me as well, but i didn't have the time to do an in-depth. Hence not doing an reviewed-by
Thanks for your work!
Thanks for your help with this.
Tom requested that I collect all these patches and yours and send them in one series. I'l going to do that soon.
Regards,
Simon
v4 cover dm: Introduce Rockchip RK3288 support
In reply to Simon GlassHi Simon,
Do you have plan to support interrupt controller driver for U-Boot?
On Rockchip SDK uboot?interrupt is enabled, usb driver using interrupt for speed up programing images. U-Boot code has no a good interrupt controller driver platform, especially when u-boot using dtb. So, I haven't a good idea if I want to upstream rockchip interrupt driver, do you have any suggestion?
Regards,
????CWZ?
cwz at rock-chips.com
???+86-0591-83991906?8090
??????????? Fuzhou Rockchip Electronics Co.Ltd
????????????????89????A?21?? (350003)
Addr : No. 21 Building, A District, No.89,software Boulevard Fuzhou,Fujian,PRC
****************************************************************************
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IMPORTANT NOTICE: This email is from Fuzhou Rockchip Electronics Co., Ltd .The contents of this email and any attachments may contain information that is privileged, confidential and/or exempt from disclosure under applicable law and relevant NDA. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information is STRICTLY PROHIBITED. Please immediately contact the sender as soon as possible and destroy the material in its entirety in any format. Thank you.
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From: Simon Glass
Date: 2015-08-24 23:12
To: U-Boot Mailing List
CC: Andre Przywara; FUKAUMI Naoki; huangtao; cwx; Ulrich Prinz; Sjoerd Simons; Simon Glass; Joe Hershberger; Pantelis Antoniou; Marek Vasut; Albert Aribaud; Lukasz Majewski; Pavel Herrmann
Subject: [PATCH v4 00/33] dm: Introduce Rockchip RK3288 support
The Rockchip RK3288 is based on a quad-core Cortex-A17 CPU and has a good set of peripherals. Various full-featured U-Boot ports are available and this is an attempt to bring those features into mainline. With this series the Firefly RK3288 can boot to a prompt from an SD card.
Since much of the code is generic, this also supports the Radxa Rock 2. Since there is no device tree available for that yet, it uses the same config and device tree as the Firefly. This works because not all peripherals are supported, so the differences don't matter.
Support for booting from USB OTG is also provided, using the on-chip boot ROM and the rkflashtool utility. This can boot as far as SPL, but there is no support for reading U-Boot proper from USB as yet. This requires implementing a suitable protocol (perhaps DFU or Rockchip's proprietary one) in SPL.
Support is also provided for the Hisense Chromebook, which is based on the same SoC. In this case it boots from SPI rather than an SD card.
This seriea makes use of driver model including a number of recently added uclasses:
- Clocks - setting and getting PLL and peripheral clocks
- Pinctrl - adjusting pin multiplexing settings
- Reset - reseting the board or SoC
- RAM - setting up RAM controllers and detecting the available RAM
- MMC - MMC controllers (using the existing block device framework)
- LEDs - turning LEDs on and off, with only a GPIO driver so far
This series avoids hard-coding RK3288-specific code into the build. There is a CONFIG_ROCKCHIP_RK3288 but it only *adds* support for RK3288. In principle another CONFIG could add support for a different Rockchip SoC with only the device tree selecting which one U-Boot works on.
Support is provided in mkimage to build these image types:
- rkimage - suitable for packaging up SPL to be sent to the boot ROM over USB OTG
- rksd - suitable for writing to an SD card
Much of the source and ideas for this series came from downstream Rockchip U-Boot trees. SDRAM init came from Coreboot. In most cases it has been pretty heavily cleaned up / rewritten to meet U-Boot style and remove hard-coding of things.
Drivers are provided for:
- Clocks
- Pinctrl
- SoC reset
- DDR3 SDRAM
- I2C
- SPI
- GPIOs
- LEDs using GPIOS
- MMC
- Firefly main PMIC (ACT8846) and included regulators
These are lightly tested and doubtless some problems exist with some, particularly I2C.
One problem with device tree is that U-Boot has no way of dropping features it does not need or use. For SPL this problem needs to be solved and this series uses a new 'fdtgrep' tool for this. The 45KB Firefly device tree reduces to a 6KB bytes when unused material is removed. SDRAM timings are also in the device tree.
There is a large amount of additional work to bring other Rockchip drivers and features into mainline U-Boot, so this is only a start.
Note: This series sits on top of Masahiro's RFC pinctrl series. I wanted to get a new version out while we wait for this to make it to mainline. You can find this series at u-boot-dm/rockchip-working.
Changes in v4:
- Add a set_state_simple() method
- Adjust the defconfig file to suit mainline
- Rename pinctrl.h to dm/pinctrl.h
- Tweak the cover letter a little, drop mention of patches already applied
- Use CONFIG_SPL_LED instead of CONFIG_SPL_LED_SUPPORT
Changes in v3:
- Add device tree bindings for CRU and DMC
- Add various new patches to get RK3288 booting to a prompt
- Make use of additional features since version 2
- Update README to mention available drivers
- Update clock rate to always be 24MHz
Changes in v2:
- Drop use of CONFIG_USE_PRIVATE_LIBGCC=y
- Tidy up license headers and remove SPL #ifdefs
Masahiro Yamada (1):
dm: do not return pointer if NULL is given to devp of device_bind()
Simon Glass (32):
pinctrl: Correct build errors in the pinctrl_simple
pinctrl: Add help text to Kconfig
pinctrl: Add the concept of peripheral IDs
mmc: Support bypass mode with the get_mmc_clk() method
dm: Improve handling of a missing uclass
dm: Provide better debugging when a device fails to bind
arm: reset: Avoid a build error when the reset uclass is enabled
rockchip: Add serial support
rockchip: Bring in RK3288 device tree file includes and bindings
rockchip: rk3288: dts: Make core devices available early
mkimage: Allow padding to any length
mkimage: Allow the original file size to be recorded
rockchip: Add the rkimage format to mkimage
rockchip: Add support for the SD image
rockchip: Add support for the SPI image
rockchip: gpio: Add rockchip GPIO driver
rockchip: Add basic peripheral and clock definitions
power: Add support for ACT8846 PMIC
power: regulator: Add a driver for ACT8846 regulators
rockchip: rk3288: Add clock driver
rockchip: rk3288: Add header files for PMU and GRF
rockchip: rk3288: Add SoC reset driver
rockchip: rk3288: Add a simple syscon driver
rockchip: rk3288: Add pinctrl driver
rockchip: rk3288: Add SDRAM init
rockchip: Add an MMC driver
rockchip: Add core SoC start-up code
rockchip: Add I2C driver
rockchip: Add SPI driver
rockchip: Add basic support for firefly-rk3288
rockchip: Add basic support for jerry
rockchip: Add a simple README
arch/arm/Kconfig | 10 + arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 3 + arch/arm/dts/cros-ec-sbs.dtsi | 16 + arch/arm/dts/rk3288-firefly.dts | 75 + arch/arm/dts/rk3288-firefly.dtsi | 457 ++++++ arch/arm/dts/rk3288-jerry.dts | 203 +++ arch/arm/dts/rk3288-thermal.dtsi | 88 ++ arch/arm/dts/rk3288-veyron-chromebook.dtsi | 200 +++ arch/arm/dts/rk3288-veyron.dtsi | 844 +++++++++++ arch/arm/dts/rk3288.dtsi | 1473 ++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/clock.h | 45 + arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 185 +++ arch/arm/include/asm/arch-rockchip/ddr_rk3288.h | 484 +++++++ arch/arm/include/asm/arch-rockchip/gpio.h | 28 + arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 768 ++++++++++ arch/arm/include/asm/arch-rockchip/hardware.h | 20 + arch/arm/include/asm/arch-rockchip/i2c.h | 70 + arch/arm/include/asm/arch-rockchip/periph.h | 54 + arch/arm/include/asm/arch-rockchip/pmu_rk3288.h | 89 ++ arch/arm/include/asm/arch-rockchip/sdram.h | 92 ++ arch/arm/lib/Makefile | 2 + arch/arm/mach-rockchip/Kconfig | 41 + arch/arm/mach-rockchip/Makefile | 13 + arch/arm/mach-rockchip/board-spl.c | 290 ++++ arch/arm/mach-rockchip/board.c | 46 + arch/arm/mach-rockchip/common.c | 28 + arch/arm/mach-rockchip/rk3288/Kconfig | 26 + arch/arm/mach-rockchip/rk3288/Makefile | 9 + arch/arm/mach-rockchip/rk3288/reset_rk3288.c | 47 + arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 878 ++++++++++++ arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 25 + board/firefly/firefly-rk3288/Kconfig | 15 + board/firefly/firefly-rk3288/MAINTAINERS | 6 + board/firefly/firefly-rk3288/Makefile | 7 + board/firefly/firefly-rk3288/firefly-rk3288.c | 7 + board/google/chromebook_jerry/Kconfig | 15 + board/google/chromebook_jerry/MAINTAINERS | 6 + board/google/chromebook_jerry/Makefile | 7 + board/google/chromebook_jerry/jerry.c | 7 + board/google/common/Makefile | 2 +- common/image.c | 3 + configs/chromebook_jerry_defconfig | 43 + configs/firefly-rk3288_defconfig | 43 + doc/README.rockchip | 246 ++++ .../clock/rockchip,rk3188-cru.txt | 61 + .../clock/rockchip,rk3288-cru.txt | 61 + .../clock/rockchip,rk3288-dmc.txt | 155 ++ doc/device-tree-bindings/clock/rockchip.txt | 77 + .../pinctrl/rockchip,pinctrl.txt | 157 +++ .../thermal/rockchip-thermal.txt | 68 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3288.c | 618 ++++++++ drivers/core/device.c | 10 +- drivers/core/root.c | 5 +- drivers/core/uclass.c | 7 +- drivers/gpio/Kconfig | 9 + drivers/gpio/Makefile | 1 + drivers/gpio/rk_gpio.c | 123 ++ drivers/i2c/Kconfig | 9 + drivers/i2c/Makefile | 1 + drivers/i2c/rk_i2c.c | 391 ++++++ drivers/mmc/Kconfig | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/dw_mmc.c | 2 +- drivers/mmc/exynos_dw_mmc.c | 2 +- drivers/mmc/rockchip_mmc.c | 98 ++ drivers/pinctrl/Kconfig | 22 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-uclass.c | 41 +- drivers/pinctrl/rockchip/Makefile | 8 + drivers/pinctrl/rockchip/pinctrl_rk3288.c | 441 ++++++ drivers/power/pmic/Kconfig | 9 + drivers/power/pmic/Makefile | 1 + drivers/power/pmic/act8846.c | 90 ++ drivers/power/regulator/Kconfig | 9 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/act8846.c | 155 ++ drivers/serial/Kconfig | 9 + drivers/serial/Makefile | 1 + drivers/serial/serial_rockchip.c | 43 + drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/rk_spi.c | 375 +++++ drivers/spi/rk_spi.h | 121 ++ include/configs/chromebook_jerry.h | 16 + include/configs/firefly-rk3288.h | 15 + include/configs/rk3288_common.h | 98 ++ include/dm/pinctrl.h | 61 + include/dt-bindings/clock/rk3288-cru.h | 370 +++++ include/dt-bindings/clock/rockchip,rk808.h | 11 + include/dt-bindings/pinctrl/rockchip.h | 26 + include/dt-bindings/power-domain/rk3288.h | 11 + include/dwmmc.h | 16 +- include/image.h | 5 +- include/power/act8846_pmic.h | 37 + tools/Makefile | 3 + tools/imagetool.h | 1 + tools/mkimage.c | 23 +- tools/rkcommon.c | 72 + tools/rkcommon.h | 28 + tools/rkimage.c | 65 + tools/rksd.c | 102 ++ tools/rkspi.c | 119 ++ 104 files changed, 11274 insertions(+), 25 deletions(-)
create mode 100644 arch/arm/dts/cros-ec-sbs.dtsi
create mode 100644 arch/arm/dts/rk3288-firefly.dts
create mode 100644 arch/arm/dts/rk3288-firefly.dtsi
create mode 100644 arch/arm/dts/rk3288-jerry.dts
create mode 100644 arch/arm/dts/rk3288-thermal.dtsi
create mode 100644 arch/arm/dts/rk3288-veyron-chromebook.dtsi create mode 100644 arch/arm/dts/rk3288-veyron.dtsi
create mode 100644 arch/arm/dts/rk3288.dtsi
create mode 100644 arch/arm/include/asm/arch-rockchip/clock.h create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/gpio.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/hardware.h create mode 100644 arch/arm/include/asm/arch-rockchip/i2c.h create mode 100644 arch/arm/include/asm/arch-rockchip/periph.h create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/sdram.h create mode 100644 arch/arm/mach-rockchip/Kconfig
create mode 100644 arch/arm/mach-rockchip/Makefile
create mode 100644 arch/arm/mach-rockchip/board-spl.c
create mode 100644 arch/arm/mach-rockchip/board.c
create mode 100644 arch/arm/mach-rockchip/common.c
create mode 100644 arch/arm/mach-rockchip/rk3288/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3288/Makefile create mode 100644 arch/arm/mach-rockchip/rk3288/reset_rk3288.c create mode 100644 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c create mode 100644 arch/arm/mach-rockchip/rk3288/syscon_rk3288.c create mode 100644 board/firefly/firefly-rk3288/Kconfig create mode 100644 board/firefly/firefly-rk3288/MAINTAINERS create mode 100644 board/firefly/firefly-rk3288/Makefile create mode 100644 board/firefly/firefly-rk3288/firefly-rk3288.c create mode 100644 board/google/chromebook_jerry/Kconfig create mode 100644 board/google/chromebook_jerry/MAINTAINERS create mode 100644 board/google/chromebook_jerry/Makefile create mode 100644 board/google/chromebook_jerry/jerry.c create mode 100644 configs/chromebook_jerry_defconfig
create mode 100644 configs/firefly-rk3288_defconfig
create mode 100644 doc/README.rockchip
create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txt create mode 100644 doc/device-tree-bindings/clock/rockchip.txt create mode 100644 doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt create mode 100644 doc/device-tree-bindings/thermal/rockchip-thermal.txt create mode 100644 drivers/clk/clk_rk3288.c
create mode 100644 drivers/gpio/rk_gpio.c
create mode 100644 drivers/i2c/rk_i2c.c
create mode 100644 drivers/mmc/rockchip_mmc.c
create mode 100644 drivers/pinctrl/rockchip/Makefile
create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3288.c create mode 100644 drivers/power/pmic/act8846.c
create mode 100644 drivers/power/regulator/act8846.c
create mode 100644 drivers/serial/serial_rockchip.c
create mode 100644 drivers/spi/rk_spi.c
create mode 100644 drivers/spi/rk_spi.h
create mode 100644 include/configs/chromebook_jerry.h
create mode 100644 include/configs/firefly-rk3288.h
create mode 100644 include/configs/rk3288_common.h
create mode 100644 include/dt-bindings/clock/rk3288-cru.h create mode 100644 include/dt-bindings/clock/rockchip,rk808.h create mode 100644 include/dt-bindings/pinctrl/rockchip.h create mode 100644 include/dt-bindings/power-domain/rk3288.h create mode 100644 include/power/act8846_pmic.h
create mode 100644 tools/rkcommon.c
create mode 100644 tools/rkcommon.h
create mode 100644 tools/rkimage.c
create mode 100644 tools/rksd.c
create mode 100644 tools/rkspi.c
Signature · 1 line
2.5.0.457.gab17608
v4 cover dm: Introduce Rockchip RK3288 support
Hi,
Quoted 10 lines · cwz at rock-chips.com
Hi Simon,
Do you have plan to support interrupt controller driver for U-Boot?
On Rockchip SDK uboot?interrupt is enabled, usb driver using interrupt for speed up programing images.
U-Boot code has no a good interrupt controller driver platform, especially when u-boot using dtb.
So, I haven't a good idea if I want to upstream rockchip interrupt driver, do you have any suggestion?
You could try writing a driver and some code to parse the device tree. We could even have a new interrupt uclass if you like.
I do not have a plan myself at present, but I can help (perhaps with tests and sandbox) if you make a start.
Regards,
Simon
Quoted 345 lines
Regards,
________________________________
????CWZ?cwz at rock-chips.com
???+86-0591-83991906?8090
??????????? Fuzhou Rockchip Electronics Co.Ltd ????????????????89????A?21?? (350003)
Addr : No. 21 Building, A District, No.89,software Boulevard Fuzhou,Fujian,PRC****************************************************************************
??????????????????????????????????????????????????? ?????????????????????????????????????????????????????????????????????????????????????????????????? IMPORTANT NOTICE: This email is from Fuzhou Rockchip Electronics Co., Ltd
.The contents of this email and any attachments may contain information that
is privileged, confidential and/or exempt from disclosure under applicable
law and relevant NDA. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the
information is STRICTLY PROHIBITED. Please immediately contact the sender as
soon as possible and destroy the material in its entirety in any format.
Thank you.
****************************************************************************From: Simon Glass
Date: 2015-08-24 23:12
To: U-Boot Mailing List
CC: Andre Przywara; FUKAUMI Naoki; huangtao; cwx; Ulrich Prinz; Sjoerd Simons; Simon Glass; Joe Hershberger; Pantelis Antoniou; Marek Vasut; Albert Aribaud; Lukasz Majewski; Pavel Herrmann
Subject: [PATCH v4 00/33] dm: Introduce Rockchip RK3288 supportThe Rockchip RK3288 is based on a quad-core Cortex-A17 CPU and has a good set of peripherals. Various full-featured U-Boot ports are available and this is an attempt to bring those features into mainline. With this series the Firefly RK3288 can boot to a prompt from an SD card.
Since much of the code is generic, this also supports the Radxa Rock 2. Since there is no device tree available for that yet, it uses the same config and device tree as the Firefly. This works because not all peripherals are supported, so the differences don't matter.
Support for booting from USB OTG is also provided, using the on-chip boot ROM and the rkflashtool utility. This can boot as far as SPL, but there is no support for reading U-Boot proper from USB as yet. This requires implementing a suitable protocol (perhaps DFU or Rockchip's proprietary one) in SPL.
Support is also provided for the Hisense Chromebook, which is based on the same SoC. In this case it boots from SPI rather than an SD card.
This seriea makes use of driver model including a number of recently added uclasses:
- Clocks - setting and getting PLL and peripheral clocks
- Pinctrl - adjusting pin multiplexing settings
- Reset - reseting the board or SoC
- RAM - setting up RAM controllers and detecting the available RAM
- MMC - MMC controllers (using the existing block device framework)
- LEDs - turning LEDs on and off, with only a GPIO driver so farThis series avoids hard-coding RK3288-specific code into the build. There is a
CONFIG_ROCKCHIP_RK3288but it only *adds* support for RK3288. In principle another CONFIG could add support for a different Rockchip SoC with only the device tree selecting which one U-Boot works on.Support is provided in mkimage to build these image types:
- rkimage - suitable for packaging up SPL to be sent to the boot ROM over USB OTG
- rksd - suitable for writing to an SD cardMuch of the source and ideas for this series came from downstream Rockchip U-Boot trees. SDRAM init came from Coreboot. In most cases it has been pretty heavily cleaned up / rewritten to meet U-Boot style and remove hard-coding of things.
Drivers are provided for:
- Clocks
- Pinctrl
- SoC reset
- DDR3 SDRAM
- I2C
- SPI
- GPIOs
- LEDs using GPIOS
- MMC
- Firefly main PMIC (ACT8846) and included regulatorsThese are lightly tested and doubtless some problems exist with some, particularly I2C.
One problem with device tree is that U-Boot has no way of dropping features it does not need or use. For SPL this problem needs to be solved and this series uses a new 'fdtgrep' tool for this. The 45KB Firefly device tree reduces to a 6KB bytes when unused material is removed. SDRAM timings are also in the device tree.
There is a large amount of additional work to bring other Rockchip drivers and features into mainline U-Boot, so this is only a start.
Note: This series sits on top of Masahiro's RFC pinctrl series. I wanted to get a new version out while we wait for this to make it to mainline. You can find this series at u-boot-dm/rockchip-working.
Changes in v4:
- Add aset_state_simple()method
- Adjust the defconfig file to suit mainline
- Renamepinctrl.htodm/pinctrl.h
- Tweak the cover letter a little, drop mention of patches already applied
- UseCONFIG_SPL_LEDinstead ofCONFIG_SPL_LED_SUPPORTChanges in v3:
- Add device tree bindings for CRU and DMC
- Add various new patches to get RK3288 booting to a prompt
- Make use of additional features since version 2
- Update README to mention available drivers
- Update clock rate to always be 24MHzChanges in v2:
- Drop use ofCONFIG_USE_PRIVATE_LIBGCC=y
- Tidy up license headers and remove SPL #ifdefsMasahiro Yamada (1):
dm: do not return pointer if NULL is given to devp ofdevice_bind()Simon Glass (32):
pinctrl: Correct build errors in thepinctrl_simple
pinctrl: Add help text toKconfig
pinctrl: Add the concept of peripheral IDs
mmc: Support bypass mode with theget_mmc_clk()method
dm: Improve handling of a missing uclass
dm: Provide better debugging when a device fails to bind
arm: reset: Avoid a build error when the reset uclass is enabled
rockchip: Add serial support
rockchip: Bring in RK3288 device tree file includes and bindings
rockchip: rk3288: dts: Make core devices available early
mkimage: Allow padding to any length
mkimage: Allow the original file size to be recorded
rockchip: Add the rkimage format to mkimage
rockchip: Add support for the SD image
rockchip: Add support for the SPI image
rockchip: gpio: Add rockchip GPIO driver
rockchip: Add basic peripheral and clock definitions
power: Add support for ACT8846 PMIC
power: regulator: Add a driver for ACT8846 regulators
rockchip: rk3288: Add clock driver
rockchip: rk3288: Add header files for PMU and GRF
rockchip: rk3288: Add SoC reset driver
rockchip: rk3288: Add a simple syscon driver
rockchip: rk3288: Add pinctrl driver
rockchip: rk3288: Add SDRAM init
rockchip: Add an MMC driver
rockchip: Add core SoC start-up code
rockchip: Add I2C driver
rockchip: Add SPI driver
rockchip: Add basic support for firefly-rk3288
rockchip: Add basic support for jerry
rockchip: Add a simple READMEarch/arm/Kconfig | 10 + arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 3 + arch/arm/dts/cros-ec-sbs.dtsi | 16 + arch/arm/dts/rk3288-firefly.dts | 75 + arch/arm/dts/rk3288-firefly.dtsi | 457 ++++++ arch/arm/dts/rk3288-jerry.dts | 203 +++ arch/arm/dts/rk3288-thermal.dtsi | 88 ++ arch/arm/dts/rk3288-veyron-chromebook.dtsi | 200 +++ arch/arm/dts/rk3288-veyron.dtsi | 844 +++++++++++ arch/arm/dts/rk3288.dtsi | 1473 ++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/clock.h | 45 + arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 185 +++ arch/arm/include/asm/arch-rockchip/ddr_rk3288.h | 484 +++++++ arch/arm/include/asm/arch-rockchip/gpio.h | 28 + arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 768 ++++++++++ arch/arm/include/asm/arch-rockchip/hardware.h | 20 + arch/arm/include/asm/arch-rockchip/i2c.h | 70 + arch/arm/include/asm/arch-rockchip/periph.h | 54 + arch/arm/include/asm/arch-rockchip/pmu_rk3288.h | 89 ++ arch/arm/include/asm/arch-rockchip/sdram.h | 92 ++ arch/arm/lib/Makefile | 2 + arch/arm/mach-rockchip/Kconfig | 41 + arch/arm/mach-rockchip/Makefile | 13 + arch/arm/mach-rockchip/board-spl.c | 290 ++++ arch/arm/mach-rockchip/board.c | 46 + arch/arm/mach-rockchip/common.c | 28 + arch/arm/mach-rockchip/rk3288/Kconfig | 26 + arch/arm/mach-rockchip/rk3288/Makefile | 9 + arch/arm/mach-rockchip/rk3288/reset_rk3288.c | 47 + arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 878 ++++++++++++ arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 25 + board/firefly/firefly-rk3288/Kconfig | 15 + board/firefly/firefly-rk3288/MAINTAINERS | 6 + board/firefly/firefly-rk3288/Makefile | 7 + board/firefly/firefly-rk3288/firefly-rk3288.c | 7 + board/google/chromebook_jerry/Kconfig | 15 + board/google/chromebook_jerry/MAINTAINERS | 6 + board/google/chromebook_jerry/Makefile | 7 + board/google/chromebook_jerry/jerry.c | 7 + board/google/common/Makefile | 2 +- common/image.c | 3 + configs/chromebook_jerry_defconfig | 43 + configs/firefly-rk3288_defconfig | 43 + doc/README.rockchip | 246 ++++ .../clock/rockchip,rk3188-cru.txt | 61 + .../clock/rockchip,rk3288-cru.txt | 61 + .../clock/rockchip,rk3288-dmc.txt | 155 ++ doc/device-tree-bindings/clock/rockchip.txt | 77 + .../pinctrl/rockchip,pinctrl.txt | 157 +++ .../thermal/rockchip-thermal.txt | 68 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3288.c | 618 ++++++++ drivers/core/device.c | 10 +- drivers/core/root.c | 5 +- drivers/core/uclass.c | 7 +- drivers/gpio/Kconfig | 9 + drivers/gpio/Makefile | 1 + drivers/gpio/rk_gpio.c | 123 ++ drivers/i2c/Kconfig | 9 + drivers/i2c/Makefile | 1 + drivers/i2c/rk_i2c.c | 391 ++++++ drivers/mmc/Kconfig | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/dw_mmc.c | 2 +- drivers/mmc/exynos_dw_mmc.c | 2 +- drivers/mmc/rockchip_mmc.c | 98 ++ drivers/pinctrl/Kconfig | 22 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-uclass.c | 41 +- drivers/pinctrl/rockchip/Makefile | 8 + drivers/pinctrl/rockchip/pinctrl_rk3288.c | 441 ++++++ drivers/power/pmic/Kconfig | 9 + drivers/power/pmic/Makefile | 1 + drivers/power/pmic/act8846.c | 90 ++ drivers/power/regulator/Kconfig | 9 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/act8846.c | 155 ++ drivers/serial/Kconfig | 9 + drivers/serial/Makefile | 1 + drivers/serial/serial_rockchip.c | 43 + drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/rk_spi.c | 375 +++++ drivers/spi/rk_spi.h | 121 ++ include/configs/chromebook_jerry.h | 16 + include/configs/firefly-rk3288.h | 15 + include/configs/rk3288_common.h | 98 ++ include/dm/pinctrl.h | 61 + include/dt-bindings/clock/rk3288-cru.h | 370 +++++ include/dt-bindings/clock/rockchip,rk808.h | 11 + include/dt-bindings/pinctrl/rockchip.h | 26 + include/dt-bindings/power-domain/rk3288.h | 11 + include/dwmmc.h | 16 +- include/image.h | 5 +- include/power/act8846_pmic.h | 37 + tools/Makefile | 3 + tools/imagetool.h | 1 + tools/mkimage.c | 23 +- tools/rkcommon.c | 72 + tools/rkcommon.h | 28 + tools/rkimage.c | 65 + tools/rksd.c | 102 ++ tools/rkspi.c | 119 ++ 104 files changed, 11274 insertions(+), 25 deletions(-)create mode 100644
arch/arm/dts/cros-ec-sbs.dtsi
create mode 100644arch/arm/dts/rk3288-firefly.dts
create mode 100644arch/arm/dts/rk3288-firefly.dtsi
create mode 100644arch/arm/dts/rk3288-jerry.dts
create mode 100644arch/arm/dts/rk3288-thermal.dtsi
create mode 100644arch/arm/dts/rk3288-veyron-chromebook.dtsicreate mode 100644arch/arm/dts/rk3288-veyron.dtsi
create mode 100644arch/arm/dts/rk3288.dtsi
create mode 100644arch/arm/include/asm/arch-rockchip/clock.hcreate mode 100644arch/arm/include/asm/arch-rockchip/cru_rk3288.hcreate mode 100644arch/arm/include/asm/arch-rockchip/ddr_rk3288.hcreate mode 100644arch/arm/include/asm/arch-rockchip/gpio.hcreate mode 100644arch/arm/include/asm/arch-rockchip/grf_rk3288.hcreate mode 100644arch/arm/include/asm/arch-rockchip/hardware.hcreate mode 100644arch/arm/include/asm/arch-rockchip/i2c.hcreate mode 100644arch/arm/include/asm/arch-rockchip/periph.hcreate mode 100644arch/arm/include/asm/arch-rockchip/pmu_rk3288.hcreate mode 100644arch/arm/include/asm/arch-rockchip/sdram.hcreate mode 100644arch/arm/mach-rockchip/Kconfig
create mode 100644arch/arm/mach-rockchip/Makefile
create mode 100644arch/arm/mach-rockchip/board-spl.c
create mode 100644arch/arm/mach-rockchip/board.c
create mode 100644arch/arm/mach-rockchip/common.c
create mode 100644arch/arm/mach-rockchip/rk3288/Kconfigcreate mode 100644arch/arm/mach-rockchip/rk3288/Makefilecreate mode 100644arch/arm/mach-rockchip/rk3288/reset_rk3288.ccreate mode 100644arch/arm/mach-rockchip/rk3288/sdram_rk3288.ccreate mode 100644arch/arm/mach-rockchip/rk3288/syscon_rk3288.ccreate mode 100644 board/firefly/firefly-rk3288/Kconfig create mode 100644 board/firefly/firefly-rk3288/MAINTAINERS create mode 100644 board/firefly/firefly-rk3288/Makefile create mode 100644board/firefly/firefly-rk3288/firefly-rk3288.ccreate mode 100644 board/google/chromebook_jerry/Kconfig create mode 100644 board/google/chromebook_jerry/MAINTAINERS create mode 100644 board/google/chromebook_jerry/Makefile create mode 100644board/google/chromebook_jerry/jerry.ccreate mode 100644 configs/chromebook_jerry_defconfig
create mode 100644 configs/firefly-rk3288_defconfig
create mode 100644 doc/README.rockchip
create mode 100644doc/device-tree-bindings/clock/rockchip,rk3188-cru.txtcreate mode 100644doc/device-tree-bindings/clock/rockchip,rk3288-cru.txtcreate mode 100644doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txtcreate mode 100644doc/device-tree-bindings/clock/rockchip.txtcreate mode 100644doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txtcreate mode 100644doc/device-tree-bindings/thermal/rockchip-thermal.txtcreate mode 100644drivers/clk/clk_rk3288.c
create mode 100644drivers/gpio/rk_gpio.c
create mode 100644drivers/i2c/rk_i2c.c
create mode 100644drivers/mmc/rockchip_mmc.c
create mode 100644drivers/pinctrl/rockchip/Makefile
create mode 100644drivers/pinctrl/rockchip/pinctrl_rk3288.ccreate mode 100644drivers/power/pmic/act8846.c
create mode 100644drivers/power/regulator/act8846.c
create mode 100644drivers/serial/serial_rockchip.c
create mode 100644drivers/spi/rk_spi.c
create mode 100644drivers/spi/rk_spi.h
create mode 100644include/configs/chromebook_jerry.h
create mode 100644include/configs/firefly-rk3288.h
create mode 100644include/configs/rk3288_common.h
create mode 100644include/dt-bindings/clock/rk3288-cru.hcreate mode 100644include/dt-bindings/clock/rockchip,rk808.hcreate mode 100644include/dt-bindings/pinctrl/rockchip.hcreate mode 100644include/dt-bindings/power-domain/rk3288.hcreate mode 100644include/power/act8846_pmic.h
create mode 100644tools/rkcommon.c
create mode 100644tools/rkcommon.h
create mode 100644tools/rkimage.c
create mode 100644tools/rksd.c
create mode 100644tools/rkspi.c--
2.5.0.457.gab17608
v4 cover dm: Introduce Rockchip RK3288 support
Hi Simon,
Thank you so much for your response.
If there is no new framework, I may first follow the following API which U-boot has defined
in the file include/common.h, such as:
/* $(CPU)/interrupts.c */
int interrupt_init (void);
void irq_install_handler(int, interrupt_handler_t *, void *);
void irq_free_handler (int);
void enable_interrupts (void);
int disable_interrupts (void);
Regards,
????CWZ?
cwz at rock-chips.com
???+86-0591-83991906?8090
??????????? Fuzhou Rockchip Electronics Co.Ltd
????????????????89????A?21?? (350003)
Addr : No. 21 Building, A District, No.89,software Boulevard Fuzhou,Fujian,PRC
****************************************************************************
??????????????????????????????????????????????????? ??????????????????????????????????????????????????????????????????????????????????????????????????
IMPORTANT NOTICE: This email is from Fuzhou Rockchip Electronics Co., Ltd .The contents of this email and any attachments may contain information that is privileged, confidential and/or exempt from disclosure under applicable law and relevant NDA. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information is STRICTLY PROHIBITED. Please immediately contact the sender as soon as possible and destroy the material in its entirety in any format. Thank you.
****************************************************************************
From: Simon Glass
Date: 2015-11-10 04:24
To: cwz at rock-chips.com
CC: U-Boot Mailing List; Andre Przywara; FUKAUMI Naoki; Huang, Tao; Ulrich Prinz; Sjoerd Simons; Joe Hershberger; Pantelis Antoniou; Marek Vasut; Albert Aribaud; Lukasz Majewski; Pavel Herrmann
Subject: Re: [PATCH v4 00/33] dm: Introduce Rockchip RK3288 support
Hi,
Quoted 10 lines · cwz at rock-chips.com
Hi Simon,
Do you have plan to support interrupt controller driver for U-Boot?
On Rockchip SDK uboot?interrupt is enabled, usb driver using interrupt for speed up programing images.
U-Boot code has no a good interrupt controller driver platform, especially when u-boot using dtb.
So, I haven't a good idea if I want to upstream rockchip interrupt driver, do you have any suggestion?
You could try writing a driver and some code to parse the device tree. We could even have a new interrupt uclass if you like.
I do not have a plan myself at present, but I can help (perhaps with tests and sandbox) if you make a start.
Regards,
Simon
Quoted 345 lines
Regards,
________________________________
????CWZ?cwz at rock-chips.com
???+86-0591-83991906?8090
??????????? Fuzhou Rockchip Electronics Co.Ltd ????????????????89????A?21?? (350003)
Addr : No. 21 Building, A District, No.89,software Boulevard Fuzhou,Fujian,PRC****************************************************************************
??????????????????????????????????????????????????? ?????????????????????????????????????????????????????????????????????????????????????????????????? IMPORTANT NOTICE: This email is from Fuzhou Rockchip Electronics Co., Ltd
.The contents of this email and any attachments may contain information that
is privileged, confidential and/or exempt from disclosure under applicable
law and relevant NDA. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the
information is STRICTLY PROHIBITED. Please immediately contact the sender as
soon as possible and destroy the material in its entirety in any format.
Thank you.
****************************************************************************From: Simon Glass
Date: 2015-08-24 23:12
To: U-Boot Mailing List
CC: Andre Przywara; FUKAUMI Naoki; huangtao; cwx; Ulrich Prinz; Sjoerd Simons; Simon Glass; Joe Hershberger; Pantelis Antoniou; Marek Vasut; Albert Aribaud; Lukasz Majewski; Pavel Herrmann
Subject: [PATCH v4 00/33] dm: Introduce Rockchip RK3288 supportThe Rockchip RK3288 is based on a quad-core Cortex-A17 CPU and has a good set of peripherals. Various full-featured U-Boot ports are available and this is an attempt to bring those features into mainline. With this series the Firefly RK3288 can boot to a prompt from an SD card.
Since much of the code is generic, this also supports the Radxa Rock 2. Since there is no device tree available for that yet, it uses the same config and device tree as the Firefly. This works because not all peripherals are supported, so the differences don't matter.
Support for booting from USB OTG is also provided, using the on-chip boot ROM and the rkflashtool utility. This can boot as far as SPL, but there is no support for reading U-Boot proper from USB as yet. This requires implementing a suitable protocol (perhaps DFU or Rockchip's proprietary one) in SPL.
Support is also provided for the Hisense Chromebook, which is based on the same SoC. In this case it boots from SPI rather than an SD card.
This seriea makes use of driver model including a number of recently added uclasses:
- Clocks - setting and getting PLL and peripheral clocks
- Pinctrl - adjusting pin multiplexing settings
- Reset - reseting the board or SoC
- RAM - setting up RAM controllers and detecting the available RAM
- MMC - MMC controllers (using the existing block device framework)
- LEDs - turning LEDs on and off, with only a GPIO driver so farThis series avoids hard-coding RK3288-specific code into the build. There is a
CONFIG_ROCKCHIP_RK3288but it only *adds* support for RK3288. In principle another CONFIG could add support for a different Rockchip SoC with only the device tree selecting which one U-Boot works on.Support is provided in mkimage to build these image types:
- rkimage - suitable for packaging up SPL to be sent to the boot ROM over USB OTG
- rksd - suitable for writing to an SD cardMuch of the source and ideas for this series came from downstream Rockchip U-Boot trees. SDRAM init came from Coreboot. In most cases it has been pretty heavily cleaned up / rewritten to meet U-Boot style and remove hard-coding of things.
Drivers are provided for:
- Clocks
- Pinctrl
- SoC reset
- DDR3 SDRAM
- I2C
- SPI
- GPIOs
- LEDs using GPIOS
- MMC
- Firefly main PMIC (ACT8846) and included regulatorsThese are lightly tested and doubtless some problems exist with some, particularly I2C.
One problem with device tree is that U-Boot has no way of dropping features it does not need or use. For SPL this problem needs to be solved and this series uses a new 'fdtgrep' tool for this. The 45KB Firefly device tree reduces to a 6KB bytes when unused material is removed. SDRAM timings are also in the device tree.
There is a large amount of additional work to bring other Rockchip drivers and features into mainline U-Boot, so this is only a start.
Note: This series sits on top of Masahiro's RFC pinctrl series. I wanted to get a new version out while we wait for this to make it to mainline. You can find this series at u-boot-dm/rockchip-working.
Changes in v4:
- Add aset_state_simple()method
- Adjust the defconfig file to suit mainline
- Renamepinctrl.htodm/pinctrl.h
- Tweak the cover letter a little, drop mention of patches already applied
- UseCONFIG_SPL_LEDinstead ofCONFIG_SPL_LED_SUPPORTChanges in v3:
- Add device tree bindings for CRU and DMC
- Add various new patches to get RK3288 booting to a prompt
- Make use of additional features since version 2
- Update README to mention available drivers
- Update clock rate to always be 24MHzChanges in v2:
- Drop use ofCONFIG_USE_PRIVATE_LIBGCC=y
- Tidy up license headers and remove SPL #ifdefsMasahiro Yamada (1):
dm: do not return pointer if NULL is given to devp ofdevice_bind()Simon Glass (32):
pinctrl: Correct build errors in thepinctrl_simple
pinctrl: Add help text toKconfig
pinctrl: Add the concept of peripheral IDs
mmc: Support bypass mode with theget_mmc_clk()method
dm: Improve handling of a missing uclass
dm: Provide better debugging when a device fails to bind
arm: reset: Avoid a build error when the reset uclass is enabled
rockchip: Add serial support
rockchip: Bring in RK3288 device tree file includes and bindings
rockchip: rk3288: dts: Make core devices available early
mkimage: Allow padding to any length
mkimage: Allow the original file size to be recorded
rockchip: Add the rkimage format to mkimage
rockchip: Add support for the SD image
rockchip: Add support for the SPI image
rockchip: gpio: Add rockchip GPIO driver
rockchip: Add basic peripheral and clock definitions
power: Add support for ACT8846 PMIC
power: regulator: Add a driver for ACT8846 regulators
rockchip: rk3288: Add clock driver
rockchip: rk3288: Add header files for PMU and GRF
rockchip: rk3288: Add SoC reset driver
rockchip: rk3288: Add a simple syscon driver
rockchip: rk3288: Add pinctrl driver
rockchip: rk3288: Add SDRAM init
rockchip: Add an MMC driver
rockchip: Add core SoC start-up code
rockchip: Add I2C driver
rockchip: Add SPI driver
rockchip: Add basic support for firefly-rk3288
rockchip: Add basic support for jerry
rockchip: Add a simple READMEarch/arm/Kconfig | 10 + arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 3 + arch/arm/dts/cros-ec-sbs.dtsi | 16 + arch/arm/dts/rk3288-firefly.dts | 75 + arch/arm/dts/rk3288-firefly.dtsi | 457 ++++++ arch/arm/dts/rk3288-jerry.dts | 203 +++ arch/arm/dts/rk3288-thermal.dtsi | 88 ++ arch/arm/dts/rk3288-veyron-chromebook.dtsi | 200 +++ arch/arm/dts/rk3288-veyron.dtsi | 844 +++++++++++ arch/arm/dts/rk3288.dtsi | 1473 ++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/clock.h | 45 + arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 185 +++ arch/arm/include/asm/arch-rockchip/ddr_rk3288.h | 484 +++++++ arch/arm/include/asm/arch-rockchip/gpio.h | 28 + arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 768 ++++++++++ arch/arm/include/asm/arch-rockchip/hardware.h | 20 + arch/arm/include/asm/arch-rockchip/i2c.h | 70 + arch/arm/include/asm/arch-rockchip/periph.h | 54 + arch/arm/include/asm/arch-rockchip/pmu_rk3288.h | 89 ++ arch/arm/include/asm/arch-rockchip/sdram.h | 92 ++ arch/arm/lib/Makefile | 2 + arch/arm/mach-rockchip/Kconfig | 41 + arch/arm/mach-rockchip/Makefile | 13 + arch/arm/mach-rockchip/board-spl.c | 290 ++++ arch/arm/mach-rockchip/board.c | 46 + arch/arm/mach-rockchip/common.c | 28 + arch/arm/mach-rockchip/rk3288/Kconfig | 26 + arch/arm/mach-rockchip/rk3288/Makefile | 9 + arch/arm/mach-rockchip/rk3288/reset_rk3288.c | 47 + arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 878 ++++++++++++ arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 25 + board/firefly/firefly-rk3288/Kconfig | 15 + board/firefly/firefly-rk3288/MAINTAINERS | 6 + board/firefly/firefly-rk3288/Makefile | 7 + board/firefly/firefly-rk3288/firefly-rk3288.c | 7 + board/google/chromebook_jerry/Kconfig | 15 + board/google/chromebook_jerry/MAINTAINERS | 6 + board/google/chromebook_jerry/Makefile | 7 + board/google/chromebook_jerry/jerry.c | 7 + board/google/common/Makefile | 2 +- common/image.c | 3 + configs/chromebook_jerry_defconfig | 43 + configs/firefly-rk3288_defconfig | 43 + doc/README.rockchip | 246 ++++ .../clock/rockchip,rk3188-cru.txt | 61 + .../clock/rockchip,rk3288-cru.txt | 61 + .../clock/rockchip,rk3288-dmc.txt | 155 ++ doc/device-tree-bindings/clock/rockchip.txt | 77 + .../pinctrl/rockchip,pinctrl.txt | 157 +++ .../thermal/rockchip-thermal.txt | 68 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3288.c | 618 ++++++++ drivers/core/device.c | 10 +- drivers/core/root.c | 5 +- drivers/core/uclass.c | 7 +- drivers/gpio/Kconfig | 9 + drivers/gpio/Makefile | 1 + drivers/gpio/rk_gpio.c | 123 ++ drivers/i2c/Kconfig | 9 + drivers/i2c/Makefile | 1 + drivers/i2c/rk_i2c.c | 391 ++++++ drivers/mmc/Kconfig | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/dw_mmc.c | 2 +- drivers/mmc/exynos_dw_mmc.c | 2 +- drivers/mmc/rockchip_mmc.c | 98 ++ drivers/pinctrl/Kconfig | 22 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-uclass.c | 41 +- drivers/pinctrl/rockchip/Makefile | 8 + drivers/pinctrl/rockchip/pinctrl_rk3288.c | 441 ++++++ drivers/power/pmic/Kconfig | 9 + drivers/power/pmic/Makefile | 1 + drivers/power/pmic/act8846.c | 90 ++ drivers/power/regulator/Kconfig | 9 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/act8846.c | 155 ++ drivers/serial/Kconfig | 9 + drivers/serial/Makefile | 1 + drivers/serial/serial_rockchip.c | 43 + drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/rk_spi.c | 375 +++++ drivers/spi/rk_spi.h | 121 ++ include/configs/chromebook_jerry.h | 16 + include/configs/firefly-rk3288.h | 15 + include/configs/rk3288_common.h | 98 ++ include/dm/pinctrl.h | 61 + include/dt-bindings/clock/rk3288-cru.h | 370 +++++ include/dt-bindings/clock/rockchip,rk808.h | 11 + include/dt-bindings/pinctrl/rockchip.h | 26 + include/dt-bindings/power-domain/rk3288.h | 11 + include/dwmmc.h | 16 +- include/image.h | 5 +- include/power/act8846_pmic.h | 37 + tools/Makefile | 3 + tools/imagetool.h | 1 + tools/mkimage.c | 23 +- tools/rkcommon.c | 72 + tools/rkcommon.h | 28 + tools/rkimage.c | 65 + tools/rksd.c | 102 ++ tools/rkspi.c | 119 ++ 104 files changed, 11274 insertions(+), 25 deletions(-)create mode 100644
arch/arm/dts/cros-ec-sbs.dtsi
create mode 100644arch/arm/dts/rk3288-firefly.dts
create mode 100644arch/arm/dts/rk3288-firefly.dtsi
create mode 100644arch/arm/dts/rk3288-jerry.dts
create mode 100644arch/arm/dts/rk3288-thermal.dtsi
create mode 100644arch/arm/dts/rk3288-veyron-chromebook.dtsicreate mode 100644arch/arm/dts/rk3288-veyron.dtsi
create mode 100644arch/arm/dts/rk3288.dtsi
create mode 100644arch/arm/include/asm/arch-rockchip/clock.hcreate mode 100644arch/arm/include/asm/arch-rockchip/cru_rk3288.hcreate mode 100644arch/arm/include/asm/arch-rockchip/ddr_rk3288.hcreate mode 100644arch/arm/include/asm/arch-rockchip/gpio.hcreate mode 100644arch/arm/include/asm/arch-rockchip/grf_rk3288.hcreate mode 100644arch/arm/include/asm/arch-rockchip/hardware.hcreate mode 100644arch/arm/include/asm/arch-rockchip/i2c.hcreate mode 100644arch/arm/include/asm/arch-rockchip/periph.hcreate mode 100644arch/arm/include/asm/arch-rockchip/pmu_rk3288.hcreate mode 100644arch/arm/include/asm/arch-rockchip/sdram.hcreate mode 100644arch/arm/mach-rockchip/Kconfig
create mode 100644arch/arm/mach-rockchip/Makefile
create mode 100644arch/arm/mach-rockchip/board-spl.c
create mode 100644arch/arm/mach-rockchip/board.c
create mode 100644arch/arm/mach-rockchip/common.c
create mode 100644arch/arm/mach-rockchip/rk3288/Kconfigcreate mode 100644arch/arm/mach-rockchip/rk3288/Makefilecreate mode 100644arch/arm/mach-rockchip/rk3288/reset_rk3288.ccreate mode 100644arch/arm/mach-rockchip/rk3288/sdram_rk3288.ccreate mode 100644arch/arm/mach-rockchip/rk3288/syscon_rk3288.ccreate mode 100644 board/firefly/firefly-rk3288/Kconfig create mode 100644 board/firefly/firefly-rk3288/MAINTAINERS create mode 100644 board/firefly/firefly-rk3288/Makefile create mode 100644board/firefly/firefly-rk3288/firefly-rk3288.ccreate mode 100644 board/google/chromebook_jerry/Kconfig create mode 100644 board/google/chromebook_jerry/MAINTAINERS create mode 100644 board/google/chromebook_jerry/Makefile create mode 100644board/google/chromebook_jerry/jerry.ccreate mode 100644 configs/chromebook_jerry_defconfig
create mode 100644 configs/firefly-rk3288_defconfig
create mode 100644 doc/README.rockchip
create mode 100644doc/device-tree-bindings/clock/rockchip,rk3188-cru.txtcreate mode 100644doc/device-tree-bindings/clock/rockchip,rk3288-cru.txtcreate mode 100644doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txtcreate mode 100644doc/device-tree-bindings/clock/rockchip.txtcreate mode 100644doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txtcreate mode 100644doc/device-tree-bindings/thermal/rockchip-thermal.txtcreate mode 100644drivers/clk/clk_rk3288.c
create mode 100644drivers/gpio/rk_gpio.c
create mode 100644drivers/i2c/rk_i2c.c
create mode 100644drivers/mmc/rockchip_mmc.c
create mode 100644drivers/pinctrl/rockchip/Makefile
create mode 100644drivers/pinctrl/rockchip/pinctrl_rk3288.ccreate mode 100644drivers/power/pmic/act8846.c
create mode 100644drivers/power/regulator/act8846.c
create mode 100644drivers/serial/serial_rockchip.c
create mode 100644drivers/spi/rk_spi.c
create mode 100644drivers/spi/rk_spi.h
create mode 100644include/configs/chromebook_jerry.h
create mode 100644include/configs/firefly-rk3288.h
create mode 100644include/configs/rk3288_common.h
create mode 100644include/dt-bindings/clock/rk3288-cru.hcreate mode 100644include/dt-bindings/clock/rockchip,rk808.hcreate mode 100644include/dt-bindings/pinctrl/rockchip.hcreate mode 100644include/dt-bindings/power-domain/rk3288.hcreate mode 100644include/power/act8846_pmic.h
create mode 100644tools/rkcommon.c
create mode 100644tools/rkcommon.h
create mode 100644tools/rkimage.c
create mode 100644tools/rksd.c
create mode 100644tools/rkspi.c--
2.5.0.457.gab17608
v4 cover dm: Introduce Rockchip RK3288 support
Hi,
Quoted 8 lines · cwz at rock-chips.com
Hi Simon,
Thank you so much for your response.
If there is no new framework, I may first follow the following API which U-boot has defined
in the fileinclude/common.h, such as:
Quoted 7 lines
/* $(CPU)/interrupts.c */
intinterrupt_init(void);
voidirq_install_handler(int, interrupt_handler_t *, void *);
voidirq_free_handler(int);void
enable_interrupts(void);
intdisable_interrupts(void);
That seems fine to me.
Regards,
Simon
[snip]