Fixes on gdsys boards and some new functionality

142 lines not on this page · raw message

index 8a5efe7..f8d8322 100644
@@ -143,7 +143,7 @@ struct ihs_fpga {
 	u16 reserved_2[2];	/* 0x001c */
 	struct ihs_io_ep ep;	/* 0x0020 */
 	u16 reserved_3[9];	/* 0x002e */
-	struct ihs_i2c i2c;	/* 0x0040 */
+	struct ihs_i2c i2c0;	/* 0x0040 */
 	u16 reserved_4[10];	/* 0x004c */
 	u16 mc_int;		/* 0x0060 */
 	u16 mc_int_en;		/* 0x0062 */

@@ -177,7 +177,7 @@ struct ihs_fpga {
 	u16 reserved_2[2];	/* 0x001c */
 	struct ihs_io_ep ep;	/* 0x0020 */
 	u16 reserved_3[9];	/* 0x002e */
-	struct ihs_i2c i2c;	/* 0x0040 */
+	struct ihs_i2c i2c0;	/* 0x0040 */
 	u16 reserved_4[10];	/* 0x004c */
 	u16 mc_int;		/* 0x0060 */
 	u16 mc_int_en;		/* 0x0062 */

@@ -208,10 +208,12 @@ struct ihs_fpga {
 	u16 reserved_1[29];	/* 0x001e */
 	u16 mpc3w_control;	/* 0x0058 */
 	u16 reserved_2[3];	/* 0x005a */
-	struct ihs_i2c i2c;	/* 0x0060 */
-	u16 reserved_3[205];	/* 0x0066 */
+	struct ihs_i2c i2c0;	/* 0x0060 */
+	u16 reserved_3[2];	/* 0x006c */
+	struct ihs_i2c i2c1;	/* 0x0070 */
+	u16 reserved_4[194];	/* 0x007c */
 	struct ihs_osd osd;	/* 0x0200 */
-	u16 reserved_4[761];	/* 0x020e */
+	u16 reserved_5[761];	/* 0x020e */
 	u16 videomem[31736];	/* 0x0800 */
 };
 #endif

index 737beaf..e001459 100644
@@ -13,24 +13,28 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 #define I2C_SET_REG(fld, val) \
-	{ if (I2C_ADAP_HWNR & 0x10) \
-		FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
-	else \
-		FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); }
+	do { \
+		if (I2C_ADAP_HWNR & 0x10) \
+			FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
+		else \
+			FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
+	} while (0)
 #else
 #define I2C_SET_REG(fld, val) \
-		FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val);
+		FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
 #endif
 
 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 #define I2C_GET_REG(fld, val) \
-	{ if (I2C_ADAP_HWNR & 0x10) \
-		FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
-	else \
-		FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); }
+	do {					\
+		if (I2C_ADAP_HWNR & 0x10) \
+			FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
+		else \
+			FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
+	} while (0)
 #else
 #define I2C_GET_REG(fld, val) \
-		FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val);
+		FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
 #endif
 
 enum {

index e001459..b05c15f 100644
@@ -135,7 +135,7 @@ static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, uint addr,
 	if (len <= 0)
 		return 1;
 
-	if (ihs_i2c_address(chip, addr, alen, !read))
+	if (ihs_i2c_address(chip, addr, alen, len))
 		return 1;
 
 	while (len) {

index 7eb15ed..baace38 100644
@@ -77,6 +77,8 @@ void dp501_powerup(u8 addr)
 	i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */
 #endif
 
+	i2c_reg_write(addr + 2, 0x1a, 0x04); /* SPDIF input method TTL */
+
 	i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
 	i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
 	i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */

index baace38..0389fd1 100644
@@ -88,7 +88,8 @@ void dp501_powerup(u8 addr)
 	dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
 	i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
 	i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
-	i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
+	i2c_reg_write(addr, 0x87, 0x7f); /* set retry counter as 7
+					    retry interval 400us */
 
 	if (dp501_detect_cable_adapter(addr)) {
 		printf("DVI/HDMI cable adapter detected\n");

index 0389fd1..d35aee0 100644
@@ -40,11 +40,29 @@ static int dp501_detect_cable_adapter(u8 addr)
 static void dp501_link_training(u8 addr)
 {
 	u8 val;
+	u8 link_bw;
+	u8 max_lane_cnt;
+	u8 lane_cnt;
 
 	val = i2c_reg_read(addr, 0x51);
-	i2c_reg_write(addr, 0x5d, val); /* set link_bw */
+	if (val >= 0x0a)
+		link_bw = 0x0a;
+	else
+		link_bw = 0x06;
+	if (link_bw != val)
+		printf("DP sink supports %d Mbps link rate, set to %d Mbps\n",
+		       val * 270, link_bw * 270);
+	i2c_reg_write(addr, 0x5d, link_bw); /* set link_bw */
 	val = i2c_reg_read(addr, 0x52);
-	i2c_reg_write(addr, 0x5e, val); /* set lane_cnt */
+	max_lane_cnt = val & 0x1f;
+	if (max_lane_cnt >= 4)
+		lane_cnt = 4;
+	else
+		lane_cnt = max_lane_cnt;
+	if (lane_cnt != max_lane_cnt)
+		printf("DP sink supports %d lanes, set to %d lanes\n",
+		       max_lane_cnt, lane_cnt);
+	i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */
 	val = i2c_reg_read(addr, 0x53);
 	i2c_reg_write(addr, 0x5c, val); /* set downspread_ctl */
 

index 35dfbbc..54c7eb3 100644
@@ -25,17 +25,19 @@
 #define LATCH2_MC2_PRESENT_N 0x0080
 
 enum {
-	UNITTYPE_VIDEO_USER = 0,
-	UNITTYPE_MAIN_USER = 1,
-	UNITTYPE_VIDEO_SERVER = 2,
-	UNITTYPE_MAIN_SERVER = 3,
+	UNITTYPE_MAIN = 1<<0,
+	UNITTYPE_SERVER = 1<<1,
+	UNITTYPE_DISPLAYPORT = 1<<2,
 };
 
 enum {
 	HWVER_101 = 0,
 	HWVER_110 = 1,
-	HWVER_120 = 2,
-	HWVER_130 = 3,
+	HWVER_130 = 2,
+	HWVER_140 = 3,
+	HWVER_150 = 4,
+	HWVER_160 = 5,
+	HWVER_170 = 6,
 };
 
 enum {

@@ -121,43 +123,48 @@ static void print_fpga_info(unsigned dev)
 	feature_carriers = (fpga_features >> 2) & 0x0003;
 	feature_video_channels = fpga_features & 0x0003;
 
-	switch (unit_type) {
-	case UNITTYPE_VIDEO_USER:
-		printf("Videochannel Userside");
-		break;
+	if (unit_type & UNITTYPE_MAIN)
+		printf("Mainchannel ");
+	else
+		printf("Videochannel ");
 
-	case UNITTYPE_MAIN_USER:
-		printf("Mainchannel Userside");
-		break;
+	if (unit_type & UNITTYPE_SERVER)
+		printf("Serverside ");
+	else
+		printf("Userside ");
+
+	if (unit_type & UNITTYPE_DISPLAYPORT)
+		printf("DisplayPort");
+	else
+		printf("DVI-DL");
 
-	case UNITTYPE_VIDEO_SERVER:
-		printf("Videochannel Serverside");
+	switch (hardware_version) {
+	case HWVER_101:
+		printf(" HW-Ver 1.01\n");
 		break;
 
-	case UNITTYPE_MAIN_SERVER:
-		printf("Mainchannel Serverside");
+	case HWVER_110:
+		printf(" HW-Ver 1.10-1.20\n");
 		break;
 
-	default:
-		printf("UnitType %d(not supported)", unit_type);
+	case HWVER_130:
+		printf(" HW-Ver 1.30\n");
 		break;
-	}
 
-	switch (hardware_version) {
-	case HWVER_101:
-		printf(" HW-Ver 1.01\n");
+	case HWVER_140:
+		printf(" HW-Ver 1.40-1.43\n");
 		break;
 
-	case HWVER_110:
-		printf(" HW-Ver 1.10-1.12\n");
+	case HWVER_150:
+		printf(" HW-Ver 1.50\n");
 		break;
 
-	case HWVER_120:
-		printf(" HW-Ver 1.20\n");
+	case HWVER_160:
+		printf(" HW-Ver 1.60-1.61\n");
 		break;
 
-	case HWVER_130:
-		printf(" HW-Ver 1.30\n");
+	case HWVER_170:
+		printf(" HW-Ver 1.70\n");
 		break;
 
 	default:

@@ -260,7 +267,7 @@ int last_stage_init(void)
 	if (get_mc2_present())
 		print_fpga_info(1);
 
-	if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
+	if (((versions >> 4) & 0x000f) & UNITTYPE_SERVER)
 		return 0;
 
 	if (!get_fpga_state(0) || (get_hwver() == HWVER_101))

index e6bfe58..08cd1dd 100644
@@ -69,7 +69,7 @@
 #undef CONFIG_CMD_DIAG
 #undef CONFIG_CMD_EEPROM
 #undef CONFIG_CMD_ELF
-#undef CONFIG_CMD_I2C
+#define CONFIG_CMD_I2C
 #undef CONFIG_CMD_IRQ
 
 /*

@@ -107,17 +107,22 @@
 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
 
 #define CONFIG_SYS_I2C_IHS
+#define CONFIG_SYS_I2C_IHS_DUAL
 #define CONFIG_SYS_I2C_IHS_CH0
 #define CONFIG_SYS_I2C_IHS_SPEED_0		50000
 #define CONFIG_SYS_I2C_IHS_SLAVE_0		0x7F
+#define CONFIG_SYS_I2C_IHS_SPEED_0_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0_1		0x7F
 #define CONFIG_SYS_I2C_IHS_CH1
 #define CONFIG_SYS_I2C_IHS_SPEED_1		50000
 #define CONFIG_SYS_I2C_IHS_SLAVE_1		0x7F
+#define CONFIG_SYS_I2C_IHS_SPEED_1_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1_1		0x7F
 
-#define CONFIG_SYS_SPD_BUS_NUM		2
+#define CONFIG_SYS_SPD_BUS_NUM		4
 
 /* Temp sensor/hwmon/dtt */
-#define CONFIG_SYS_DTT_BUS_NUM	2
+#define CONFIG_SYS_DTT_BUS_NUM	4
 #define CONFIG_DTT_LM63		1	/* National LM63	*/
 #define CONFIG_DTT_SENSORS	{ 0x4c, 0x4e, 0x18 } /* Sensor addresses */
 #define CONFIG_DTT_PWM_LOOKUPTABLE	\

@@ -125,8 +130,9 @@
 		  { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
 #define CONFIG_DTT_TACH_LIMIT	0xa10
 
-#define CONFIG_SYS_ICS8N3QV01_I2C	{0, 1}
-#define CONFIG_SYS_SIL1178_I2C		{0, 1}
+#define CONFIG_SYS_ICS8N3QV01_I2C	{1, 3}
+#define CONFIG_SYS_SIL1178_I2C		{0, 2}
+#define CONFIG_SYS_DP501_I2C		{0, 2}
 
 /* EBC peripherals */
 

@@ -329,5 +335,7 @@
  */
 #define CONFIG_SYS_MPC92469AC
 #define CONFIG_SYS_OSD_SCREENS		CONFIG_SYS_FPGA_COUNT
+#define CONFIG_SYS_DP501_DIFFERENTIAL
+#define CONFIG_SYS_DP501_VCAPCTRL0	0x01 /* DDR mode 0, DE for H/VSYNC */
 
 #endif	/* __CONFIG_H */

index 64d90dd..2f98e47 100644
@@ -57,6 +57,8 @@ struct ihs_fpga {
 	u32 versions;		/* 0x0004 */
 	u32 fpga_version;	/* 0x0008 */
 	u32 fpga_features;	/* 0x000c */
+	u32 reserved[4];	/* 0x0010 */
+	u32 control;		/* 0x0020 */
 };
 
 #ifndef CONFIG_TRAILBLAZER

@@ -384,6 +386,9 @@ static void hydra_initialize(void)
 		fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
 			PCI_REGION_MEM);
 
+		/* disable sideband clocks */
+		writel(1, &fpga->control);
+
 		versions = readl(&fpga->versions);
 		fpga_version = readl(&fpga->fpga_version);
 		fpga_features = readl(&fpga->fpga_features);

index 3a51d86..7484624 100644
@@ -381,7 +381,7 @@ int last_stage_init(void)
 		ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
 	}
 
-	/* wait for FPGA done */
+	/* wait for FPGA done; then reset FPGA */
 	for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
 		unsigned int ctr = 0;
 

@@ -396,6 +396,12 @@ int last_stage_init(void)
 				break;
 			}
 		}
+
+		pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
+		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
+		udelay(10);
+		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
+				MCFPGA_RESET_N);
 	}
 
 	if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {

index 558edfc..f1a69a3 100644
@@ -361,7 +361,6 @@
 #define CONFIG_SYS_I2C_SOFT_SLAVE_4		0x7F
 
 #define CONFIG_SYS_ICS8N3QV01_I2C		{5, 6, 7, 8}
-#define CONFIG_SYS_CH7301_I2C			{5, 6, 7, 8}
 #define CONFIG_SYS_DP501_I2C			{1, 2, 3, 4}
 
 #ifndef __ASSEMBLY__

177 lines not on this page · raw message

new file mode 100644
index 0000000..25a8367
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach at gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ADV7611_H_
+#define _ADV7611_H_
+
+int adv7611_probe(unsigned int screen);
+
+#endif

64 lines not on this page · raw message

new file mode 100644
index 0000000..8383719
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach at gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CH7301_H_
+#define _CH7301_H_
+
+int ch7301_probe(unsigned screen, bool power);
+
+#endif

227 lines not on this page · raw message

new file mode 100644
index 0000000..44f7139
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, [email protected]
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _IOEP_FPGA_H_
+#define _IOEP_FPGA_H_
+
+void ioep_fpga_print_info(unsigned int fpga);
+bool ioep_fpga_has_osd(unsigned int fpga);
+
+#endif

70 lines not on this page · raw message

index 440b276..5b3f14b 100644
@@ -8,6 +8,7 @@
 #ifndef _OSD_H_
 #define _OSD_H_
 
+int ch7301_probe(unsigned screen, bool power);
 int osd_probe(unsigned screen);
 
 #endif

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index 18d37dc..96f02d6 100644
@@ -43,6 +43,7 @@ enum {
 enum {
 	RAM_DDR2_32 = 0,
 	RAM_DDR3_32 = 1,
+	RAM_DDR3_48 = 2,
 };
 
 enum {

@@ -215,6 +216,10 @@ void ioep_fpga_print_info(unsigned int fpga)
 		printf(", RAM 32 bit DDR3");
 		break;
 
+	case RAM_DDR3_48:
+		printf(", RAM 48 bit DDR3");
+		break;
+
 	default:
 		printf(", RAM %d(not supported)", feature_ramconfig);
 		break;

271 lines not on this page · raw message

index 29c85c8..5492718 100644
@@ -119,7 +119,7 @@ int last_stage_init(void)
 	int slaves;
 	unsigned int k;
 	unsigned int mux_ch;
-	unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
+	unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
 	u16 fpga_features;
 	bool hw_type_cat = pca9698_get_value(0x20, 20);
 	bool ch0_rgmii2_present = false;

@@ -131,7 +131,7 @@ int last_stage_init(void)
 
 	ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
 
-	/* wait for FPGA done */
+	/* wait for FPGA done, then reset FPGA */
 	for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
 		unsigned int ctr = 0;
 

@@ -146,6 +146,12 @@ int last_stage_init(void)
 				break;
 			}
 		}
+
+		pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
+		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
+		udelay(10);
+		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
+				MCFPGA_RESET_N);
 	}
 
 	if (hw_type_cat) {

index f11e26f..b288df8 100644
@@ -28,12 +28,45 @@
 
 #define PIXCLK_640_480_60 25180000
 
+#ifdef CONFIG_SYS_OSD_DH
+#define MAX_OSD_SCREEN 8
+#define OSD_DH_BASE 4
+#else
+#define MAX_OSD_SCREEN 4
+#endif
+
+#ifdef CONFIG_SYS_OSD_DH
+#define OSD_SET_REG(screen, fld, val) \
+	do { \
+		if (screen >= OSD_DH_BASE) \
+			FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
+		else \
+			FPGA_SET_REG(screen, osd0.fld, val); \
+	} while (0)
+#else
+#define OSD_SET_REG(screen, fld, val) \
+		FPGA_SET_REG(screen, osd0.fld, val)
+#endif
+
+#ifdef CONFIG_SYS_OSD_DH
+#define OSD_GET_REG(screen, fld, val) \
+	do {					\
+		if (screen >= OSD_DH_BASE) \
+			FPGA_GET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
+		else \
+			FPGA_GET_REG(screen, osd0.fld, val); \
+	} while (0)
+#else
+#define OSD_GET_REG(screen, fld, val) \
+		FPGA_GET_REG(screen, osd0.fld, val)
+#endif
+
 unsigned int base_width;
 unsigned int base_height;
 size_t bufsize;
 u16 *buf;
 
-unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
+unsigned int osd_screen_mask = 0;
 
 #ifdef CONFIG_SYS_ICS8N3QV01_I2C
 int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;

@@ -47,6 +80,9 @@ int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
 int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
 #endif
 
+#ifdef CONFIG_SYS_DP501_BASE
+int dp501_base[] = CONFIG_SYS_DP501_BASE;
+#endif
 
 #ifdef CONFIG_SYS_MPC92469AC
 static void mpc92469ac_calc_parameters(unsigned int fout,

@@ -216,7 +252,15 @@ static int osd_write_videomem(unsigned screen, unsigned offset,
 	for (k = 0; k < charcount; ++k) {
 		if (offset + k >= bufsize)
 			return -1;
-		FPGA_SET_REG(screen, videomem[offset + k], data[k]);
+#ifdef CONFIG_SYS_OSD_DH
+		if (screen >= OSD_DH_BASE)
+			FPGA_SET_REG(screen - OSD_DH_BASE,
+				     videomem1[offset + k], data[k]);
+		else
+			FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
+#else
+		FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
+#endif
 	}
 
 	return charcount;

@@ -226,7 +270,12 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	unsigned screen;
 
-	for (screen = 0; screen <= max_osd_screen; ++screen) {
+	if (argc < 5) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
 		unsigned x;
 		unsigned y;
 		unsigned charcount;

@@ -236,10 +285,8 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		char *text;
 		int res;
 
-		if (argc < 5) {
-			cmd_usage(cmdtp);
-			return 1;
-		}
+		if (!(osd_screen_mask & (1 << screen)))
+			continue;
 
 		x = simple_strtoul(argv[1], NULL, 16);
 		y = simple_strtoul(argv[2], NULL, 16);

@@ -266,9 +313,16 @@ int osd_probe(unsigned screen)
 	int old_bus = i2c_get_bus_num();
 	bool pixclock_present = false;
 	bool output_driver_present = false;
+#ifdef CONFIG_SYS_DP501_I2C
+#ifdef CONFIG_SYS_DP501_BASE
+	uint8_t dp501_addr = dp501_base[screen];
+#else
+	uint8_t dp501_addr = DP501_I2C_ADDR;
+#endif
+#endif
 
-	FPGA_GET_REG(0, osd.version, &version);
-	FPGA_GET_REG(0, osd.features, &features);
+	OSD_GET_REG(0, version, &version);
+	OSD_GET_REG(0, features, &features);
 
 	base_width = ((features & 0x3f00) >> 8) + 1;
 	base_height = (features & 0x001f) + 1;

@@ -277,9 +331,15 @@ int osd_probe(unsigned screen)
 	if (!buf)
 		return -1;
 
+#ifdef CONFIG_SYS_OSD_DH
+	printf("OSD%d-%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
+	       (screen >= OSD_DH_BASE) ? (screen - OSD_DH_BASE) : screen,
+	       (screen > 3) ? 1 : 0, version/100, version%100, base_width,
+	       base_height);
+#else
 	printf("OSD%d:  Digital-OSD version %01d.%02d, %d" "x%d characters\n",
-		screen, version/100, version%100, base_width, base_height);
-
+	       screen, version/100, version%100, base_width, base_height);
+#endif
 	/* setup pixclock */
 
 #ifdef CONFIG_SYS_MPC92469AC

@@ -330,8 +390,8 @@ int osd_probe(unsigned screen)
 
 #ifdef CONFIG_SYS_DP501_I2C
 	i2c_set_bus_num(dp501_i2c[screen]);
-	if (!i2c_probe(DP501_I2C_ADDR)) {
-		dp501_powerup(DP501_I2C_ADDR);
+	if (!i2c_probe(dp501_addr)) {
+		dp501_powerup(dp501_addr);
 		output_driver_present = true;
 	}
 #endif

@@ -339,14 +399,14 @@ int osd_probe(unsigned screen)
 	if (!output_driver_present)
 		printf("       no output driver found\n");
 
-	FPGA_SET_REG(screen, osd.control, 0x0049);
+	OSD_SET_REG(screen, control, 0x0049);
 
-	FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1));
-	FPGA_SET_REG(screen, osd.x_pos, 0x007f);
-	FPGA_SET_REG(screen, osd.y_pos, 0x005f);
+	OSD_SET_REG(screen, xy_size, ((32 - 1) << 8) | (16 - 1));
+	OSD_SET_REG(screen, x_pos, 0x007f);
+	OSD_SET_REG(screen, y_pos, 0x005f);
 
-	if (screen > max_osd_screen)
-		max_osd_screen = screen;
+	if (pixclock_present && output_driver_present)
+		osd_screen_mask |= 1 << screen;
 
 	i2c_set_bus_num(old_bus);
 

@@ -357,7 +417,12 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	unsigned screen;
 
-	for (screen = 0; screen <= max_osd_screen; ++screen) {
+	if ((argc < 4) || (strlen(argv[3]) % 4)) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
 		unsigned x;
 		unsigned y;
 		unsigned k;

@@ -367,10 +432,8 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		unsigned count = (argc > 4) ?
 			simple_strtoul(argv[4], NULL, 16) : 1;
 
-		if ((argc < 4) || (strlen(argv[3]) % 4)) {
-			cmd_usage(cmdtp);
-			return 1;
-		}
+		if (!(osd_screen_mask & (1 << screen)))
+			continue;
 
 		x = simple_strtoul(argv[1], NULL, 16);
 		y = simple_strtoul(argv[2], NULL, 16);

index 5492718..3cc03cb 100644
@@ -128,6 +128,7 @@ int last_stage_init(void)
 
 	/* Turn on Parade DP501 */
 	pca9698_direction_output(0x20, 10, 1);
+	pca9698_direction_output(0x20, 11, 1);
 
 	ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
 

@@ -174,6 +175,9 @@ int last_stage_init(void)
 
 	ioep_fpga_print_info(0);
 	osd_probe(0);
+#ifdef CONFIG_SYS_OSD_DH
+	osd_probe(4);
+#endif
 
 	if (slaves <= 0)
 		return 0;

@@ -185,6 +189,9 @@ int last_stage_init(void)
 
 		ioep_fpga_print_info(k);
 		osd_probe(k);
+#ifdef CONFIG_SYS_OSD_DH
+		osd_probe(k + 4);
+#endif
 		if (hw_type_cat) {
 			miiphy_register(bb_miiphy_buses[k].name,
 					bb_miiphy_read, bb_miiphy_write);

@@ -196,28 +203,44 @@ int last_stage_init(void)
 }
 
 /*
- * provide access to fpga gpios (for I2C bitbang)
+ * provide access to fpga gpios and controls (for I2C bitbang)
  * (these may look all too simple but make iocon.h much more readable)
  */
 void fpga_gpio_set(unsigned int bus, int pin)
 {
-	FPGA_SET_REG(bus, gpio.set, pin);
+	FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
 }
 
 void fpga_gpio_clear(unsigned int bus, int pin)
 {
-	FPGA_SET_REG(bus, gpio.clear, pin);
+	FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
 }
 
 int fpga_gpio_get(unsigned int bus, int pin)
 {
 	u16 val;
 
-	FPGA_GET_REG(bus, gpio.read, &val);
+	FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, gpio.read, &val);
 
 	return val & pin;
 }
 
+void fpga_control_set(unsigned int bus, int pin)
+{
+	u16 val;
+
+	FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
+	FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin);
+}
+
+void fpga_control_clear(unsigned int bus, int pin)
+{
+	u16 val;
+
+	FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
+	FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin);
+}
+
 void mpc8308_init(void)
 {
 	pca9698_direction_output(0x20, 4, 1);

index db9b402..b000a0e 100644
@@ -473,3 +473,31 @@ U_BOOT_I2C_ADAP_COMPLETE(soft3, soft_i2c_init, soft_i2c_probe,
 			 CONFIG_SYS_I2C_SOFT_SLAVE_4,
 			 3)
 #endif
+#if defined(I2C_SOFT_DECLARATIONS5)
+U_BOOT_I2C_ADAP_COMPLETE(soft4, soft_i2c_init, soft_i2c_probe,
+			 soft_i2c_read, soft_i2c_write, NULL,
+			 CONFIG_SYS_I2C_SOFT_SPEED_5,
+			 CONFIG_SYS_I2C_SOFT_SLAVE_5,
+			 4)
+#endif
+#if defined(I2C_SOFT_DECLARATIONS6)
+U_BOOT_I2C_ADAP_COMPLETE(soft5, soft_i2c_init, soft_i2c_probe,
+			 soft_i2c_read, soft_i2c_write, NULL,
+			 CONFIG_SYS_I2C_SOFT_SPEED_6,
+			 CONFIG_SYS_I2C_SOFT_SLAVE_6,
+			 5)
+#endif
+#if defined(I2C_SOFT_DECLARATIONS7)
+U_BOOT_I2C_ADAP_COMPLETE(soft6, soft_i2c_init, soft_i2c_probe,
+			 soft_i2c_read, soft_i2c_write, NULL,
+			 CONFIG_SYS_I2C_SOFT_SPEED_7,
+			 CONFIG_SYS_I2C_SOFT_SLAVE_7,
+			 6)
+#endif
+#if defined(I2C_SOFT_DECLARATIONS8)
+U_BOOT_I2C_ADAP_COMPLETE(soft7, soft_i2c_init, soft_i2c_probe,
+			 soft_i2c_read, soft_i2c_write, NULL,
+			 CONFIG_SYS_I2C_SOFT_SPEED_8,
+			 CONFIG_SYS_I2C_SOFT_SLAVE_8,
+			 7)
+#endif

91 lines not on this page · raw message

index 69d248f..3b8762d 100644
@@ -157,9 +157,9 @@ struct ihs_fpga {
 	u16 mc_rx_data;		/* 0x0072 */
 	u16 reserved_5[69];	/* 0x0074 */
 	u16 reflection_high;	/* 0x00fe */
-	struct ihs_osd osd;	/* 0x0100 */
+	struct ihs_osd osd0;	/* 0x0100 */
 	u16 reserved_6[889];	/* 0x010e */
-	u16 videomem[31736];	/* 0x0800 */
+	u16 videomem0[2048];	/* 0x0800 */
 };
 #endif
 

@@ -171,7 +171,9 @@ struct ihs_fpga {
 	u16 fpga_features;	/* 0x0006 */
 	u16 reserved_0[1];	/* 0x0008 */
 	u16 top_interrupt;	/* 0x000a */
-	u16 reserved_1[4];	/* 0x000c */
+	u16 reserved_1[2];	/* 0x000c */
+	u16 control;		/* 0x0010 */
+	u16 extended_control;	/* 0x0012 */
 	struct ihs_gpio gpio;	/* 0x0014 */
 	u16 mpc3w_control;	/* 0x001a */
 	u16 reserved_2[2];	/* 0x001c */

@@ -191,9 +193,19 @@ struct ihs_fpga {
 	u16 mc_rx_data;		/* 0x0072 */
 	u16 reserved_5[69];	/* 0x0074 */
 	u16 reflection_high;	/* 0x00fe */
-	struct ihs_osd osd;	/* 0x0100 */
+	struct ihs_osd osd0;	/* 0x0100 */
+#ifdef CONFIG_SYS_OSD_DH
+	u16 reserved_6[57];	/* 0x010e */
+	struct ihs_osd osd1;	/* 0x0180 */
+	u16 reserved_7[9];	/* 0x018e */
+	struct ihs_i2c i2c1;	/* 0x01a0 */
+	u16 reserved_8[1834];	/* 0x01ac */
+	u16 videomem0[2048];	/* 0x1000 */
+	u16 videomem1[2048];	/* 0x2000 */
+#else
 	u16 reserved_6[889];	/* 0x010e */
-	u16 videomem[31736];	/* 0x0800 */
+	u16 videomem0[2048];	/* 0x0800 */
+#endif
 };
 #endif
 

@@ -254,9 +266,9 @@ struct ihs_fpga {
 	u16 mc_rx_cmd_status;	/* 0x0070 */
 	u16 mc_rx_data;		/* 0x0072 */
 	u16 reserved_5[70];	/* 0x0074 */
-	struct ihs_osd osd;	/* 0x0100 */
+	struct ihs_osd osd0;	/* 0x0100 */
 	u16 reserved_6[889];	/* 0x010e */
-	u16 videomem[31736];	/* 0x0800 */
+	u16 videomem0[2048];	/* 0x0800 */
 };
 #endif
 

@@ -275,9 +287,9 @@ struct ihs_fpga {
 	u16 reserved_3[2];	/* 0x006c */
 	struct ihs_i2c i2c1;	/* 0x0070 */
 	u16 reserved_4[194];	/* 0x007c */
-	struct ihs_osd osd;	/* 0x0200 */
+	struct ihs_osd osd0;	/* 0x0200 */
 	u16 reserved_5[761];	/* 0x020e */
-	u16 videomem[31736];	/* 0x0800 */
+	u16 videomem0[2048];	/* 0x0800 */
 };
 #endif
 

new file mode 100644
index 0000000..44569bb
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2015
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach at gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+enum {
+	FAN_CONFIG = 0x03,
+	FAN_TACHLIM_LSB = 0x48,
+	FAN_TACHLIM_MSB = 0x49,
+	FAN_PWM_FREQ = 0x4D,
+};
+
+void init_fan_controller(u8 addr)
+{
+	int val;
+
+	/* set PWM Frequency to 2.5% resolution */
+	i2c_reg_write(addr, FAN_PWM_FREQ, 20);
+
+	/* set Tachometer Limit */
+	i2c_reg_write(addr, FAN_TACHLIM_LSB, 0x10);
+	i2c_reg_write(addr, FAN_TACHLIM_MSB, 0x0a);
+
+	/* enable Tach input */
+	val = i2c_reg_read(addr, FAN_CONFIG) | 0x04;
+	i2c_reg_write(addr, FAN_CONFIG, val);
+}

new file mode 100644
index 0000000..12bc850
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2015
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach at gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _FANCTRL_H_
+#define _FANCTRL_H_
+
+void init_fan_controller(u8 addr);
+
+#endif

index 3cc03cb..880b638 100644
@@ -26,6 +26,7 @@
 #include "../common/osd.h"
 #include "../common/mclink.h"
 #include "../common/phy.h"
+#include "../common/fanctrl.h"
 
 #include <pca953x.h>
 #include <pca9698.h>

@@ -52,6 +53,11 @@ enum {
 unsigned int mclink_fpgacount;
 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
 
+struct {
+	u8 bus;
+	u8 addr;
+} hrcon_fans[] = CONFIG_HRCON_FANS;
+
 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
 {
 	int res;

@@ -199,6 +205,11 @@ int last_stage_init(void)
 		}
 	}
 
+	for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) {
+		i2c_set_bus_num(hrcon_fans[k].bus);
+		init_fan_controller(hrcon_fans[k].addr);
+	}
+
 	return 0;
 }
 

index 8e5d5de..ef5b6c0 100644
@@ -28,6 +28,7 @@
 #include "../common/mclink.h"
 #include "../common/osd.h"
 #include "../common/phy.h"
+#include "../common/fanctrl.h"
 
 #include <pca953x.h>
 #include <pca9698.h>

@@ -51,13 +52,6 @@ enum {
 	GPIO_MDIO = 1 << 15,
 };
 
-enum {
-	FAN_CONFIG = 0x03,
-	FAN_TACHLIM_LSB = 0x48,
-	FAN_TACHLIM_MSB = 0x49,
-	FAN_PWM_FREQ = 0x4D,
-};
-
 unsigned int mclink_fpgacount;
 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
 

@@ -128,22 +122,6 @@ int checkboard(void)
 	return 0;
 }
 
-static void init_fan_controller(u8 addr)
-{
-	int val;
-
-	/* set PWM Frequency to 2.5% resolution */
-	i2c_reg_write(addr, FAN_PWM_FREQ, 20);
-
-	/* set Tachometer Limit */
-	i2c_reg_write(addr, FAN_TACHLIM_LSB, 0x10);
-	i2c_reg_write(addr, FAN_TACHLIM_MSB, 0x0a);
-
-	/* enable Tach input */
-	val = i2c_reg_read(addr, FAN_CONFIG) | 0x04;
-	i2c_reg_write(addr, FAN_CONFIG, val);
-}
-
 int last_stage_init(void)
 {
 	int slaves;

index b000a0e..5ffc974 100644
@@ -501,3 +501,31 @@ U_BOOT_I2C_ADAP_COMPLETE(soft7, soft_i2c_init, soft_i2c_probe,
 			 CONFIG_SYS_I2C_SOFT_SLAVE_8,
 			 7)
 #endif
+#if defined(I2C_SOFT_DECLARATIONS9)
+U_BOOT_I2C_ADAP_COMPLETE(soft8, soft_i2c_init, soft_i2c_probe,
+			 soft_i2c_read, soft_i2c_write, NULL,
+			 CONFIG_SYS_I2C_SOFT_SPEED_9,
+			 CONFIG_SYS_I2C_SOFT_SLAVE_9,
+			 8)
+#endif
+#if defined(I2C_SOFT_DECLARATIONS10)
+U_BOOT_I2C_ADAP_COMPLETE(soft9, soft_i2c_init, soft_i2c_probe,
+			 soft_i2c_read, soft_i2c_write, NULL,
+			 CONFIG_SYS_I2C_SOFT_SPEED_10,
+			 CONFIG_SYS_I2C_SOFT_SLAVE_10,
+			 9)
+#endif
+#if defined(I2C_SOFT_DECLARATIONS11)
+U_BOOT_I2C_ADAP_COMPLETE(soft10, soft_i2c_init, soft_i2c_probe,
+			 soft_i2c_read, soft_i2c_write, NULL,
+			 CONFIG_SYS_I2C_SOFT_SPEED_11,
+			 CONFIG_SYS_I2C_SOFT_SLAVE_11,
+			 10)
+#endif
+#if defined(I2C_SOFT_DECLARATIONS12)
+U_BOOT_I2C_ADAP_COMPLETE(soft11, soft_i2c_init, soft_i2c_probe,
+			 soft_i2c_read, soft_i2c_write, NULL,
+			 CONFIG_SYS_I2C_SOFT_SPEED_12,
+			 CONFIG_SYS_I2C_SOFT_SLAVE_12,
+			 11)
+#endif

87 lines not on this page · raw message

index b288df8..a774bec 100644
@@ -27,6 +27,8 @@
 #define DP501_I2C_ADDR 0x08
 
 #define PIXCLK_640_480_60 25180000
+#define MAX_X_CHARS 53
+#define MAX_Y_CHARS 26
 
 #ifdef CONFIG_SYS_OSD_DH
 #define MAX_OSD_SCREEN 8

@@ -464,6 +466,35 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+int osd_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned screen;
+	unsigned x;
+	unsigned y;
+
+	if (argc < 3) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	x = simple_strtoul(argv[1], NULL, 16);
+	y = simple_strtoul(argv[2], NULL, 16);
+
+	if (!x || (x > 64) || (x > MAX_X_CHARS) ||
+	    !y || (y > 32) || (y > MAX_Y_CHARS)) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
+		OSD_SET_REG(screen, xy_size, ((x - 1) << 8) | (y - 1));
+		OSD_SET_REG(screen, x_pos, 32767 * (640 - 12 * x) / 65535);
+		OSD_SET_REG(screen, y_pos, 32767 * (480 - 18 * y) / 65535);
+	}
+
+	return 0;
+}
+
 U_BOOT_CMD(
 	osdw, 5, 0, osd_write,
 	"write 16-bit hex encoded buffer to osd memory",

@@ -475,3 +506,10 @@ U_BOOT_CMD(
 	"write ASCII buffer to osd memory",
 	"pos_x pos_y color text\n"
 );
+
+U_BOOT_CMD(
+	osdsize, 3, 0, osd_size,
+	"set OSD XY size in characters",
+	"size_x(max. " __stringify(MAX_X_CHARS)
+	") size_y(max. " __stringify(MAX_Y_CHARS) ")\n"
+);

index a774bec..7444bee 100644
@@ -303,6 +303,8 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		res = osd_write_videomem(screen, y * base_width + x, buf, len);
 		if (res < 0)
 			return res;
+
+		OSD_SET_REG(screen, control, 0x0049);
 	}
 
 	return 0;

@@ -401,8 +403,6 @@ int osd_probe(unsigned screen)
 	if (!output_driver_present)
 		printf("       no output driver found\n");
 
-	OSD_SET_REG(screen, control, 0x0049);
-
 	OSD_SET_REG(screen, xy_size, ((32 - 1) << 8) | (16 - 1));
 	OSD_SET_REG(screen, x_pos, 0x007f);
 	OSD_SET_REG(screen, y_pos, 0x005f);

@@ -461,6 +461,8 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			osd_write_videomem(screen, offset, buffer,
 				wp - buffer);
 		}
+
+		OSD_SET_REG(screen, control, 0x0049);
 	}
 
 	return 0;

index 5ffc974..05bf4d4 100644
@@ -448,68 +448,68 @@ static int  soft_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 /*
  * Register soft i2c adapters
  */
-U_BOOT_I2C_ADAP_COMPLETE(soft0, soft_i2c_init, soft_i2c_probe,
+U_BOOT_I2C_ADAP_COMPLETE(soft00, soft_i2c_init, soft_i2c_probe,
 			 soft_i2c_read, soft_i2c_write, NULL,
 			 CONFIG_SYS_I2C_SOFT_SPEED, CONFIG_SYS_I2C_SOFT_SLAVE,
 			 0)
 #if defined(I2C_SOFT_DECLARATIONS2)
-U_BOOT_I2C_ADAP_COMPLETE(soft1, soft_i2c_init, soft_i2c_probe,
+U_BOOT_I2C_ADAP_COMPLETE(soft01, soft_i2c_init, soft_i2c_probe,
 			 soft_i2c_read, soft_i2c_write, NULL,
 			 CONFIG_SYS_I2C_SOFT_SPEED_2,
 			 CONFIG_SYS_I2C_SOFT_SLAVE_2,
 			 1)
 #endif
 #if defined(I2C_SOFT_DECLARATIONS3)
-U_BOOT_I2C_ADAP_COMPLETE(soft2, soft_i2c_init, soft_i2c_probe,
+U_BOOT_I2C_ADAP_COMPLETE(soft02, soft_i2c_init, soft_i2c_probe,
 			 soft_i2c_read, soft_i2c_write, NULL,
 			 CONFIG_SYS_I2C_SOFT_SPEED_3,
 			 CONFIG_SYS_I2C_SOFT_SLAVE_3,
 			 2)
 #endif
 #if defined(I2C_SOFT_DECLARATIONS4)
-U_BOOT_I2C_ADAP_COMPLETE(soft3, soft_i2c_init, soft_i2c_probe,
+U_BOOT_I2C_ADAP_COMPLETE(soft03, soft_i2c_init, soft_i2c_probe,
 			 soft_i2c_read, soft_i2c_write, NULL,
 			 CONFIG_SYS_I2C_SOFT_SPEED_4,
 			 CONFIG_SYS_I2C_SOFT_SLAVE_4,
 			 3)
 #endif
 #if defined(I2C_SOFT_DECLARATIONS5)
-U_BOOT_I2C_ADAP_COMPLETE(soft4, soft_i2c_init, soft_i2c_probe,
+U_BOOT_I2C_ADAP_COMPLETE(soft04, soft_i2c_init, soft_i2c_probe,
 			 soft_i2c_read, soft_i2c_write, NULL,
 			 CONFIG_SYS_I2C_SOFT_SPEED_5,
 			 CONFIG_SYS_I2C_SOFT_SLAVE_5,
 			 4)
 #endif
 #if defined(I2C_SOFT_DECLARATIONS6)
-U_BOOT_I2C_ADAP_COMPLETE(soft5, soft_i2c_init, soft_i2c_probe,
+U_BOOT_I2C_ADAP_COMPLETE(soft05, soft_i2c_init, soft_i2c_probe,
 			 soft_i2c_read, soft_i2c_write, NULL,
 			 CONFIG_SYS_I2C_SOFT_SPEED_6,
 			 CONFIG_SYS_I2C_SOFT_SLAVE_6,
 			 5)
 #endif
 #if defined(I2C_SOFT_DECLARATIONS7)
-U_BOOT_I2C_ADAP_COMPLETE(soft6, soft_i2c_init, soft_i2c_probe,
+U_BOOT_I2C_ADAP_COMPLETE(soft06, soft_i2c_init, soft_i2c_probe,
 			 soft_i2c_read, soft_i2c_write, NULL,
 			 CONFIG_SYS_I2C_SOFT_SPEED_7,
 			 CONFIG_SYS_I2C_SOFT_SLAVE_7,
 			 6)
 #endif
 #if defined(I2C_SOFT_DECLARATIONS8)
-U_BOOT_I2C_ADAP_COMPLETE(soft7, soft_i2c_init, soft_i2c_probe,
+U_BOOT_I2C_ADAP_COMPLETE(soft07, soft_i2c_init, soft_i2c_probe,
 			 soft_i2c_read, soft_i2c_write, NULL,
 			 CONFIG_SYS_I2C_SOFT_SPEED_8,
 			 CONFIG_SYS_I2C_SOFT_SLAVE_8,
 			 7)
 #endif
 #if defined(I2C_SOFT_DECLARATIONS9)
-U_BOOT_I2C_ADAP_COMPLETE(soft8, soft_i2c_init, soft_i2c_probe,
+U_BOOT_I2C_ADAP_COMPLETE(soft08, soft_i2c_init, soft_i2c_probe,
 			 soft_i2c_read, soft_i2c_write, NULL,
 			 CONFIG_SYS_I2C_SOFT_SPEED_9,
 			 CONFIG_SYS_I2C_SOFT_SLAVE_9,
 			 8)
 #endif
 #if defined(I2C_SOFT_DECLARATIONS10)
-U_BOOT_I2C_ADAP_COMPLETE(soft9, soft_i2c_init, soft_i2c_probe,
+U_BOOT_I2C_ADAP_COMPLETE(soft09, soft_i2c_init, soft_i2c_probe,
 			 soft_i2c_read, soft_i2c_write, NULL,
 			 CONFIG_SYS_I2C_SOFT_SPEED_10,
 			 CONFIG_SYS_I2C_SOFT_SLAVE_10,