ARM64: Enable SP805 WDT support for FSL LS2080A
cover ARM64: Enable SP805 WDT support for FSL LS2080A
This patchset adds the support for SP805 WDT on FSL LS2080A and also adds the missing documentation of SP805 WDT device-tree bindings.
Rebased against arm-soc/next/dt
Bhupesh Sharma (2):
Documentation: DT: Add entry for ARM SP805-WDT dts/ls2080a: Update DTSI to add support of SP805 WDT
.../devicetree/bindings/watchdog/sp805-wdt.txt | 33 ++++++++++ arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 64 ++++++++++++++++++++ 2 files changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
Signature · 1 line
1.7.9.5
PATCH 1/2 Documentation: DT: Add entry for ARM SP805-WDT
This patch adds a devicetree binding documentation for ARM's SP805 WatchDog Timer.
--- .../devicetree/bindings/watchdog/sp805-wdt.txt | 33 ++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +33 -0
@@ -0,0 +1,33 @@ +* ARM SP805 Watchdog Timer (WDT) Controller + +SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that +can be used to identify the peripheral type, vendor, and revision. +This value can be used for driver matching. + +Note that the current sp805_wdt driver relies on the 'drivers/amba/bus.c' +framework to invoke the probe function of the sp805_wdt driver using the +unique PRIMECELL identifiers of the sp805 wdt IP. + +As SP805 WDT is a primecell IP, it follows the base bindings specified in +'arm/primecell.txt' + +Required properties: +- compatible : Should be "arm,sp805-wdt", "arm,primecell" +- reg : Base address and size of the watchdog timer registers. +- interrupts : Should specify WDT interrupt number. + +Optional properties: +- clocks : From common clock binding. First clock is phandle to clock for apb + pclk. Additional clocks are optional. +- clock-names : From common clock binding. Shall be "apb_pclk" for first clock. + +Examples: + + cluster1_core0_watchdog: wdt at c000000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; +
Signature · 1 line
1.7.9.5
PATCH 1/2 Documentation: DT: Add entry for ARM SP805-WDT
Quoted 15 lines · Bhupesh Sharma
This patch adds a devicetree binding documentation for ARM's SP805 WatchDog Timer.
Signed-off-by Bhupesh Sharma <[email protected]>--- .../devicetree/bindings/watchdog/sp805-wdt.txt | 33 ++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/sp805-wdt.txtDocumentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +0
-0
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt line 9
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Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +9
-0@@ -0,0 +1,33 @@ +* ARM SP805 Watchdog Timer (WDT) Controller + +SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that +can be used to identify the peripheral type, vendor, and revision. +This value can be used for driver matching. + +Note that the current sp805_wdt driver relies on the 'drivers/amba/bus.c' +framework to invoke the probe function of the sp805_wdt driver using the +unique PRIMECELL identifiers of the sp805 wdt IP.
This paragraph can go. We shouldn't describe kernel internals.
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt line 22
Quoted 12 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +12
-0+As SP805 WDT is a primecell IP, it follows the base bindings specified in +'arm/primecell.txt' + +Required properties: +- compatible : Should be "arm,sp805-wdt", "arm,primecell" +- reg : Base address and size of the watchdog timer registers. +- interrupts : Should specify WDT interrupt number. + +Optional properties: +- clocks : From common clock binding. First clock is phandle to clock for apb + pclk. Additional clocks are optional. +- clock-names : From common clock binding. Shall be "apb_pclk" for first clock.
The hardware has "WDOGCLK", which is what the driver appears to expect first implicitly.
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt line 29
Quoted 6 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +6
-0+Examples: + + cluster1_core0_watchdog: wdt at c000000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */
I don't see how you can use PPIs here. This is not banked per CPU.
Mark.
Quoted 8 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +4
-0+ clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; +Signature · 1 line
1.7.9.5
Rob Herring
maintainerPATCH 1/2 Documentation: DT: Add entry for ARM SP805-WDT
Quoted 28 lines · Mark Rutland
Quoted 15 lines · Bhupesh Sharma
This patch adds a devicetree binding documentation for ARM's SP805 WatchDog Timer.
Signed-off-by Bhupesh Sharma <[email protected]>--- .../devicetree/bindings/watchdog/sp805-wdt.txt | 33 ++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/sp805-wdt.txtDocumentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +0
-0Documentation/devicetree/bindings/watchdog/sp805-wdt.txt line 9
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Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +9
-0@@ -0,0 +1,33 @@ +* ARM SP805 Watchdog Timer (WDT) Controller + +SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that +can be used to identify the peripheral type, vendor, and revision. +This value can be used for driver matching. + +Note that the current sp805_wdt driver relies on the 'drivers/amba/bus.c' +framework to invoke the probe function of the sp805_wdt driver using the +unique PRIMECELL identifiers of the sp805 wdt IP.This paragraph can go. We shouldn't describe kernel internals.
Quoted 15 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt line 22
Quoted 12 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +12
-0+As SP805 WDT is a primecell IP, it follows the base bindings specified in +'arm/primecell.txt' + +Required properties: +- compatible : Should be "arm,sp805-wdt", "arm,primecell" +- reg : Base address and size of the watchdog timer registers. +- interrupts : Should specify WDT interrupt number. + +Optional properties: +- clocks : From common clock binding. First clock is phandle to clock for apb + pclk. Additional clocks are optional. +- clock-names : From common clock binding. Shall be "apb_pclk" for first clock.The hardware has "WDOGCLK", which is what the driver appears to expect first implicitly.
The h/w has 2 clocks, PCLK and WDOGCLK, so both should be described and neither should be optional.
Rob
PATCH 1/2 Documentation: DT: Add entry for ARM SP805-WDT
Hi Rob,
Thanks for the review.
Quoted 23 lines · Rob Herring
Quoted 22 lines · Mark Rutland
Quoted 21 lines · Bhupesh Sharma
This patch adds a devicetree binding documentation for ARM's SP805 WatchDog Timer.
Signed-off-by Bhupesh Sharma <[email protected]>--- .../devicetree/bindings/watchdog/sp805-wdt.txt | 33 ++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/sp805-wdt.txtDocumentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +6
-0@@ -0,0 +1,33 @@ +* ARM SP805 Watchdog Timer (WDT) Controller + +SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that +can be used to identify the peripheral type, vendor, and revision. +This value can be used for driver matching. +
[snip..]
Quoted 16 lines
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Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +7
-0+As SP805 WDT is a primecell IP, it follows the base bindings specified in +'arm/primecell.txt' + +Required properties: +- compatible : Should be "arm,sp805-wdt", "arm,primecell" +- reg : Base address and size of the watchdog timer registers. +- interrupts : Should specify WDT interrupt number.Quoted 8 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt line 22
Quoted 5 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +5
-0+ +Optional properties: +- clocks : From common clock binding. First clock is phandle to clock for apb + pclk. Additional clocks are optional. +- clock-names : From common clock binding. Shall be "apb_pclk" for first clock.The hardware has "WDOGCLK", which is what the driver appears to expect first implicitly.
Quoted 2 lines
The h/w has 2 clocks, PCLK and WDOGCLK, so both should be described and neither should be optional.
As per the SP805 WDT TRM I have with me (see [1], Figure 1-1), this h/w has only only input
clock WDOGCLK.
[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0270b/DDI0270.pdf
Regards,
Bhupesh
Quoted 2 lines
Rob
Rob Herring
maintainerPATCH 1/2 Documentation: DT: Add entry for ARM SP805-WDT
Quoted 47 lines · Bhupesh SHARMA
Hi Rob,
Thanks for the review.
Quoted 23 lines · Rob Herring
Quoted 22 lines · Mark Rutland
Quoted 21 lines · Bhupesh Sharma
This patch adds a devicetree binding documentation for ARM's SP805 WatchDog Timer.
Signed-off-by Bhupesh Sharma <[email protected]>--- .../devicetree/bindings/watchdog/sp805-wdt.txt | 33 ++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/sp805-wdt.txtDocumentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +6
-0@@ -0,0 +1,33 @@ +* ARM SP805 Watchdog Timer (WDT) Controller + +SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that +can be used to identify the peripheral type, vendor, and revision. +This value can be used for driver matching. +[snip..]
Quoted 16 lines
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Documentation/devicetree/bindings/watchdog/sp805-wdt.txt line 22
Quoted 12 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +12
-0+As SP805 WDT is a primecell IP, it follows the base bindings specified in +'arm/primecell.txt' + +Required properties: +- compatible : Should be "arm,sp805-wdt", "arm,primecell" +- reg : Base address and size of the watchdog timer registers. +- interrupts : Should specify WDT interrupt number. + +Optional properties: +- clocks : From common clock binding. First clock is phandle to clock for apb + pclk. Additional clocks are optional. +- clock-names : From common clock binding. Shall be "apb_pclk" for first clock.The hardware has "WDOGCLK", which is what the driver appears to expect first implicitly.
Quoted 8 lines
Quoted 2 lines
The h/w has 2 clocks, PCLK and WDOGCLK, so both should be described and neither should be optional.
As per the SP805 WDT TRM I have with me (see [1], Figure 1-1), this h/w has only only input
clock WDOGCLK.[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0270b/DDI0270.pdf
Look closer, PCLK is in the AMBA bus signals. The version online has some timing diagrams also which I didn't find here.
Rob
PATCH 1/2 Documentation: DT: Add entry for ARM SP805-WDT
Hi Rob,
Quoted 51 lines · Rob Herring
Quoted 50 lines · Bhupesh SHARMA
Hi Rob,
Thanks for the review.
Quoted 23 lines · Rob Herring
Quoted 22 lines · Mark Rutland
Quoted 21 lines · Bhupesh Sharma
This patch adds a devicetree binding documentation for ARM's SP805 WatchDog Timer.
Signed-off-by Bhupesh Sharma <[email protected]>--- .../devicetree/bindings/watchdog/sp805-wdt.txt | 33 ++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/sp805-wdt.txtDocumentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +6
-0@@ -0,0 +1,33 @@ +* ARM SP805 Watchdog Timer (WDT) Controller + +SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that +can be used to identify the peripheral type, vendor, and revision. +This value can be used for driver matching. +[snip..]
Quoted 18 lines
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Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +7
-0+As SP805 WDT is a primecell IP, it follows the base bindings specified in +'arm/primecell.txt' + +Required properties: +- compatible : Should be "arm,sp805-wdt", "arm,primecell" +- reg : Base address and size of the watchdog timer registers. +- interrupts : Should specify WDT interrupt number.Quoted 8 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt line 22
Quoted 5 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +5
-0+ +Optional properties: +- clocks : From common clock binding. First clock is phandle to clock for apb + pclk. Additional clocks are optional. +- clock-names : From common clock binding. Shall be "apb_pclk" for first clock.The hardware has "WDOGCLK", which is what the driver appears to expect first implicitly.
The h/w has 2 clocks, PCLK and WDOGCLK, so both should be described and neither should be optional.
Quoted 8 lines
Quoted 5 lines
As per the SP805 WDT TRM I have with me (see [1], Figure 1-1), this h/w has only only input
clock WDOGCLK.[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0270b/DDI0270.pdf
Look closer, PCLK is in the AMBA bus signals. The version online has some timing diagrams also which I didn't find here.
Correct. So will add both PCLK and WDOGCLK to the compatible node in the v2 of this patch.
Regards,
Bhupesh
PATCH 1/2 Documentation: DT: Add entry for ARM SP805-WDT
In reply to Mark RutlandHi Mark,
Thanks for the review.
Quoted 19 lines · Mark Rutland
Quoted 18 lines · Bhupesh Sharma
This patch adds a devicetree binding documentation for ARM's SP805 WatchDog Timer.
Signed-off-by Bhupesh Sharma <[email protected]>--- .../devicetree/bindings/watchdog/sp805-wdt.txt | 33 ++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/sp805-wdt.txtDocumentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +3
-0@@ -0,0 +1,33 @@ +* ARM SP805 Watchdog Timer (WDT) Controller + +SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that
Quoted 8 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt line 9
Quoted 6 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +6
-0+can be used to identify the peripheral type, vendor, and revision. +This value can be used for driver matching. + +Note that the current sp805_wdt driver relies on the 'drivers/amba/bus.c' +framework to invoke the probe function of the sp805_wdt driver using the +unique PRIMECELL identifiers of the sp805 wdt IP.This paragraph can go. We shouldn't describe kernel internals.
Ok.
Quoted 7 lines
Quoted 7 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +7
-0+As SP805 WDT is a primecell IP, it follows the base bindings specified in +'arm/primecell.txt' + +Required properties: +- compatible : Should be "arm,sp805-wdt", "arm,primecell" +- reg : Base address and size of the watchdog timer registers. +- interrupts : Should specify WDT interrupt number.
Quoted 8 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt line 22
Quoted 5 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +5
-0+ +Optional properties: +- clocks : From common clock binding. First clock is phandle to clock for apb + pclk. Additional clocks are optional. +- clock-names : From common clock binding. Shall be "apb_pclk" for first clock.The hardware has "WDOGCLK", which is what the driver appears to expect first implicitly.
Ok.
Quoted 8 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt line 29
Quoted 6 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +6
-0+Examples: + + cluster1_core0_watchdog: wdt at c000000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */I don't see how you can use PPIs here. This is not banked per CPU.
I have raised this concern to my hardware team. This might be an issue with the documentation.
I will change it in v2 as per their comments.
Regards,
Bhupesh
Quoted 10 lines
Mark.
Quoted 8 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +4
-1+ clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + --1.7.9.5
PATCH 1/2 Documentation: DT: Add entry for ARM SP805-WDT
Hi Mark,
Quoted 62 lines · Bhupesh SHARMA
Hi Mark,
Thanks for the review.
Quoted 19 lines · Mark Rutland
Quoted 18 lines · Bhupesh Sharma
This patch adds a devicetree binding documentation for ARM's SP805 WatchDog Timer.
Signed-off-by Bhupesh Sharma <[email protected]>--- .../devicetree/bindings/watchdog/sp805-wdt.txt | 33 ++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/sp805-wdt.txtDocumentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +3
-0@@ -0,0 +1,33 @@ +* ARM SP805 Watchdog Timer (WDT) Controller + +SP805 WDT is a ARM Primecell Peripheral and has a standard-id register thatQuoted 8 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt line 9
Quoted 6 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +6
-0+can be used to identify the peripheral type, vendor, and revision. +This value can be used for driver matching. + +Note that the current sp805_wdt driver relies on the 'drivers/amba/bus.c' +framework to invoke the probe function of the sp805_wdt driver using the +unique PRIMECELL identifiers of the sp805 wdt IP.This paragraph can go. We shouldn't describe kernel internals.
Ok.
Quoted 7 lines
Quoted 7 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +7
-0+As SP805 WDT is a primecell IP, it follows the base bindings specified in +'arm/primecell.txt' + +Required properties: +- compatible : Should be "arm,sp805-wdt", "arm,primecell" +- reg : Base address and size of the watchdog timer registers. +- interrupts : Should specify WDT interrupt number.Quoted 8 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt line 22
Quoted 5 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +5
-0+ +Optional properties: +- clocks : From common clock binding. First clock is phandle to clock for apb + pclk. Additional clocks are optional. +- clock-names : From common clock binding. Shall be "apb_pclk" for first clock.The hardware has "WDOGCLK", which is what the driver appears to expect first implicitly.
Ok.
Quoted 8 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt line 29
Quoted 6 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +6
-0+Examples: + + cluster1_core0_watchdog: wdt at c000000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */I don't see how you can use PPIs here. This is not banked per CPU.
Quoted 3 lines
I have raised this concern to my hardware team. This might be an issue with the documentation.
I will change it in v2 as per their comments.
I just checked back with the hardware team. They confirm that the WDOGINT interrupts lines
from the eight instances of the SP805 WDT are infact connected to PPI input of the GICv3 controller.
Also this SP805 WDT IP supports 2 interrupt lines:
- WDOGINT
- WDOGRES
but the current sp805_wdt.c driver doesn't handle the WDOGINT interrupt (irrespective of whether
it is a SPI or PPI). I could not trace a request_irq being called for the same in the driver.
So, I would suggest the following:
I can spin a patch for sp805_wdt.c to add support to handle WDOGINT interrupt when the WDT counter expires
as currently the cadence_wdt driver does (see [1] and [2] as reference):
[1] http://lxr.free-electrons.com/source/drivers/watchdog/cadence_wdt.c#L343
[2] http://lxr.free-electrons.com/source/drivers/watchdog/cadence_wdt.c#L254
Please suggest if this approach seems fine to you.
Regards,
Bhupesh
Quoted 14 lines
Regards,
BhupeshQuoted 10 lines
Mark.
Quoted 8 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +4
-1+ clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + --1.7.9.5
PATCH 1/2 Documentation: DT: Add entry for ARM SP805-WDT
Hi Mark,
Ping..
Quoted 112 lines · Bhupesh SHARMA
Hi Mark,
Quoted 62 lines · Bhupesh SHARMA
Hi Mark,
Thanks for the review.
Quoted 19 lines · Mark Rutland
Quoted 18 lines · Bhupesh Sharma
This patch adds a devicetree binding documentation for ARM's SP805 WatchDog Timer.
Signed-off-by Bhupesh Sharma <[email protected]>--- .../devicetree/bindings/watchdog/sp805-wdt.txt | 33 ++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/sp805-wdt.txtDocumentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +3
-0@@ -0,0 +1,33 @@ +* ARM SP805 Watchdog Timer (WDT) Controller + +SP805 WDT is a ARM Primecell Peripheral and has a standard-id register thatQuoted 8 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt line 9
Quoted 6 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +6
-0+can be used to identify the peripheral type, vendor, and revision. +This value can be used for driver matching. + +Note that the current sp805_wdt driver relies on the 'drivers/amba/bus.c' +framework to invoke the probe function of the sp805_wdt driver using the +unique PRIMECELL identifiers of the sp805 wdt IP.This paragraph can go. We shouldn't describe kernel internals.
Ok.
Quoted 7 lines
Quoted 7 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +7
-0+As SP805 WDT is a primecell IP, it follows the base bindings specified in +'arm/primecell.txt' + +Required properties: +- compatible : Should be "arm,sp805-wdt", "arm,primecell" +- reg : Base address and size of the watchdog timer registers. +- interrupts : Should specify WDT interrupt number.Quoted 8 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt line 22
Quoted 5 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +5
-0+ +Optional properties: +- clocks : From common clock binding. First clock is phandle to clock for apb + pclk. Additional clocks are optional. +- clock-names : From common clock binding. Shall be "apb_pclk" for first clock.The hardware has "WDOGCLK", which is what the driver appears to expect first implicitly.
Ok.
Quoted 8 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt line 29
Quoted 6 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +6
-0+Examples: + + cluster1_core0_watchdog: wdt at c000000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */I don't see how you can use PPIs here. This is not banked per CPU.
Quoted 3 lines
I have raised this concern to my hardware team. This might be an issue with the documentation.
I will change it in v2 as per their comments.I just checked back with the hardware team. They confirm that the WDOGINT interrupts lines
from the eight instances of the SP805 WDT are infact connected to PPI input of the GICv3 controller.Also this SP805 WDT IP supports 2 interrupt lines:
- WDOGINT
- WDOGRESbut the current
sp805_wdt.cdriver doesn't handle the WDOGINT interrupt (irrespective of whether
it is a SPI or PPI). I could not trace arequest_irqbeing called for the same in the driver.So, I would suggest the following:
I can spin a patch for
sp805_wdt.cto add support to handle WDOGINT interrupt when the WDT counter expires
as currently thecadence_wdtdriver does (see [1] and [2] as reference):[1] http://lxr.free-electrons.com/source/drivers/watchdog/cadence_wdt.c#L343
[2] http://lxr.free-electrons.com/source/drivers/watchdog/cadence_wdt.c#L254Please suggest if this approach seems fine to you.
Regards,
BhupeshQuoted 14 lines
Regards,
BhupeshQuoted 10 lines
Mark.
Quoted 8 lines
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt new file +4
-1+ clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + --1.7.9.5
PATCH 2/2 dts/ls2080a: Update DTSI to add support of SP805 WDT
In reply to Bhupesh SharmaThis patch updates the LS2080a DTSI (DTS Include) file to add support for eight SP805 Watchdog units which can be used to reset the eight Cortex-A57 cores available on LS2080A.
--- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 64 ++++++++++++++++++++++++ 1 file changed, 64 insertions(+)
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +64 -0
@@ -193,6 +193,70 @@ interrupts = <0 32 0x4>; /* Level high type */ }; + cluster1_core0_watchdog: wdt at c000000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster1_core1_watchdog: wdt at c010000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc010000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster2_core0_watchdog: wdt at c100000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc100000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster2_core1_watchdog: wdt at c110000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc110000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster3_core0_watchdog: wdt at c200000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc200000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster3_core1_watchdog: wdt at c210000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc210000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster4_core0_watchdog: wdt at c300000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc300000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + + cluster4_core1_watchdog: wdt at c310000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc310000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + }; + fsl_mc: fsl-mc at 80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
Signature · 1 line
1.7.9.5
PATCH 2/2 dts/ls2080a: Update DTSI to add support of SP805 WDT
Quoted 22 lines · Bhupesh Sharma
This patch updates the LS2080a DTSI (DTS Include) file to add support for eight SP805 Watchdog units which can be used to reset the eight Cortex-A57 cores available on LS2080A.
Signed-off-by Bhupesh Sharma <[email protected]>--- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 64 ++++++++++++++++++++++++ 1 file changed, 64 insertions(+)arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +5
-0@@ -193,6 +193,70 @@ interrupts = <0 32 0x4>; /* Level high type */ }; + cluster1_core0_watchdog: wdt at c000000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>;
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 210
Quoted 10 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +10
-0+ clock-names = "apb_pclk"; + }; + + cluster1_core1_watchdog: wdt at c010000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc010000 0x0 0x1000>; + interrupts = <1 12 0x8>; /* PPI, Level low type */ + clocks = <&clockgen 4 3>; + clock-names = "apb_pclk"; + };
How does this pseudo-banking work?
For one thing as far as I can see, the SP805 driver can't handle PPIs in mainline.
Additionally, the kernel has no idea which CPU each of these is associated with, and we effectively need to deal with shared PPIs in order to use this appropriately in the kernel (if each WDT's interrupt is wired to a particular core).
Thanks,
Mark.