Bring up rk3036 uboot
Subsystems (7)
v6 cover Bring up rk3036 uboot
This series patch bring up rk3036 uboot, since rk3036 only 4K size SRAM for SPL, so in SPL stage only support timer, uart, sdram driver, and back to bootrom when finish ddr initial, and boot up second stage from bootrom.You can boot to command line(mmc info etc) for now use this patchset.
Jeffy Chen (2):
rockchip: Add max spl size & spl header configs
rockchip: Add support for rk's second level loader
Lin Huang (21):
rockchip: add timer driver
rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfig
rockchip: rename board-spl.c to rk3288-board-spl.c
rockchip: add config decide whether to build common.c
dm: core: Add SPL Kconfig for REGMAP and SYSCON
rockchip: serial driver support rk3036
rockchip: Bring in RK3036 device tree file includes and bindings
rockchip: rk3036: Add clock driver
rockchip: rk3036: Add header files for GRF
rockchip: rk3036: Add Soc reset driver
rockchip: rk3036: Add a simple syscon driver
rockchip: rk3036: Add pinctrl driver
mmc: dw_mmc: move data transfer as a separate function
mmc: dw_mmc: support fifo mode in dwc mmc driver
rockchip: mmc: use non-removable property to disginguish emmc and
sdcard register
rockchip: mmc: get the fifo mode and fifo depth property from dts
rockchip: add early uart driver
rockchip: add rk3036 sdram driver
rockchip: rk3036: Add core Soc start-up code
rockchip: Add basic support for evb-rk3036 board
rockchip: doc: show packet rk3036 uboot image
arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3036-sdk.dts | 46 ++ arch/arm/dts/rk3036.dtsi | 428 ++++++++++++ arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 168 +++++ arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 ++++++++++++++ arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 ++++++++++ arch/arm/include/asm/arch-rockchip/timer.h | 22 + arch/arm/include/asm/arch-rockchip/uart.h | 44 ++ arch/arm/mach-rockchip/Kconfig | 28 +- arch/arm/mach-rockchip/Makefile | 10 +- arch/arm/mach-rockchip/board-spl.c | 294 --------- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 55 ++ arch/arm/mach-rockchip/rk3036/Kconfig | 23 + arch/arm/mach-rockchip/rk3036/Makefile | 13 + arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++ arch/arm/mach-rockchip/rk3036/save_boot_param.S | 32 + arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 764 ++++++++++++++++++++++ arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 + arch/arm/mach-rockchip/rk3288-board-spl.c | 277 ++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 9 + arch/arm/mach-rockchip/rk_early_print.c | 63 ++ arch/arm/mach-rockchip/rk_timer.c | 48 ++ board/evb_rk3036/evb_rk3036/Kconfig | 15 + board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 + board/evb_rk3036/evb_rk3036/evb_rk3036.c | 49 ++ configs/chromebook_jerry_defconfig | 2 + configs/evb-rk3036_defconfig | 26 + configs/firefly-rk3288_defconfig | 2 + configs/sandbox_defconfig | 2 + doc/README.rockchip | 11 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 414 ++++++++++++ drivers/core/Kconfig | 19 + drivers/core/Makefile | 4 +- drivers/mmc/dw_mmc.c | 140 ++-- drivers/mmc/rockchip_dw_mmc.c | 27 +- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++ drivers/serial/serial_rockchip.c | 1 + include/configs/evb_rk3036.h | 12 + include/configs/rk3036_common.h | 103 +++ include/configs/rk3288_common.h | 8 +- include/dt-bindings/clock/rk3036-cru.h | 186 ++++++ include/dwmmc.h | 5 + tools/Makefile | 6 + tools/rkcommon.c | 26 +- tools/rkcommon.h | 4 +- tools/rkimage.c | 2 +- tools/rksd.c | 6 +- tools/rkspi.c | 6 +- 53 files changed, 4222 insertions(+), 376 deletions(-) create mode 100644 arch/arm/dts/rk3036-sdk.dts create mode 100644 arch/arm/dts/rk3036.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/timer.h create mode 100644 arch/arm/include/asm/arch-rockchip/uart.h delete mode 100644 arch/arm/mach-rockchip/board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3036-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3036/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3036/Makefile create mode 100644 arch/arm/mach-rockchip/rk3036/reset_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3036/save_boot_param.S create mode 100644 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3036/syscon_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3288-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk_early_print.c create mode 100644 arch/arm/mach-rockchip/rk_timer.c create mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644 board/evb_rk3036/evb_rk3036/evb_rk3036.c create mode 100644 configs/evb-rk3036_defconfig create mode 100644 drivers/clk/clk_rk3036.c create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c create mode 100644 include/configs/evb_rk3036.h create mode 100644 include/configs/rk3036_common.h create mode 100644 include/dt-bindings/clock/rk3036-cru.h
Signature · 1 line
1.9.1
PATCH v6 1/23 rockchip: add timer driver
some rockchip soc will not include lib/timer.c in SPL stage, so implement timer driver for some soc can use us delay function in SPL.
---
Changes in v1: None
Changes in v2:
- add udelay function
Changes in v3:
- fix some coding style
Changes in v4: None
Changes in v5: None
Changes in v6:
- Adviced by Ben Chan:
- use uint64_t as usec_to_tick() return type
arch/arm/include/asm/arch-rockchip/timer.h | 22 ++++++++++++++ arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/board-spl.c | 21 ++----------- arch/arm/mach-rockchip/rk_timer.c | 48 ++++++++++++++++++++++++++++++ include/configs/rk3288_common.h | 3 +- 5 files changed, 75 insertions(+), 20 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/timer.h create mode 100644 arch/arm/mach-rockchip/rk_timer.c
arch/arm/include/asm/arch-rockchip/timer.h new file +22 -0
@@ -0,0 +1,22 @@ +/* +* (C) Copyright 2015 Rockchip Electronics Co., Ltd +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __ASM_ARCH_TIMER_H +#define __ASM_ARCH_TIMER_H + +struct rk_timer { +unsigned int timer_load_count0; +unsigned int timer_load_count1; +unsigned int timer_curr_value0; +unsigned int timer_curr_value1; +unsigned int timer_ctrl_reg; +unsigned int timer_int_status; +}; + +void rockchip_timer_init (void ); +void rockchip_udelay (unsigned int usec); + +#endif
arch/arm/mach-rockchip/Makefile +1 -0
@@ -10,4 +10,5 @@ else obj-y += board.o endif obj-y += common.o +obj-y += rk_timer.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
arch/arm/mach-rockchip/board-spl.c +2 -19
@@ -18,6 +18,7 @@#include <asm/arch/hardware.h> #include <asm/arch/periph.h> #include <asm/arch/sdram.h> +#include <asm/arch/timer.h> #include <dm/pinctrl.h> #include <dm/root.h> #include <dm/test.h>
@@ -110,24 +111,6 @@ static void configure_l2ctlr(void)write_l2ctlr (l2ctlr); } -struct rk3288_timer { -u32 timer_load_count0; -u32 timer_load_count1; -u32 timer_curr_value0; -u32 timer_curr_value1; -u32 timer_ctrl_reg; -u32 timer_int_status; -}; - -void init_timer (void ) -{ -struct rk3288_timer *const timer7_ptr = (void *)TIMER7_BASE ; - -writel (0xffffffff , &timer7_ptr->timer_load_count0); -writel (0xffffffff , &timer7_ptr->timer_load_count1); -writel (1 , &timer7_ptr->timer_ctrl_reg); -} -static int configure_emmc (struct udevice *pinctrl) {struct gpio_desc desc;
@@ -197,7 +180,7 @@ void board_init_f(ulong dummy)hang (); } -init_timer (); +rockchip_timer_init ();configure_l2ctlr (); ret =uclass_get_device (UCLASS_CLK ,0 , &dev);
arch/arm/mach-rockchip/rk_timer.c new file +48 -0
48 lines not on this page · raw message
include/configs/rk3288_common.h +2 -1
@@ -23,7 +23,8 @@#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) -#define CONFIG_SYS_TIMER_COUNTER (TIMER7_BASE + 8) +#define CONFIG_SYS_TIMER_BASE 0xff810020/* TIMER7 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)#define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LIBCOMMON_SUPPORT
Signature · 1 line
1.9.1
PATCH v6 1/23 rockchip: add timer driver
Quoted 17 lines · Lin Huang
some rockchip soc will not include
lib/timer.cin SPL stage, so implement timer driver for some soc can use us delay function in SPL.Signed-off-by Lin Huang <[email protected]>Acked-by Simon Glass <[email protected]>---
Changes in v1: None
Changes in v2:
- add udelay function
Changes in v3:
- fix some coding style
Changes in v4: None
Changes in v5: None
Changes in v6:
- Adviced by Ben Chan:
- useuint64_tasusec_to_tick()return type
Quoted 8 lines
arch/arm/include/asm/arch-rockchip/timer.h | 22 ++++++++++++++ arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/board-spl.c | 21 ++----------- arch/arm/mach-rockchip/rk_timer.c | 48 ++++++++++++++++++++++++++++++ include/configs/rk3288_common.h | 3 +- 5 files changed, 75 insertions(+), 20 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/timer.h create mode 100644 arch/arm/mach-rockchip/rk_timer.c
Applied to u-boot-rockchip, thanks!
PATCH v6 2/23 rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfig
In reply to Lin Huangsince different rockchip SOC have different size of SRAM, So the size SYS_MALLOC_F_LEN may different, so move this config to rk3288 own Kconfig
---
Changes in v1: None
Changes in v2: None
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
arch/arm/mach-rockchip/Kconfig | 3 --- arch/arm/mach-rockchip/rk3288/Kconfig | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-)
arch/arm/mach-rockchip/Kconfig +0 -3
@@ -12,9 +12,6 @@ config ROCKCHIP_RK3288 config SYS_MALLOC_F default y -config SYS_MALLOC_F_LEN - default 0x800 - config SPL_DM default y
arch/arm/mach-rockchip/rk3288/Kconfig +3 -0
@@ -19,6 +19,9 @@ config TARGET_CHROMEBOOK_JERRY config SYS_SOC default "rockchip" +config SYS_MALLOC_F_LEN + default 0x0800 + source "board/google/chromebook_jerry/Kconfig" source "board/firefly/firefly-rk3288/Kconfig"
Signature · 1 line
1.9.1
PATCH v6 2/23 rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfig
Quoted 14 lines · Lin Huang
since different rockchip SOC have different size of SRAM, So the size
SYS_MALLOC_F_LENmay different, so move this config to rk3288 ownKconfigSigned-off-by Lin Huang <[email protected]>Acked-by Simon Glass <[email protected]>---
Changes in v1: None
Changes in v2: None
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
Quoted 3 lines
arch/arm/mach-rockchip/Kconfig | 3 --- arch/arm/mach-rockchip/rk3288/Kconfig | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-)
Applied to u-boot-rockchip, thanks!
PATCH v6 3/23 rockchip: rename board-spl.c to rk3288-board-spl.c
In reply to Lin Huangsince different rockchip soc need different spl file, so rename board-spl.c.
---
Changes in v1: None
Changes in v2: None
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
arch/arm/mach-rockchip/Makefile | 2 +- arch/arm/mach-rockchip/board-spl.c | 277 ------------------------------ arch/arm/mach-rockchip/rk3288-board-spl.c | 277 ++++++++++++++++++++++++++++++ 3 files changed, 278 insertions(+), 278 deletions(-) delete mode 100644 arch/arm/mach-rockchip/board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3288-board-spl.c
arch/arm/mach-rockchip/Makefile +1 -1
@@ -5,7 +5,7 @@ # ifdef CONFIG_SPL_BUILD -obj-y += board-spl.o +obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o else obj-y += board.o endif
arch/arm/mach-rockchip/board-spl.c deleted +0 -277
277 lines not on this page · raw message
arch/arm/mach-rockchip/rk3288-board-spl.c new file +277 -0
277 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH v6 3/23 rockchip: rename board-spl.c to rk3288-board-spl.c
Quoted 13 lines · Lin Huang
since different rockchip soc need different spl file, so rename
board-spl.c.Signed-off-by Lin Huang <[email protected]>Acked-by Simon Glass <[email protected]>---
Changes in v1: None
Changes in v2: None
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
Quoted 6 lines
arch/arm/mach-rockchip/Makefile | 2 +- arch/arm/mach-rockchip/board-spl.c | 277 ------------------------------ arch/arm/mach-rockchip/rk3288-board-spl.c | 277 ++++++++++++++++++++++++++++++ 3 files changed, 278 insertions(+), 278 deletions(-) delete mode 100644 arch/arm/mach-rockchip/board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3288-board-spl.c
Applied to u-boot-rockchip, thanks!
PATCH v6 4/23 rockchip: add config decide whether to build common.c
In reply to Lin Huangsome rockchips soc will not use uclass in SPL stage, so define config to decide whether to build common.c
---
Changes in v1: None
Changes in v2: None
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
arch/arm/mach-rockchip/Makefile | 2 +- include/configs/rk3288_common.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-)
arch/arm/mach-rockchip/Makefile +1 -1
@@ -9,6 +9,6 @@ obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o else obj-y += board.o endif -obj-y += common.o obj-y += rk_timer.o +obj-$(CONFIG_$(SPL_)ROCKCHIP_COMMON) += common.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
include/configs/rk3288_common.h +3 -0
@@ -44,6 +44,9 @@#define CONFIG_SPL_STACK 0xff718000#define CONFIG_SPL_TEXT_BASE 0xff704004 +#define CONFIG_ROCKCHIP_COMMON +#define CONFIG_SPL_ROCKCHIP_COMMON +/* MMC/SD IP block */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC
Signature · 1 line
1.9.1
PATCH v6 4/23 rockchip: add config decide whether to build common.c
Quoted 13 lines · Lin Huang
some rockchips soc will not use uclass in SPL stage, so define config to decide whether to build
common.cSigned-off-by Lin Huang <[email protected]>Acked-by Simon Glass <[email protected]>---
Changes in v1: None
Changes in v2: None
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
Quoted 3 lines
arch/arm/mach-rockchip/Makefile | 2 +- include/configs/rk3288_common.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-)
Applied to u-boot-rockchip, thanks!
PATCH v6 5/23 dm: core: Add SPL Kconfig for REGMAP and SYSCON
In reply to Lin HuangAdd SPL Kconfig for REGMAP and SYSCON, so REGMAP and SYSCON can remove from SPL stage.
---
Changes in v1: None
Changes in v2: None
Changes in v3:
- fix compile error
Changes in v4: None
Changes in v5: None
Changes in v6: None
configs/chromebook_jerry_defconfig | 2 ++ configs/firefly-rk3288_defconfig | 2 ++ configs/sandbox_defconfig | 2 ++ drivers/core/Kconfig | 19 +++++++++++++++++++ drivers/core/Makefile | 4 ++-- 5 files changed, 27 insertions(+), 2 deletions(-)
configs/chromebook_jerry_defconfig +2 -0
@@ -12,11 +12,13 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_SPL_SYSCON=y CONFIG_LED=y CONFIG_SPL_LED=y CONFIG_LED_GPIO=y
configs/firefly-rk3288_defconfig +2 -0
@@ -12,11 +12,13 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_SPL_SYSCON=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_RESET=y
configs/sandbox_defconfig +2 -0
@@ -17,7 +17,9 @@ CONFIG_CMD_TPM_TEST=y CONFIG_OF_CONTROL=y CONFIG_OF_HOSTFILE=y CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y CONFIG_DEVRES=y CONFIG_CLK=y CONFIG_SANDBOX_GPIO=y
drivers/core/Kconfig +19 -0
@@ -72,6 +72,16 @@ config REGMAP support any bus type (I2C, SPI) but so far this only supports direct memory access. +config SPL_REGMAP + bool "Support register maps in SPL" + depends on DM + help + Hardware peripherals tend to have one or more sets of registers + which can be accessed to control the hardware. A register map + models this with a simple read/write interface. It can in principle + support any bus type (I2C, SPI) but so far this only supports + direct memory access. + config SYSCON bool "Support system controllers" depends on REGMAP
@@ -81,6 +91,15 @@ config SYSCON by this uclass, including accessing registers via regmap and assigning a unique number to each. +config SPL_SYSCON + bool "Support system controllers in SPL" + depends on REGMAP + help + Many SoCs have a number of system controllers which are dealt with + as a group by a single driver. Some common functionality is provided + by this uclass, including accessing registers via regmap and + assigning a unique number to each. + config DEVRES bool "Managed device resources" depends on DM
drivers/core/Makefile +2 -2
@@ -9,5 +9,5 @@ obj-$(CONFIG_DEVRES) += devres.o obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE) += device-remove.o obj-$(CONFIG_$(SPL_)SIMPLE_BUS) += simple-bus.o obj-$(CONFIG_DM) += dump.o -obj-$(CONFIG_REGMAP) += regmap.o -obj-$(CONFIG_SYSCON) += syscon-uclass.o +obj-$(CONFIG_$(SPL_)REGMAP) += regmap.o +obj-$(CONFIG_$(SPL_)SYSCON) += syscon-uclass.o
Signature · 1 line
1.9.1
PATCH v6 5/23 dm: core: Add SPL Kconfig for REGMAP and SYSCON
Quoted 14 lines · Lin Huang
Add SPL
Kconfigfor REGMAP and SYSCON, so REGMAP and SYSCON can remove from SPL stage.Signed-off-by Lin Huang <[email protected]>Acked-by Simon Glass <[email protected]>---
Changes in v1: None
Changes in v2: None
Changes in v3:
- fix compile error
Changes in v4: None
Changes in v5: None
Changes in v6: None
Quoted 6 lines
configs/chromebook_jerry_defconfig | 2 ++ configs/firefly-rk3288_defconfig | 2 ++ configs/sandbox_defconfig | 2 ++ drivers/core/Kconfig | 19 +++++++++++++++++++ drivers/core/Makefile | 4 ++-- 5 files changed, 27 insertions(+), 2 deletions(-)
Applied to u-boot-rockchip, thanks!
PATCH v6 6/23 rockchip: serial driver support rk3036
In reply to Lin Huang---
Changes in v1: None
Changes in v2:
- modify code suggest by Simon
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
drivers/serial/serial_rockchip.c | 1 + 1 file changed, 1 insertion(+)
drivers/serial/serial_rockchip.c +1 -0
@@ -12,6 +12,7 @@static const struct udevice_id rockchip_serial_ids[] = { { .compatible ="rockchip,rk3288-uart" }, + { .compatible ="rockchip,rk3036-uart" }, { } };
Signature · 1 line
1.9.1
PATCH v6 6/23 rockchip: serial driver support rk3036
Quoted 11 lines · Lin Huang
Signed-off-by Lin Huang <[email protected]>Acked-by Simon Glass <[email protected]>---
Changes in v1: None
Changes in v2:
- modify code suggest by Simon
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
Quoted 2 lines
drivers/serial/serial_rockchip.c | 1 + 1 file changed, 1 insertion(+)
Applied to u-boot-rockchip, thanks!
PATCH v6 7/23 rockchip: Bring in RK3036 device tree file includes and bindings
In reply to Lin HuangSince rk3036 device tree file still in reviewing, bring it from
https://patchwork.kernel.org/patch/7203371/ and add some aliases we need in uboot
---
Changes in v1:
- clean copyright announcement
Changes in v2: None
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
arch/arm/dts/rk3036.dtsi | 427 +++++++++++++++++++++++++++++++++ include/dt-bindings/clock/rk3036-cru.h | 186 ++++++++++++++ 2 files changed, 613 insertions(+) create mode 100644 arch/arm/dts/rk3036.dtsi create mode 100644 include/dt-bindings/clock/rk3036-cru.h
arch/arm/dts/rk3036.dtsi new file +427 -0
@@ -0,0 +1,427 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rk3036-cru.h> +#include "skeleton.dtsi" + +/ { + compatible = "rockchip,rk3036"; + + interrupt-parent = <&gic>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + i2c1 = &i2c1; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + mmc0 = &emmc; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "rockchip,rk3036-smp"; + + cpu0: cpu at f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + operating-points = < + /* KHz uV */ + 816000 1000000 + >; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + resets = <&cru SRST_CORE0>; + }; + cpu1: cpu at f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + resets = <&cru SRST_CORE1>; + }; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma at 20078000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20078000 0x4000>; + arm,pl330-broken-no-flushp; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + }; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency = <24000000>; + }; + + cru: clock-controller at 20000000 { + compatible = "rockchip,rk3036-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>; + assigned-clock-rates = <594000000>; + }; + + uart0: serial at 20060000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg = <0x20060000 0x100>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + }; + + uart1: serial at 20064000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg = <0x20064000 0x100>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + }; + + uart2: serial at 20068000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg = <0x20068000 0x100>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + }; + + pwm0: pwm at 20050000 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050000 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm1: pwm at 20050010 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050010 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm2: pwm at 20050020 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050020 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm3: pwm at 20050030 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050030 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + sram: sram at 10080000 { + compatible = "rockchip,rk3036-smp-sram", "mmio-sram"; + reg = <0x10080000 0x2000>; + }; + + gic: interrupt-controller at 10139000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x10139000 0x1000>, + <0x1013a000 0x1000>, + <0x1013c000 0x2000>, + <0x1013e000 0x2000>; + interrupts = <GIC_PPI 9 0xf04>; + }; + + grf: syscon at 20008000 { + compatible = "rockchip,rk3036-grf", "syscon"; + reg = <0x20008000 0x1000>; + }; + + usb_otg: usb at 10180000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x10180000 0x40000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <275>; + g-tx-fifo-size = <256 128 128 64 64 32>; + g-use-dma; + status = "disabled"; + }; + + usb_host: usb at 101c0000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x101c0000 0x40000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG1>; + clock-names = "otg"; + dr_mode = "host"; + status = "disabled"; + }; + + emmc: dwmmc at 1021c000 { + compatible = "rockchip,rk3288-dw-mshc"; + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + dmas = <&pdma 12>; + dma-names = "rx-tx"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x1021c000 0x4000>; + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + disable-wp; + non-removable; + num-slots = <1>; + default-sample-phase = <158>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3036-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0 at 2007c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2007c000 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1 at 20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2 at 20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + emmc { + /* + * We run eMMC at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + emmc_clk: emmc-clk { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, + <1 25 RK_FUNC_2 &pcfg_pull_none>, + <1 26 RK_FUNC_2 &pcfg_pull_none>, + <1 27 RK_FUNC_2 &pcfg_pull_none>; + /* + <1 28 RK_FUNC_2 &pcfg_pull_up>, + <1 29 RK_FUNC_2 &pcfg_pull_up>, + <1 30 RK_FUNC_2 &pcfg_pull_up>, + <1 31 RK_FUNC_2 &pcfg_pull_up>; + */ + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, + <0 17 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, + <2 23 RK_FUNC_1 &pcfg_pull_none>; + }; + /* no rts / cts for uart1 */ + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, + <1 19 RK_FUNC_2 &pcfg_pull_none>; + }; + /* no rts / cts for uart2 */ + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <0 1 2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <0 27 1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, + <0 3 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; + + i2c1: i2c at 20056000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0x20056000 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; +};
include/dt-bindings/clock/rk3036-cru.h new file +186 -0
186 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH v6 7/23 rockchip: Bring in RK3036 device tree file includes and bindings
Quoted 15 lines · Lin Huang
Since rk3036 device tree file still in reviewing, bring it from
https://patchwork.kernel.org/patch/7203371/ and add some aliases we need in ubootSigned-off-by Lin Huang <[email protected]>Acked-by Simon Glass <[email protected]>---
Changes in v1:
- clean copyright announcement
Changes in v2: None
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
Quoted 5 lines
arch/arm/dts/rk3036.dtsi | 427 +++++++++++++++++++++++++++++++++ include/dt-bindings/clock/rk3036-cru.h | 186 ++++++++++++++ 2 files changed, 613 insertions(+) create mode 100644 arch/arm/dts/rk3036.dtsi create mode 100644 include/dt-bindings/clock/rk3036-cru.h
Applied to u-boot-rockchip, thanks!
PATCH v6 8/23 rockchip: rk3036: Add clock driver
In reply to Lin HuangAdd a driver for setting up and modifying the various PLLs, peripheral clocks and mmc clocks on RK3036
---
Changes in v1:
- clean copyright announcement
Changes in v2:
- move some macro to cru_rk3036.h
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 168 ++++++++++ drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 414 ++++++++++++++++++++++++ 3 files changed, 583 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3036.h create mode 100644 drivers/clk/clk_rk3036.c
arch/arm/include/asm/arch-rockchip/cru_rk3036.h new file +168 -0
@@ -0,0 +1,168 @@ +/* +* (C) Copyright 2015 Rockchip Electronics Co., Ltd +* +* SPDX-License-Identifier: GPL-2.0+ +*/ +#ifndef _ASM_ARCH_CRU_RK3036_H +#define _ASM_ARCH_CRU_RK3036_H + +#include <common.h> + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (600 * 1000000) +#define GPLL_HZ (594 * 1000000) + +#define CORE_PERI_HZ 150000000 +#define CORE_ACLK_HZ 300000000 + +#define CPU_ACLK_HZ 150000000 +#define CPU_HCLK_HZ 300000000 +#define CPU_PCLK_HZ 300000000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +struct rk3036_cru { +struct rk3036_pll { +unsigned int con0; +unsigned int con1; +unsigned int con2; +unsigned int con3; + } pll[4 ]; +unsigned int cru_mode_con; +unsigned int cru_clksel_con[35 ]; +unsigned int cru_clkgate_con[11 ]; +unsigned int reserved; +unsigned int cru_glb_srst_fst_value; +unsigned int cru_glb_srst_snd_value; +unsigned int reserved1[2 ]; +unsigned int cru_softrst_con[9 ]; +unsigned int cru_misc_con; +unsigned int reserved2[2 ]; +unsigned int cru_glb_cnt_th; +unsigned int cru_sdmmc_con[2 ]; +unsigned int cru_sdio_con[2 ]; +unsigned int cru_emmc_con[2 ]; +unsigned int reserved3; +unsigned int cru_rst_st; +unsigned int reserved4[0x23 ]; +unsigned int cru_pll_mask_con; +}; +check_member (rk3036_cru, cru_pll_mask_con,0x01f0 ); + +struct pll_div { +u32 refdiv; +u32 fbdiv; +u32 postdiv1; +u32 postdiv2; +u32 frac; +}; + +enum { +/* PLLCON0*/ +PLL_POSTDIV1_MASK =7 , +PLL_POSTDIV1_SHIFT =12 , +PLL_FBDIV_MASK =0xfff , +PLL_FBDIV_SHIFT =0 , + +/* PLLCON1 */ +PLL_DSMPD_MASK =1 , +PLL_DSMPD_SHIFT =12 , +PLL_LOCK_STATUS_MASK =1 , +PLL_LOCK_STATUS_SHIFT =10 , +PLL_POSTDIV2_MASK =7 , +PLL_POSTDIV2_SHIFT =6 , +PLL_REFDIV_MASK =0x3f , +PLL_REFDIV_SHIFT =0 , +PLL_RST_SHIFT =14 , + +/* CRU_MODE */ +GPLL_MODE_MASK =3 , +GPLL_MODE_SHIFT =12 , +GPLL_MODE_SLOW =0 , +GPLL_MODE_NORM , +GPLL_MODE_DEEP , +DPLL_MODE_MASK =1 , +DPLL_MODE_SHIFT =4 , +DPLL_MODE_SLOW =0 , +DPLL_MODE_NORM , +APLL_MODE_MASK =1 , +APLL_MODE_SHIFT =0 , +APLL_MODE_SLOW =0 , +APLL_MODE_NORM , + +/* CRU_CLK_SEL0_CON */ +CPU_CLK_PLL_SEL_MASK =3 , +CPU_CLK_PLL_SEL_SHIFT =14 , +CPU_CLK_PLL_SEL_APLL =0 , +CPU_CLK_PLL_SEL_DPLL , +CPU_CLK_PLL_SEL_GPLL , +ACLK_CPU_DIV_MASK =0x1f , +ACLK_CPU_DIV_SHIFT =8 , +CORE_CLK_PLL_SEL_MASK =1 , +CORE_CLK_PLL_SEL_SHIFT =7 , +CORE_CLK_PLL_SEL_APLL =0 , +CORE_CLK_PLL_SEL_GPLL , +CORE_DIV_CON_MASK =0x1f , +CORE_DIV_CON_SHIFT =0 , + +/* CRU_CLK_SEL1_CON */ +CPU_PCLK_DIV_MASK =7 , +CPU_PCLK_DIV_SHIFT =12 , +CPU_HCLK_DIV_MASK =3 , +CPU_HCLK_DIV_SHIFT =8 , +CORE_ACLK_DIV_MASK =7 , +CORE_ACLK_DIV_SHIFT =4 , +CORE_PERI_DIV_MASK =0xf , +CORE_PERI_DIV_SHIFT =0 , + +/* CRU_CLKSEL10_CON */ +PERI_PLL_SEL_MASK =3 , +PERI_PLL_SEL_SHIFT =14 , +PERI_PLL_APLL =0 , +PERI_PLL_DPLL , +PERI_PLL_GPLL , +PERI_PCLK_DIV_MASK =3 , +PERI_PCLK_DIV_SHIFT =12 , +PERI_HCLK_DIV_MASK =3 , +PERI_HCLK_DIV_SHIFT =8 , +PERI_ACLK_DIV_MASK =0x1f , +PERI_ACLK_DIV_SHIFT =0 , + +/* CRU_CLKSEL11_CON */ +SDIO_DIV_MASK =0x7f , +SDIO_DIV_SHIFT =8 , +MMC0_DIV_MASK =0x7f , +MMC0_DIV_SHIFT =0 , + +/* CRU_CLKSEL12_CON */ +EMMC_PLL_MASK =3 , +EMMC_PLL_SHIFT =12 , +EMMC_SEL_APLL =0 , +EMMC_SEL_DPLL , +EMMC_SEL_GPLL , +EMMC_SEL_24M , +SDIO_PLL_MASK =3 , +SDIO_PLL_SHIFT =10 , +SDIO_SEL_APLL =0 , +SDIO_SEL_DPLL , +SDIO_SEL_GPLL , +SDIO_SEL_24M , +MMC0_PLL_MASK =3 , +MMC0_PLL_SHIFT =8 , +MMC0_SEL_APLL =0 , +MMC0_SEL_DPLL , +MMC0_SEL_GPLL , +MMC0_SEL_24M , +EMMC_DIV_MASK =0x7f , +EMMC_DIV_SHIFT =0 , + +/* CRU_SOFTRST5_CON */ +DDRCTRL_PSRST_SHIFT =11 , +DDRCTRL_SRST_SHIFT =10 , +DDRPHY_PSRST_SHIFT =9 , +DDRPHY_SRST_SHIFT =8 , +}; +#endif
drivers/clk/Makefile +1 -0
@@ -6,5 +6,6 @@ # obj-$(CONFIG_CLK) += clk-uclass.o +obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_SANDBOX) += clk_sandbox.o
drivers/clk/clk_rk3036.c new file +414 -0
414 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH v6 8/23 rockchip: rk3036: Add clock driver
Quoted 15 lines · Lin Huang
Add a driver for setting up and modifying the various PLLs, peripheral clocks and mmc clocks on RK3036
Signed-off-by Lin Huang <[email protected]>Acked-by Simon Glass <[email protected]>---
Changes in v1:
- clean copyright announcement
Changes in v2:
- move some macro tocru_rk3036.h
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
Quoted 6 lines
arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 168 ++++++++++ drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 414 ++++++++++++++++++++++++ 3 files changed, 583 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3036.h create mode 100644 drivers/clk/clk_rk3036.c
Applied to u-boot-rockchip, thanks!
PATCH v6 9/23 rockchip: rk3036: Add header files for GRF
In reply to Lin HuangGRF is the gereral register file. Add header files with register definitions.
---
Changes in v1:
- clean copyright announcement
Changes in v2:
- move some macro to grf_rk3036.h
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 ++++++++++++++++++++++++ 1 file changed, 493 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3036.h
arch/arm/include/asm/arch-rockchip/grf_rk3036.h new file +493 -0
@@ -0,0 +1,493 @@ +/* +* (C) Copyright 2015 Rockchip Electronics Co., Ltd +* +* SPDX-License-Identifier: GPL-2.0+ +*/ +#ifndef _ASM_ARCH_GRF_RK3036_H +#define _ASM_ARCH_GRF_RK3036_H + +#include <common.h> + +struct rk3036_grf { +unsigned int reserved[0x2a ]; +unsigned int gpio0a_iomux; +unsigned int gpio0b_iomux; +unsigned int gpio0c_iomux; +unsigned int gpio0d_iomux; + +unsigned int gpio1a_iomux; +unsigned int gpio1b_iomux; +unsigned int gpio1c_iomux; +unsigned int gpio1d_iomux; + +unsigned int gpio2a_iomux; +unsigned int gpio2b_iomux; +unsigned int gpio2c_iomux; +unsigned int gpio2d_iomux; + +unsigned int reserved2[0x0a ]; +unsigned int gpiods; +unsigned int reserved3[0x05 ]; +unsigned int gpio0l_pull; +unsigned int gpio0h_pull; +unsigned int gpio1l_pull; +unsigned int gpio1h_pull; +unsigned int gpio2l_pull; +unsigned int gpio2h_pull; +unsigned int reserved4[4 ]; +unsigned int soc_con0; +unsigned int soc_con1; +unsigned int soc_con2; +unsigned int soc_status0; +unsigned int reserved5; +unsigned int soc_con3; +unsigned int reserved6; +unsigned int dmac_con0; +unsigned int dmac_con1; +unsigned int dmac_con2; +unsigned int reserved7[5 ]; +unsigned int uoc0_con5; +unsigned int reserved8[4 ]; +unsigned int uoc1_con4; +unsigned int uoc1_con5; +unsigned int reserved9; +unsigned int ddrc_stat; +unsigned int uoc_con6; +unsigned int soc_status1; +unsigned int cpu_con0; +unsigned int cpu_con1; +unsigned int cpu_con2; +unsigned int cpu_con3; +unsigned int reserved10; +unsigned int reserved11; +unsigned int cpu_status0; +unsigned int cpu_status1; +unsigned int os_reg[8 ]; +unsigned int reserved12[6 ]; +unsigned int dll_con[4 ]; +unsigned int dll_status[4 ]; +unsigned int dfi_wrnum; +unsigned int dfi_rdnum; +unsigned int dfi_actnum; +unsigned int dfi_timerval; +unsigned int nfi_fifo[4 ]; +unsigned int reserved13[0x10 ]; +unsigned int usbphy0_con[8 ]; +unsigned int usbphy1_con[8 ]; +unsigned int reserved14[0x10 ]; +unsigned int chip_tag; +unsigned int sdmmc_det_cnt; +}; +check_member (rk3036_grf, sdmmc_det_cnt,0x304 ); + +/* GRF_GPIO0A_IOMUX */ +enum { +GPIO0A3_SHIFT =6 , +GPIO0A3_MASK =1 , +GPIO0A3_GPIO =0 , +GPIO0A3_I2C1_SDA , + +GPIO0A2_SHIFT =4 , +GPIO0A2_MASK =1 , +GPIO0A2_GPIO =0 , +GPIO0A2_I2C1_SCL , + +GPIO0A1_SHIFT =2 , +GPIO0A1_MASK =3 , +GPIO0A1_GPIO =0 , +GPIO0A1_I2C0_SDA , +GPIO0A1_PWM2 , + +GPIO0A0_SHIFT =0 , +GPIO0A0_MASK =3 , +GPIO0A0_GPIO =0 , +GPIO0A0_I2C0_SCL , +GPIO0A0_PWM1 , + +}; + +/* GRF_GPIO0B_IOMUX */ +enum { +GPIO0B6_SHIFT =12 , +GPIO0B6_MASK =3 , +GPIO0B6_GPIO =0 , +GPIO0B6_MMC1_D3 , +GPIO0B6_I2S1_SCLK , + +GPIO0B5_SHIFT =10 , +GPIO0B5_MASK =3 , +GPIO0B5_GPIO =0 , +GPIO0B5_MMC1_D2 , +GPIO0B5_I2S1_SDI , + +GPIO0B4_SHIFT =8 , +GPIO0B4_MASK =3 , +GPIO0B4_GPIO =0 , +GPIO0B4_MMC1_D1 , +GPIO0B4_I2S1_LRCKTX , + +GPIO0B3_SHIFT =6 , +GPIO0B3_MASK =3 , +GPIO0B3_GPIO =0 , +GPIO0B3_MMC1_D0 , +GPIO0B3_I2S1_LRCKRX , + +GPIO0B1_SHIFT =2 , +GPIO0B1_MASK =3 , +GPIO0B1_GPIO =0 , +GPIO0B1_MMC1_CLKOUT , +GPIO0B1_I2S1_MCLK , + +GPIO0B0_SHIFT =0 , +GPIO0B0_MASK =3 , +GPIO0B0_GPIO =0 , +GPIO0B0_MMC1_CMD , +GPIO0B0_I2S1_SDO , +}; + +/* GRF_GPIO0C_IOMUX */ +enum { +GPIO0C4_SHIFT =8 , +GPIO0C4_MASK =1 , +GPIO0C4_GPIO =0 , +GPIO0C4_DRIVE_VBUS , + +GPIO0C3_SHIFT =6 , +GPIO0C3_MASK =1 , +GPIO0C3_GPIO =0 , +GPIO0C3_UART0_CTSN , + +GPIO0C2_SHIFT =4 , +GPIO0C2_MASK =1 , +GPIO0C2_GPIO =0 , +GPIO0C2_UART0_RTSN , + +GPIO0C1_SHIFT =2 , +GPIO0C1_MASK =1 , +GPIO0C1_GPIO =0 , +GPIO0C1_UART0_SIN , + + +GPIO0C0_SHIFT =0 , +GPIO0C0_MASK =1 , +GPIO0C0_GPIO =0 , +GPIO0C0_UART0_SOUT , +}; + +/* GRF_GPIO0D_IOMUX */ +enum { +GPIO0D4_SHIFT =8 , +GPIO0D4_MASK =1 , +GPIO0D4_GPIO =0 , +GPIO0D4_SPDIF , + +GPIO0D3_SHIFT =6 , +GPIO0D3_MASK =1 , +GPIO0D3_GPIO =0 , +GPIO0D3_PWM3 , + +GPIO0D2_SHIFT =4 , +GPIO0D2_MASK =1 , +GPIO0D2_GPIO =0 , +GPIO0D2_PWM0 , +}; + +/* GRF_GPIO1A_IOMUX */ +enum { +GPIO1A5_SHIFT =10 , +GPIO1A5_MASK =1 , +GPIO1A5_GPIO =0 , +GPIO1A5_I2S_SDI , + +GPIO1A4_SHIFT =8 , +GPIO1A4_MASK =1 , +GPIO1A4_GPIO =0 , +GPIO1A4_I2S_SD0 , + +GPIO1A3_SHIFT =6 , +GPIO1A3_MASK =1 , +GPIO1A3_GPIO =0 , +GPIO1A3_I2S_LRCKTX , + +GPIO1A2_SHIFT =4 , +GPIO1A2_MASK =6 , +GPIO1A2_GPIO =0 , +GPIO1A2_I2S_LRCKRX , +GPIO1A2_I2S_PWM1_0 , + +GPIO1A1_SHIFT =2 , +GPIO1A1_MASK =1 , +GPIO1A1_GPIO =0 , +GPIO1A1_I2S_SCLK , + +GPIO1A0_SHIFT =0 , +GPIO1A0_MASK =1 , +GPIO1A0_GPIO =0 , +GPIO1A0_I2S_MCLK , + +}; + +/* GRF_GPIO1B_IOMUX */ +enum { +GPIO1B7_SHIFT =14 , +GPIO1B7_MASK =1 , +GPIO1B7_GPIO =0 , +GPIO1B7_MMC0_CMD , + +GPIO1B3_SHIFT =6 , +GPIO1B3_MASK =1 , +GPIO1B3_GPIO =0 , +GPIO1B3_HDMI_HPD , + +GPIO1B2_SHIFT =4 , +GPIO1B2_MASK =1 , +GPIO1B2_GPIO =0 , +GPIO1B2_HDMI_SCL , + +GPIO1B1_SHIFT =2 , +GPIO1B1_MASK =1 , +GPIO1B1_GPIO =0 , +GPIO1B1_HDMI_SDA , + +GPIO1B0_SHIFT =0 , +GPIO1B0_MASK =1 , +GPIO1B0_GPIO =0 , +GPIO1B0_HDMI_CEC , +}; + +/* GRF_GPIO1C_IOMUX */ +enum { +GPIO1C5_SHIFT =10 , +GPIO1C5_MASK =3 , +GPIO1C5_GPIO =0 , +GPIO1C5_MMC0_D3 , +GPIO1C5_JTAG_TMS , + +GPIO1C4_SHIFT =8 , +GPIO1C4_MASK =3 , +GPIO1C4_GPIO =0 , +GPIO1C4_MMC0_D2 , +GPIO1C4_JTAG_TCK , + +GPIO1C3_SHIFT =6 , +GPIO1C3_MASK =3 , +GPIO1C3_GPIO =0 , +GPIO1C3_MMC0_D1 , +GPIO1C3_UART2_SOUT , + +GPIO1C2_SHIFT =4 , +GPIO1C2_MASK =3 , +GPIO1C2_GPIO =0 , +GPIO1C2_MMC0_D0 , +GPIO1C2_UART2_SIN , + +GPIO1C1_SHIFT =2 , +GPIO1C1_MASK =1 , +GPIO1C1_GPIO =0 , +GPIO1C1_MMC0_DETN , + +GPIO1C0_SHIFT =0 , +GPIO1C0_MASK =1 , +GPIO1C0_GPIO =0 , +GPIO1C0_MMC0_CLKOUT , +}; + +/* GRF_GPIO1D_IOMUX */ +enum { +GPIO1D7_SHIFT =14 , +GPIO1D7_MASK =3 , +GPIO1D7_GPIO =0 , +GPIO1D7_NAND_D7 , +GPIO1D7_EMMC_D7 , +GPIO1D7_SPI_CSN1 , + +GPIO1D6_SHIFT =12 , +GPIO1D6_MASK =3 , +GPIO1D6_GPIO =0 , +GPIO1D6_NAND_D6 , +GPIO1D6_EMMC_D6 , +GPIO1D6_SPI_CSN0 , + +GPIO1D5_SHIFT =10 , +GPIO1D5_MASK =3 , +GPIO1D5_GPIO =0 , +GPIO1D5_NAND_D5 , +GPIO1D5_EMMC_D5 , +GPIO1D5_SPI_TXD , + +GPIO1D4_SHIFT =8 , +GPIO1D4_MASK =3 , +GPIO1D4_GPIO =0 , +GPIO1D4_NAND_D4 , +GPIO1D4_EMMC_D4 , +GPIO1D4_SPI_RXD , + +GPIO1D3_SHIFT =6 , +GPIO1D3_MASK =3 , +GPIO1D3_GPIO =0 , +GPIO1D3_NAND_D3 , +GPIO1D3_EMMC_D3 , +GPIO1D3_SFC_SIO3 , + +GPIO1D2_SHIFT =4 , +GPIO1D2_MASK =3 , +GPIO1D2_GPIO =0 , +GPIO1D2_NAND_D2 , +GPIO1D2_EMMC_D2 , +GPIO1D2_SFC_SIO2 , + +GPIO1D1_SHIFT =2 , +GPIO1D1_MASK =3 , +GPIO1D1_GPIO =0 , +GPIO1D1_NAND_D1 , +GPIO1D1_EMMC_D1 , +GPIO1D1_SFC_SIO1 , + +GPIO1D0_SHIFT =0 , +GPIO1D0_MASK =3 , +GPIO1D0_GPIO =0 , +GPIO1D0_NAND_D0 , +GPIO1D0_EMMC_D0 , +GPIO1D0_SFC_SIO0 , +}; + +/* GRF_GPIO2A_IOMUX */ +enum { +GPIO2A7_SHIFT =14 , +GPIO2A7_MASK =1 , +GPIO2A7_GPIO =0 , +GPIO2A7_TESTCLK_OUT , + +GPIO2A6_SHIFT =12 , +GPIO2A6_MASK =1 , +GPIO2A6_GPIO =0 , +GPIO2A6_NAND_CS0 , + +GPIO2A4_SHIFT =8 , +GPIO2A4_MASK =3 , +GPIO2A4_GPIO =0 , +GPIO2A4_NAND_RDY , +GPIO2A4_EMMC_CMD , +GPIO2A3_SFC_CLK , + +GPIO2A3_SHIFT =6 , +GPIO2A3_MASK =3 , +GPIO2A3_GPIO =0 , +GPIO2A3_NAND_RDN , +GPIO2A4_SFC_CSN1 , + +GPIO2A2_SHIFT =4 , +GPIO2A2_MASK =3 , +GPIO2A2_GPIO =0 , +GPIO2A2_NAND_WRN , +GPIO2A4_SFC_CSN0 , + +GPIO2A1_SHIFT =2 , +GPIO2A1_MASK =3 , +GPIO2A1_GPIO =0 , +GPIO2A1_NAND_CLE , +GPIO2A1_EMMC_CLKOUT , + +GPIO2A0_SHIFT =0 , +GPIO2A0_MASK =3 , +GPIO2A0_GPIO =0 , +GPIO2A0_NAND_ALE , +GPIO2A0_SPI_CLK , +}; + +/* GRF_GPIO2B_IOMUX */ +enum { +GPIO2B7_SHIFT =14 , +GPIO2B7_MASK =1 , +GPIO2B7_GPIO =0 , +GPIO2B7_MAC_RXER , + +GPIO2B6_SHIFT =12 , +GPIO2B6_MASK =3 , +GPIO2B6_GPIO =0 , +GPIO2B6_MAC_CLKOUT , +GPIO2B6_MAC_CLKIN , + +GPIO2B5_SHIFT =10 , +GPIO2B5_MASK =1 , +GPIO2B5_GPIO =0 , +GPIO2B5_MAC_TXEN , + +GPIO2B4_SHIFT =8 , +GPIO2B4_MASK =1 , +GPIO2B4_GPIO =0 , +GPIO2B4_MAC_MDIO , + +GPIO2B2_SHIFT =4 , +GPIO2B2_MASK =1 , +GPIO2B2_GPIO =0 , +GPIO2B2_MAC_CRS , +}; + +/* GRF_GPIO2C_IOMUX */ +enum { +GPIO2C7_SHIFT =14 , +GPIO2C7_MASK =3 , +GPIO2C7_GPIO =0 , +GPIO2C7_UART1_SOUT , +GPIO2C7_TESTCLK_OUT1 , + +GPIO2C6_SHIFT =12 , +GPIO2C6_MASK =1 , +GPIO2C6_GPIO =0 , +GPIO2C6_UART1_SIN , + +GPIO2C5_SHIFT =10 , +GPIO2C5_MASK =1 , +GPIO2C5_GPIO =0 , +GPIO2C5_I2C2_SCL , + +GPIO2C4_SHIFT =8 , +GPIO2C4_MASK =1 , +GPIO2C4_GPIO =0 , +GPIO2C4_I2C2_SDA , + +GPIO2C3_SHIFT =6 , +GPIO2C3_MASK =1 , +GPIO2C3_GPIO =0 , +GPIO2C3_MAC_TXD0 , + +GPIO2C2_SHIFT =4 , +GPIO2C2_MASK =1 , +GPIO2C2_GPIO =0 , +GPIO2C2_MAC_TXD1 , + +GPIO2C1_SHIFT =2 , +GPIO2C1_MASK =1 , +GPIO2C1_GPIO =0 , +GPIO2C1_MAC_RXD0 , + +GPIO2C0_SHIFT =0 , +GPIO2C0_MASK =1 , +GPIO2C0_GPIO =0 , +GPIO2C0_MAC_RXD1 , +}; + +/* GRF_GPIO2D_IOMUX */ +enum { +GPIO2D6_SHIFT =12 , +GPIO2D6_MASK =1 , +GPIO2D6_GPIO =0 , +GPIO2D6_I2S_SDO1 , + +GPIO2D5_SHIFT =10 , +GPIO2D5_MASK =1 , +GPIO2D5_GPIO =0 , +GPIO2D5_I2S_SDO2 , + +GPIO2D4_SHIFT =8 , +GPIO2D4_MASK =1 , +GPIO2D4_GPIO =0 , +GPIO2D4_I2S_SDO3 , + +GPIO2D1_SHIFT =2 , +GPIO2D1_MASK =1 , +GPIO2D1_GPIO =0 , +GPIO2D1_MAC_MDC , +}; +#endif
Signature · 1 line
1.9.1
PATCH v6 9/23 rockchip: rk3036: Add header files for GRF
Quoted 14 lines · Lin Huang
GRF is the gereral register file. Add header files with register definitions.
Signed-off-by Lin Huang <[email protected]>Acked-by Simon Glass <[email protected]>---
Changes in v1:
- clean copyright announcement
Changes in v2:
- move some macro togrf_rk3036.h
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
Quoted 3 lines
arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 ++++++++++++++++++++++++ 1 file changed, 493 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3036.h
Applied to u-boot-rockchip, thanks!
PATCH v6 10/23 rockchip: rk3036: Add Soc reset driver
In reply to Lin HuangWe can reset the Soc using some CRU (clock/reset unit) register. Add support for this.
---
---
Changes in v1:
- clean copyright announcement
Changes in v2:
- only build reset_rk3036.c in NON-SPL stage
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
arch/arm/mach-rockchip/rk3036/Makefile | 10 +++++++ arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3036/Makefile create mode 100644 arch/arm/mach-rockchip/rk3036/reset_rk3036.c
arch/arm/mach-rockchip/rk3036/Makefile new file +10 -0
@@ -0,0 +1,10 @@ +# +# (C) Copyright 2015 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifndef CONFIG_SPL_BUILD +obj-y += reset_rk3036.o +endif +
arch/arm/mach-rockchip/rk3036/reset_rk3036.c new file +45 -0
45 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH v6 10/23 rockchip: rk3036: Add Soc reset driver
Quoted 16 lines · Lin Huang
We can reset the Soc using some CRU (clock/reset unit) register. Add support for this.
Signed-off-by Lin Huang <[email protected]>Acked-by Simon Glass <[email protected]>---
---
Changes in v1:
- clean copyright announcement
Changes in v2:
- only buildreset_rk3036.cin NON-SPL stage
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6: None
Quoted 5 lines
arch/arm/mach-rockchip/rk3036/Makefile | 10 +++++++ arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3036/Makefile create mode 100644 arch/arm/mach-rockchip/rk3036/reset_rk3036.c
Applied to u-boot-rockchip, thanks!
PATCH v6 11/23 rockchip: rk3036: Add a simple syscon driver
In reply to Lin HuangAdd a driver that provides access to system controllers
---
Changes in v1:
- clean copyright announcement
Changes in v2:
- only build syscon_rk3036.c on NON-SPL stage
Changes in v3: None
Changes in v4: None
Changes in v5: None
arch/arm/mach-rockchip/rk3036/Makefile | 2 +- arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-rockchip/rk3036/syscon_rk3036.c
arch/arm/mach-rockchip/rk3036/Makefile +1 -1
@@ -6,5 +6,5 @@ ifndef CONFIG_SPL_BUILD obj-y += reset_rk3036.o +obj-y += syscon_rk3036.o endif -
arch/arm/mach-rockchip/rk3036/syscon_rk3036.c new file +21 -0
@@ -0,0 +1,21 @@ +/* +* (C) Copyright 2015 Rockchip Electronics Co., Ltd +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> + +static const struct udevice_id rk3036_syscon_ids[] = { + { .compatible ="rockchip,rk3036-grf" , .data =ROCKCHIP_SYSCON_GRF }, + { } +}; + +U_BOOT_DRIVER (syscon_rk3036) = { + .name ="rk3036_syscon" , + .id =UCLASS_SYSCON , + .of_match = rk3036_syscon_ids, +};
Signature · 1 line
1.9.1
PATCH v6 11/23 rockchip: rk3036: Add a simple syscon driver
Quoted 13 lines · Lin Huang
Add a driver that provides access to system controllers
Signed-off-by Lin Huang <[email protected]>Acked-by Simon Glass <[email protected]>---
Changes in v1:
- clean copyright announcement
Changes in v2:
- only buildsyscon_rk3036.con NON-SPL stage
Changes in v3: None
Changes in v4: None
Changes in v5: None
Quoted 4 lines
arch/arm/mach-rockchip/rk3036/Makefile | 2 +- arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-rockchip/rk3036/syscon_rk3036.c
Applied to u-boot-rockchip, thanks!
PATCH v6 12/23 rockchip: rk3036: Add pinctrl driver
In reply to Lin HuangAdd a driver which support pin multiplexing setup for rk3036
---
Changes in v1:
- clean copyright announcement
Changes in v2: None
Changes in v3:
- fix some coding style error
Changes in v4: None
Changes in v5: None
Changes in v6:
- remove duplicate ROCKCHIP_PINCTRL in Kconfig
drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++++++++++++++++++++++++ 3 files changed, 286 insertions(+) create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c
drivers/pinctrl/Kconfig +9 -0
@@ -114,6 +114,15 @@ config ROCKCHIP_PINCTRL definitions and pin control functions for each available multiplex function. +config ROCKCHIP_3036_PINCTRL + bool "Rockchip rk3036 pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is + controlled by a device tree node which contains both the GPIO + definitions and pin control functions for each available multiplex + function. + config PINCTRL_SANDBOX bool "Sandbox pinctrl driver" depends on SANDBOX
drivers/pinctrl/rockchip/Makefile +1 -0
@@ -6,3 +6,4 @@ # obj-$(CONFIG_ROCKCHIP_PINCTRL) += pinctrl_rk3288.o +obj-$(CONFIG_ROCKCHIP_3036_PINCTRL) += pinctrl_rk3036.o
drivers/pinctrl/rockchip/pinctrl_rk3036.c new file +276 -0
276 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH v6 12/23 rockchip: rk3036: Add pinctrl driver
Quoted 15 lines · Lin Huang
Add a driver which support pin multiplexing setup for rk3036
Signed-off-by Lin Huang <[email protected]>Acked-by Simon Glass <[email protected]>---
Changes in v1:
- clean copyright announcement
Changes in v2: None
Changes in v3:
- fix some coding style error
Changes in v4: None
Changes in v5: None
Changes in v6:
- remove duplicateROCKCHIP_PINCTRLinKconfig
Quoted 5 lines
drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++++++++++++++++++++++++ 3 files changed, 286 insertions(+) create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c
Applied to u-boot-rockchip, thanks!
PATCH v6 13/23 mmc: dw_mmc: move data transfer as a separate function
In reply to Lin Huangthe data transfer seem to long in the dwmci_send_cmd function, so move this block as a separate funciton.
---
drivers/mmc/dw_mmc.c | 65 ++++++++++++++++++++++++++++++---------------------- 1 file changed, 37 insertions(+), 28 deletions(-)
drivers/mmc/dw_mmc.c +37 -28
@@ -94,6 +94,42 @@ static void dwmci_prepare_data(struct dwmci_host *host,dwmci_writel (host,DWMCI_BYTCNT , data->blocksize * data->blocks); } +static int dwmci_data_transfer (struct dwmci_host *host) +{ +int ret =0 ; +unsigned int timeout =240000 ; +u32 mask; +ulong start =get_timer (0 ); + +for (;;) { + mask =dwmci_readl (host,DWMCI_RINTSTS ); +/* Error during data transfer. */ +if (mask & (DWMCI_DATA_ERR |DWMCI_DATA_TOUT )) { +debug ("%s: DATA ERROR!\n" , __func__); + ret = -EINVAL ; +break ; + } + +/* Data arrived correctly. */ +if (mask &DWMCI_INTMSK_DTO ) { + ret =0 ; +break ; + } + +/* Check for timeout. */ +if (get_timer (start) > timeout) { +debug ("%s: Timeout waiting for data!\n" , + __func__); + ret =TIMEOUT ; +break ; + } + } + +dwmci_writel (host,DWMCI_RINTSTS , mask); + +return ret; +} +static int dwmci_set_transfer_mode (struct dwmci_host *host,struct mmc_data *data) {
@@ -213,38 +249,11 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, }if (data) { - start =get_timer (0 ); - timeout =240000 ; -for (;;) { - mask =dwmci_readl (host,DWMCI_RINTSTS ); -/* Error during data transfer. */ -if (mask & (DWMCI_DATA_ERR |DWMCI_DATA_TOUT )) { -debug ("%s: DATA ERROR!\n" , __func__); - ret = -EINVAL ; -break ; - } - -/* Data arrived correctly. */ -if (mask &DWMCI_INTMSK_DTO ) { - ret =0 ; -break ; - } - -/* Check for timeout. */ -if (get_timer (start) > timeout) { -debug ("%s: Timeout waiting for data!\n" , - __func__); - ret =TIMEOUT ; -break ; - } - } - -dwmci_writel (host,DWMCI_RINTSTS , mask); + ret =dwmci_data_transfer (host); ctrl =dwmci_readl (host,DWMCI_CTRL ); ctrl &= ~(DWMCI_DMA_EN );dwmci_writel (host,DWMCI_CTRL , ctrl); -bounce_buffer_stop (&bbstate); }
Signature · 1 line
1.9.1
PATCH v6 13/23 mmc: dw_mmc: move data transfer as a separate function
Quoted 8 lines · Lin Huang
the data transfer seem to long in the
dwmci_send_cmdfunction, so move this block as a separate funciton.Signed-off-by Lin Huang <[email protected]>---
drivers/mmc/dw_mmc.c | 65 ++++++++++++++++++++++++++++++---------------------- 1 file changed, 37 insertions(+), 28 deletions(-)
PATCH v6 14/23 mmc: dw_mmc: support fifo mode in dwc mmc driver
In reply to Lin Huangsome soc(rk3036 etc) use dw_mmc but do not have internal dma, so we implement fifo mode to read and write data.
---
Changes in v1: None
Changes in v2: None
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6:
- move data fifo mode to dwmci_data_transfer() function
drivers/mmc/dw_mmc.c | 85 +++++++++++++++++++++++++++++++++++++++++----------- include/dwmmc.h | 5 ++++ 2 files changed, 72 insertions(+), 18 deletions(-)
drivers/mmc/dw_mmc.c +67 -18
@@ -94,12 +94,21 @@ static void dwmci_prepare_data(struct dwmci_host *host,dwmci_writel (host,DWMCI_BYTCNT , data->blocksize * data->blocks); } -static int dwmci_data_transfer (struct dwmci_host *host) +static int dwmci_data_transfer (struct dwmci_host *host,struct mmc_data *data) {int ret =0 ; -unsigned int timeout =240000 ; -u32 mask; +u32 timeout =240000 ; +u32 mask, size, i, len =0 ; +u32 *buf =NULL ;ulong start =get_timer (0 ); +u32 fifo_depth = (((host->fifoth_val &RX_WMARK_MASK ) >> +RX_WMARK_SHIFT ) +1 ) *2 ; + + size = data->blocksize * data->blocks /4 ; +if (data->flags ==MMC_DATA_READ ) + buf = (unsigned int *)data->dest; +else + buf = (unsigned int *)data->src;for (;;) { mask =dwmci_readl (host,DWMCI_RINTSTS );
@@ -110,6 +119,36 @@ static int dwmci_data_transfer(struct dwmci_host *host)break ; } +if (host->fifo_mode && size) { +if (data->flags ==MMC_DATA_READ ) { +if ((dwmci_readl (host,DWMCI_RINTSTS ) && +DWMCI_INTMSK_RXDR )) { + len =dwmci_readl (host,DWMCI_STATUS ); + len = (len >>DWMCI_FIFO_SHIFT ) & +DWMCI_FIFO_MASK ; +for (i =0 ; i < len; i++) + *buf++ = +dwmci_readl (host,DWMCI_DATA ); +dwmci_writel (host,DWMCI_RINTSTS , +DWMCI_INTMSK_RXDR ); + } + }else { +if ((dwmci_readl (host,DWMCI_RINTSTS ) && +DWMCI_INTMSK_TXDR )) { + len =dwmci_readl (host,DWMCI_STATUS ); + len = fifo_depth - ((len >> +DWMCI_FIFO_SHIFT ) & +DWMCI_FIFO_MASK ); +for (i =0 ; i < len; i++) +dwmci_writel (host,DWMCI_DATA , + *buf++); +dwmci_writel (host,DWMCI_RINTSTS , +DWMCI_INTMSK_TXDR ); + } + } + size = size > len ? (size - len) :0 ; + } +/* Data arrived correctly. */ if (mask &DWMCI_INTMSK_DTO ) { ret =0 ;
@@ -165,17 +204,24 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,dwmci_writel (host,DWMCI_RINTSTS ,DWMCI_INTMSK_ALL );if (data) { -if (data->flags ==MMC_DATA_READ ) { -bounce_buffer_start (&bbstate, (void *)data->dest, - data->blocksize * - data->blocks,GEN_BB_WRITE ); +if (host->fifo_mode) { +dwmci_writel (host,DWMCI_BLKSIZ , data->blocksize); +dwmci_writel (host,DWMCI_BYTCNT , + data->blocksize * data->blocks); +dwmci_wait_reset (host,DWMCI_CTRL_FIFO_RESET ); }else { -bounce_buffer_start (&bbstate, (void *)data->src, - data->blocksize * - data->blocks,GEN_BB_READ ); +if (data->flags ==MMC_DATA_READ ) { +bounce_buffer_start (&bbstate, (void *)data->dest, + data->blocksize * + data->blocks,GEN_BB_WRITE ); + }else { +bounce_buffer_start (&bbstate, (void *)data->src, + data->blocksize * + data->blocks,GEN_BB_READ ); + } +dwmci_prepare_data (host, data, cur_idmac, + bbstate.bounce_buffer); } -dwmci_prepare_data (host, data, cur_idmac, - bbstate.bounce_buffer); }dwmci_writel (host,DWMCI_CMDARG , cmd->cmdarg);
@@ -249,12 +295,15 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, }if (data) { - ret =dwmci_data_transfer (host); - - ctrl =dwmci_readl (host,DWMCI_CTRL ); - ctrl &= ~(DWMCI_DMA_EN ); -dwmci_writel (host,DWMCI_CTRL , ctrl); -bounce_buffer_stop (&bbstate); + ret =dwmci_data_transfer (host, data); + +/* only dma mode need it */ +if (!host->fifo_mode) { + ctrl =dwmci_readl (host,DWMCI_CTRL ); + ctrl &= ~(DWMCI_DMA_EN ); +dwmci_writel (host,DWMCI_CTRL , ctrl); +bounce_buffer_stop (&bbstate); + } }udelay (100 );
include/dwmmc.h +5 -0
@@ -105,6 +105,8 @@/* Status Register */ #define DWMCI_BUSY (1 << 9) +#define DWMCI_FIFO_MASK 0x1ff +#define DWMCI_FIFO_SHIFT 17/* FIFOTH Register */ #define MSIZE (x) ((x) << 28)
@@ -180,6 +182,9 @@ struct dwmci_host {unsigned int (*get_mmc_clk)(struct dwmci_host *host,uint freq);struct mmc_config cfg; + +/* use fifo mode to read and write data */ +bool fifo_mode; };struct dwmci_idmac {
Signature · 1 line
1.9.1
PATCH v6 14/23 mmc: dw_mmc: support fifo mode in dwc mmc driver
Quoted 13 lines · Lin Huang
some soc(rk3036 etc) use
dw_mmcbut do not have internal dma, so we implement fifo mode to read and write data.Signed-off-by Lin Huang <[email protected]>---
Changes in v1: None
Changes in v2: None
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6:
- move data fifo mode todwmci_data_transfer()function
Quoted 3 lines
drivers/mmc/dw_mmc.c | 85 +++++++++++++++++++++++++++++++++++++++++----------- include/dwmmc.h | 5 ++++ 2 files changed, 72 insertions(+), 18 deletions(-)
I suspect this could be a little tidier but it seems reasonable to me.
PATCH v6 15/23 rockchip: mmc: use non-removable property to disginguish emmc and sdcard register
In reply to Lin Huangemmc and sdcard have different register address, use non-removeable property to disginuish them.
--- drivers/mmc/rockchip_dw_mmc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
drivers/mmc/rockchip_dw_mmc.c +4 -2
@@ -50,8 +50,10 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; host->priv = dev; -/* TODO(sjg at chromium.org): Remove the need for this hack */ - host->dev_index = (ulong )host->ioaddr ==0xff0f0000 ?0 :1 ; +/* use non-removeable as sdcard and emmc as judgement */ +if (fdtdec_lookup_phandle (gd->fdt_blob, dev->of_offset,"non-removable" ) + == -FDT_ERR_NOTFOUND ) + host->dev_index =1 ;return 0 ; }
Signature · 1 line
1.9.1
PATCH v6 15/23 rockchip: mmc: use non-removable property to disginguish emmc and sdcard register
Hi Lin,
Quoted 2 lines · Lin Huang
emmc and sdcard have different register address, use non-removeable property to disginuish them.
distinguish
(also please fix commit subject)
Quoted 11 lines
Signed-off-by Lin Huang <[email protected]>--- drivers/mmc/rockchip_dw_mmc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)drivers/mmc/rockchip_dw_mmc.c +0
-0
drivers/mmc/rockchip_dw_mmc.c static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) · line 55
Quoted 8 lines
drivers/mmc/rockchip_dw_mmc.c +3
-2@@ -50,8 +50,10 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; host->priv = dev; -/* TODO(sjg at chromium.org): Remove the need for this hack */ - host->dev_index = (ulong )host->ioaddr ==0xff0f0000 ?0 :1 ; +/* use non-removeable as sdcard and emmc as judgement */ +if (fdtdec_lookup_phandle (gd->fdt_blob, dev->of_offset,"non-removable" ) + == -FDT_ERR_NOTFOUND )
Should be fdtdec_get_bool(), right?
Quoted 7 lines
drivers/mmc/rockchip_dw_mmc.c +1
-1+ host->dev_index =1 ;return 0 ; } --1.9.1
Regards,
Simon
PATCH v6 16/23 rockchip: mmc: get the fifo mode and fifo depth property from dts
In reply to Lin Huangrk3036 mmc do not have internal dma, so we use fifo mode when read and write data, we get the fifo mode and fifo depth property from dts, pass to dw_mmc driver.
---
Changes in v1: None
Changes in v2: None
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6:
- Advices by Simon:
- use int instead of u32 for fifo_depth
- use fdtdec_get_bool() to get "fifo-mode" property
arch/arm/dts/rk3036.dtsi | 1 + drivers/mmc/rockchip_dw_mmc.c | 21 +++++++++++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-)
arch/arm/dts/rk3036.dtsi +1 -0
@@ -257,6 +257,7 @@ cap-mmc-highspeed; mmc-ddr-1_8v; disable-wp; + fifo-mode; non-removable; num-slots = <1>; default-sample-phase = <158>;
drivers/mmc/rockchip_dw_mmc.c +17 -4
@@ -65,6 +65,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev)struct dwmci_host *host = &priv->host;u32 minmax[2 ];int ret; +int fifo_depth; priv->grf =syscon_get_first_range (ROCKCHIP_SYSCON_GRF );if (IS_ERR (priv->grf))
@@ -73,10 +74,22 @@ static int rockchip_dwmmc_probe(struct udevice *dev)if (ret)return ret; - ret =fdtdec_get_int_array (gd->fdt_blob, dev->of_offset, -"clock-freq-min-max" , minmax,2 ); -if (!ret) - ret =add_dwmci (host, minmax[1 ], minmax[0 ]); +if (fdtdec_get_int_array (gd->fdt_blob, dev->of_offset, +"clock-freq-min-max" , minmax,2 )) +return -EINVAL ; + + fifo_depth =fdtdec_get_int (gd->fdt_blob, dev->of_offset, +"fifo-depth" ,0 ); +if (fifo_depth <0 ) +return -EINVAL ; + + host->fifoth_val =MSIZE (0x2 ) | +RX_WMARK (fifo_depth /2 -1 ) |TX_WMARK (fifo_depth /2 ); + +if (fdtdec_get_bool (gd->fdt_blob, dev->of_offset,"fifo-mode" )) + host->fifo_mode = true; + + ret =add_dwmci (host, minmax[1 ], minmax[0 ]);if (ret)return ret;
Signature · 1 line
1.9.1
PATCH v6 16/23 rockchip: mmc: get the fifo mode and fifo depth property from dts
Quoted 16 lines · Lin Huang
rk3036 mmc do not have internal dma, so we use fifo mode when read and write data, we get the fifo mode and fifo depth property from dts, pass to
dw_mmcdriver.Signed-off-by Lin Huang <[email protected]>---
Changes in v1: None
Changes in v2: None
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6:
- Advices by Simon:
- use int instead of u32 forfifo_depth
- usefdtdec_get_bool()to get "fifo-mode" property
Quoted 3 lines
arch/arm/dts/rk3036.dtsi | 1 + drivers/mmc/rockchip_dw_mmc.c | 21 +++++++++++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-)
PATCH v6 17/23 rockchip: add early uart driver
In reply to Lin Huangadd early uart driver so we can print debug message in SPL stage
---
Changes in v1: None
Changes in v2: None
Changes in v3:
- pass uart base address to rk_uart_init() function Changes in v4: None
Changes in v5: None
Changes in v6:
- Adviced by Simon:
- add some comment
arch/arm/include/asm/arch-rockchip/uart.h | 44 +++++++++++++++++++++ arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk_early_print.c | 63 +++++++++++++++++++++++++++++++ 3 files changed, 108 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/uart.h create mode 100644 arch/arm/mach-rockchip/rk_early_print.c
arch/arm/include/asm/arch-rockchip/uart.h new file +44 -0
@@ -0,0 +1,44 @@ +/* +* (C) Copyright 2015 Rockchip Electronics Co., Ltd +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __ASM_ARCH_UART_H +#define __ASM_ARCH_UART_H +struct rk_uart { +unsigned int rbr;/* Receive buffer register. */ +unsigned int ier;/* Interrupt enable register. */ +unsigned int fcr;/* FIFO control register. */ +unsigned int lcr;/* Line control register. */ +unsigned int mcr;/* Modem control register. */ +unsigned int lsr;/* Line status register. */ +unsigned int msr;/* Modem status register. */ +unsigned int scr; +unsigned int reserved1[(0x30 -0x20 ) /4 ]; +unsigned int srbr[(0x70 -0x30 ) /4 ]; +unsigned int far; +unsigned int tfr; +unsigned int rfw; +unsigned int usr; +unsigned int tfl; +unsigned int rfl; +unsigned int srr; +unsigned int srts; +unsigned int sbcr; +unsigned int sdmam; +unsigned int sfe; +unsigned int srt; +unsigned int stet; +unsigned int htx; +unsigned int dmasa; +unsigned int reserver2[(0xf4 -0xac ) /4 ]; +unsigned int cpr; +unsigned int ucv; +unsigned int ctr; +}; + +void rk_uart_init (void *base); +void print_hex (unsigned int n); +void char *s); +#endif
arch/arm/mach-rockchip/Makefile +1 -0
@@ -10,5 +10,6 @@ else obj-y += board.o endif obj-y += rk_timer.o +obj-y += rk_early_print.o obj-$(CONFIG_$(SPL_)ROCKCHIP_COMMON) += common.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
arch/arm/mach-rockchip/rk_early_print.c new file +63 -0
63 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH v6 17/23 rockchip: add early uart driver
Quoted 16 lines · Lin Huang
add early uart driver so we can print debug message in SPL stage
Signed-off-by Lin Huang <[email protected]>Acked-by Simon Glass <[email protected]>---
Changes in v1: None
Changes in v2: None
Changes in v3:
- pass uart base address tork_uart_init()function Changes in v4: None
Changes in v5: None
Changes in v6:
- Adviced by Simon:
- add some comment
Quoted 6 lines
arch/arm/include/asm/arch-rockchip/uart.h | 44 +++++++++++++++++++++ arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk_early_print.c | 63 +++++++++++++++++++++++++++++++ 3 files changed, 108 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/uart.h create mode 100644 arch/arm/mach-rockchip/rk_early_print.c
Applied to u-boot-rockchip, thanks!
(as discussed, there is future work to try to unify this with the ns16550 debug UART)
PATCH v6 18/23 rockchip: add rk3036 sdram driver
In reply to Lin Huangadd rk3036 sdram driver so we can set up sdram in SPL
---
Changes in v1: None
Changes in v2: None
Changes in v3:
- fix some code style error
Changes in v4:
- modify code advice by Simon Glass
Changes in v5:
- Advice by Simon:
- move some global variables to local variables
- delete __weak get_ddr_config() function
Changes in v6:
- Adviced by Simon:
- pass pointer to the function call
- fix some nits
arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 ++++++++++ arch/arm/mach-rockchip/rk3036/Makefile | 2 + arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 764 ++++++++++++++++++++++ 3 files changed, 1107 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3036.h create mode 100644 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
arch/arm/include/asm/arch-rockchip/sdram_rk3036.h new file +341 -0
@@ -0,0 +1,341 @@ +/* +* (C) Copyright 2015 Rockchip Electronics Co., Ltd +* +* SPDX-License-Identifier: GPL-2.0+ +*/ +#ifndef _ASM_ARCH_SDRAM_RK3036_H +#define _ASM_ARCH_SDRAM_RK3036_H + +#include <common.h> + +struct rk3036_ddr_pctl { +u32 scfg; +u32 sctl; +u32 stat; +u32 intrstat; +u32 reserved0[12 ]; +u32 mcmd; +u32 powctl; +u32 powstat; +u32 cmdtstat; +u32 cmdtstaten; +u32 reserved1[3 ]; +u32 mrrcfg0; +u32 mrrstat0; +u32 mrrstat1; +u32 reserved2[4 ]; +u32 mcfg1; +u32 mcfg; +u32 ppcfg; +u32 mstat; +u32 lpddr2zqcfg; +u32 reserved3; +u32 dtupdes; +u32 dtuna; +u32 dtune; +u32 dtuprd0; +u32 dtuprd1; +u32 dtuprd2; +u32 dtuprd3; +u32 dtuawdt; +u32 reserved4[3 ]; +u32 togcnt1u; +u32 tinit; +u32 trsth; +u32 togcnt100n; +u32 trefi; +u32 tmrd; +u32 trfc; +u32 trp; +u32 trtw; +u32 tal; +u32 tcl; +u32 tcwl; +u32 tras; +u32 trc; +u32 trcd; +u32 trrd; +u32 trtp; +u32 twr; +u32 twtr; +u32 texsr; +u32 txp; +u32 txpdll; +u32 tzqcs; +u32 tzqcsi; +u32 tdqs; +u32 tcksre; +u32 tcksrx; +u32 tcke; +u32 tmod; +u32 trstl; +u32 tzqcl; +u32 tmrr; +u32 tckesr; +u32 reserved5[47 ]; +u32 dtuwactl; +u32 dturactl; +u32 dtucfg; +u32 dtuectl; +u32 dtuwd0; +u32 dtuwd1; +u32 dtuwd2; +u32 dtuwd3; +u32 dtuwdm; +u32 dturd0; +u32 dturd1; +u32 dturd2; +u32 dturd3; +u32 dtulfsrwd; +u32 dtulfsrrd; +u32 dtueaf; +u32 dfitctrldelay; +u32 dfiodtcfg; +u32 dfiodtcfg1; +u32 dfiodtrankmap; +u32 dfitphywrdata; +u32 dfitphywrlat; +u32 reserved7[2 ]; +u32 dfitrddataen; +u32 dfitphyrdlat; +u32 reserved8[2 ]; +u32 dfitphyupdtype0; +u32 dfitphyupdtype1; +u32 dfitphyupdtype2; +u32 dfitphyupdtype3; +u32 dfitctrlupdmin; +u32 dfitctrlupdmax; +u32 dfitctrlupddly; +u32 reserved9; +u32 dfiupdcfg; +u32 dfitrefmski; +u32 dfitctrlupdi; +u32 reserved10[4 ]; +u32 dfitrcfg0; +u32 dfitrstat0; +u32 dfitrwrlvlen; +u32 dfitrrdlvlen; +u32 dfitrrdlvlgateen; +u32 dfiststat0; +u32 dfistcfg0; +u32 dfistcfg1; +u32 reserved11; +u32 dfitdramclken; +u32 dfitdramclkdis; +u32 dfistcfg2; +u32 dfistparclr; +u32 dfistparlog; +u32 reserved12[3 ]; +u32 dfilpcfg0; +u32 reserved13[3 ]; +u32 dfitrwrlvlresp0; +u32 dfitrwrlvlresp1; +u32 dfitrwrlvlresp2; +u32 dfitrrdlvlresp0; +u32 dfitrrdlvlresp1; +u32 dfitrrdlvlresp2; +u32 dfitrwrlvldelay0; +u32 dfitrwrlvldelay1; +u32 dfitrwrlvldelay2; +u32 dfitrrdlvldelay0; +u32 dfitrrdlvldelay1; +u32 dfitrrdlvldelay2; +u32 dfitrrdlvlgatedelay0; +u32 dfitrrdlvlgatedelay1; +u32 dfitrrdlvlgatedelay2; +u32 dfitrcmd; +u32 reserved14[46 ]; +u32 ipvr; +u32 iptr; +}; +check_member (rk3036_ddr_pctl, iptr,0x03fc ); + +struct rk3036_ddr_phy { +u32 ddrphy_reg1; +u32 ddrphy_reg3; +u32 ddrphy_reg2; +u32 reserve[11 ]; +u32 ddrphy_reg4a; +u32 ddrphy_reg4b; +u32 reserve1[5 ]; +u32 ddrphy_reg16; +u32 reserve2; +u32 ddrphy_reg18; +u32 ddrphy_reg19; +u32 reserve3; +u32 ddrphy_reg21; +u32 reserve4; +u32 ddrphy_reg22; +u32 reserve5[3 ]; +u32 ddrphy_reg25; +u32 ddrphy_reg26; +u32 ddrphy_reg27; +u32 ddrphy_reg28; +u32 reserve6[17 ]; +u32 ddrphy_reg6; +u32 ddrphy_reg7; +u32 reserve7; +u32 ddrphy_reg8; +u32 ddrphy_reg0e4; +u32 reserve8[11 ]; +u32 ddrphy_reg9; +u32 ddrphy_reg10; +u32 reserve9; +u32 ddrphy_reg11; +u32 ddrphy_reg124; +u32 reserve10[38 ]; +u32 ddrphy_reg29; +u32 reserve11[40 ]; +u32 ddrphy_reg264; +u32 reserve12[18 ]; +u32 ddrphy_reg2a; +u32 reserve13[4 ]; +u32 ddrphy_reg30; +u32 ddrphy_reg31; +u32 ddrphy_reg32; +u32 ddrphy_reg33; +u32 ddrphy_reg34; +u32 ddrphy_reg35; +u32 ddrphy_reg36; +u32 ddrphy_reg37; +u32 ddrphy_reg38; +u32 ddrphy_reg39; +u32 ddrphy_reg40; +u32 ddrphy_reg41; +u32 ddrphy_reg42; +u32 ddrphy_reg43; +u32 ddrphy_reg44; +u32 ddrphy_reg45; +u32 ddrphy_reg46; +u32 ddrphy_reg47; +u32 ddrphy_reg48; +u32 ddrphy_reg49; +u32 ddrphy_reg50; +u32 ddrphy_reg51; +u32 ddrphy_reg52; +u32 ddrphy_reg53; +u32 reserve14; +u32 ddrphy_reg54; +u32 ddrphy_reg55; +u32 ddrphy_reg56; +u32 ddrphy_reg57; +u32 ddrphy_reg58; +u32 ddrphy_reg59; +u32 ddrphy_reg5a; +u32 ddrphy_reg5b; +u32 ddrphy_reg5c; +u32 ddrphy_reg5d; +u32 ddrphy_reg5e; +u32 reserve15[28 ]; +u32 ddrphy_reg5f; +u32 reserve16[6 ]; +u32 ddrphy_reg60; +u32 ddrphy_reg61; +u32 ddrphy_reg62; +}; +check_member (rk3036_ddr_phy, ddrphy_reg62,0x03e8 ); + +struct rk3036_pctl_timing { +u32 togcnt1u; +u32 tinit; +u32 trsth; +u32 togcnt100n; +u32 trefi; +u32 tmrd; +u32 trfc; +u32 trp; +u32 trtw; +u32 tal; +u32 tcl; +u32 tcwl; +u32 tras; +u32 trc; +u32 trcd; +u32 trrd; +u32 trtp; +u32 twr; +u32 twtr; +u32 texsr; +u32 txp; +u32 txpdll; +u32 tzqcs; +u32 tzqcsi; +u32 tdqs; +u32 tcksre; +u32 tcksrx; +u32 tcke; +u32 tmod; +u32 trstl; +u32 tzqcl; +u32 tmrr; +u32 tckesr; +u32 tdpd; +}; + +struct rk3036_phy_timing { +u32 mr[4 ]; +u32 bl; +u32 cl_al; +}; + +typedef union { +u32 noc_timing; +struct { +u32 acttoact:6 ; +u32 rdtomiss:6 ; +u32 wrtomiss:6 ; +u32 burstlen:3 ; +u32 rdtowr:5 ; +u32 wrtord:5 ; +u32 bwratio:1 ; + }; +}rk3036_noc_timing ; + +struct rk3036_ddr_timing { +u32 freq; +struct rk3036_pctl_timing pctl_timing; +struct rk3036_phy_timing phy_timing; +rk3036_noc_timing noc_timing; +}; + +struct rk3036_service_sys { +u32 id_coreid; +u32 id_revisionid; +u32 ddrconf; +u32 ddrtiming; +u32 ddrmode; +u32 readlatency; +}; + +struct rk3036_ddr_config { +/* +* 000: lpddr +* 001: ddr +* 010: ddr2 +* 011: ddr3 +* 100: lpddr2-s2 +* 101: lpddr2-s4 +* 110: lpddr3 +*/ +u32 ddr_type; +u32 rank; +u32 cs0_row; +u32 cs1_row; + +/* 2: 4bank, 3: 8bank */ +u32 bank; +u32 col; + +/* bw(0: 8bit, 1: 16bit, 2: 32bit) */ +u32 bw; +}; + +/* rk3036 sdram initial */ +void sdram_init (void ); + +/* get ddr die config, implement in specific board */ +void get_ddr_config (struct rk3036_ddr_config *config); + +/* get ddr size on board */ +size_t sdram_size (void ); +#endif
arch/arm/mach-rockchip/rk3036/Makefile +2 -0
@@ -8,3 +8,5 @@ ifndef CONFIG_SPL_BUILD obj-y += reset_rk3036.o obj-y += syscon_rk3036.o endif + +obj-y += sdram_rk3036.o
arch/arm/mach-rockchip/rk3036/sdram_rk3036.c new file +764 -0
764 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH v6 18/23 rockchip: add rk3036 sdram driver
Quoted 19 lines · Lin Huang
add rk3036 sdram driver so we can set up sdram in SPL
Signed-off-by Lin Huang <[email protected]>---
Changes in v1: None
Changes in v2: None
Changes in v3:
- fix some code style error
Changes in v4:
- modify code advice by Simon Glass
Changes in v5:
- Advice by Simon:
- move some global variables to local variables
- delete__weakget_ddr_config()function
Changes in v6:
- Adviced by Simon:
- pass pointer to the function call
- fix some nits
Quoted 6 lines
arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 ++++++++++ arch/arm/mach-rockchip/rk3036/Makefile | 2 + arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 764 ++++++++++++++++++++++ 3 files changed, 1107 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3036.h create mode 100644 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
PATCH v6 19/23 rockchip: rk3036: Add core Soc start-up code
In reply to Lin Huangrk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart.
---
Changes in v1:
- clean copyright announcement
Changes in v2:
- support SPL
Changes in v3:
- delete DEBUG_UART config
- modify ENV_MEM_LAYOUT_SETTINGS config Changes in v4:
- delete some unuse config advice by Sjoerd Simons Changes in v5:
- use CONFIG_DWMMC
Changes in v6:
- Adviced by Simon:
- fix some nits
arch/arm/mach-rockchip/Kconfig | 10 ++- arch/arm/mach-rockchip/Makefile | 4 +- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 55 +++++++++++++ arch/arm/mach-rockchip/rk3036/Kconfig | 17 ++++ arch/arm/mach-rockchip/rk3036/Makefile | 1 + arch/arm/mach-rockchip/rk3036/save_boot_param.S | 32 ++++++++ include/configs/rk3036_common.h | 103 ++++++++++++++++++++++++ 8 files changed, 221 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk3036-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3036/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3036/save_boot_param.S create mode 100644 include/configs/rk3036_common.h
arch/arm/mach-rockchip/Kconfig +9 -1
@@ -9,6 +9,14 @@ config ROCKCHIP_RK3288 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs. +config ROCKCHIP_RK3036 + bool "Support Rockchip RK3036" + help + The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 + including NEON and GPU, Mali-400 graphics, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. + config SYS_MALLOC_F default y
@@ -34,5 +42,5 @@ config ROCKCHIP_SERIAL default y source "arch/arm/mach-rockchip/rk3288/Kconfig" - +source "arch/arm/mach-rockchip/rk3036/Kconfig" endif
arch/arm/mach-rockchip/Makefile +3 -1
@@ -6,10 +6,12 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o else -obj-y += board.o +obj-$(CONFIG_ROCKCHIP_RK3288) += board.o endif obj-y += rk_timer.o obj-y += rk_early_print.o obj-$(CONFIG_$(SPL_)ROCKCHIP_COMMON) += common.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ +obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
arch/arm/mach-rockchip/board.c +1 -0
@@ -7,6 +7,7 @@#include <common.h> #include <dm.h> #include <ram.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR ;
arch/arm/mach-rockchip/rk3036-board-spl.c new file +55 -0
55 lines not on this page · raw message
arch/arm/mach-rockchip/rk3036/Kconfig new file +17 -0
@@ -0,0 +1,17 @@ +if ROCKCHIP_RK3036 + +config TARGET_EVB_RK3036 + bool "EVB_RK3036" + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x400 + +config ROCKCHIP_COMMON + bool "Support rk common fuction" + +source "board/evb_rk3036/evb_rk3036/Kconfig" + +endif
arch/arm/mach-rockchip/rk3036/Makefile +1 -0
@@ -10,3 +10,4 @@ obj-y += syscon_rk3036.o endif obj-y += sdram_rk3036.o +obj-y += save_boot_param.o
arch/arm/mach-rockchip/rk3036/save_boot_param.S new file +32 -0
@@ -0,0 +1,32 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> + +.globl SAVE_SP_ADDR +SAVE_SP_ADDR: + .word 0 + +/* + * void save_boot_params + * + * Save sp, lr, r1~r12 + */ +ENTRY(save_boot_params) + push {r1-r12, lr} + ldr r0, =SAVE_SP_ADDR + str sp, [r0] + b save_boot_params_ret @ back to my caller +ENDPROC(save_boot_params) + + +.globl back_to_bootrom +ENTRY(back_to_bootrom) + ldr r0, =SAVE_SP_ADDR + ldr sp, [r0] + mov r0, #0 + pop {r1-r12, pc} +ENDPROC(back_to_bootrom)
include/configs/rk3036_common.h new file +103 -0
103 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH v6 20/23 rockchip: Add basic support for evb-rk3036 board
In reply to Lin HuangThis add some basic files required to allow the board to dispaly serial message and can run command(mmc info etc)
---
Changes in v1:
- clean copyright announcement
Changes in v2:
- get sdram info from evb_rk3036.c
Changes in v3:
- delete some config
Changes in v4: None
Changes in v5:
- use CONFIG_ROCKCHIP_DWMMC instead CONFIG_ROCKCHIP_3036_DWMMC Changes in v6:
- Advices by Simon:
- fix some nits
arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3036-sdk.dts | 46 ++++++++++++++++++++++++++++++ board/evb_rk3036/evb_rk3036/Kconfig | 15 ++++++++++ board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 +++++ board/evb_rk3036/evb_rk3036/evb_rk3036.c | 49 ++++++++++++++++++++++++++++++++ configs/evb-rk3036_defconfig | 26 +++++++++++++++++ include/configs/evb_rk3036.h | 12 ++++++++ 8 files changed, 157 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3036-sdk.dts create mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644 board/evb_rk3036/evb_rk3036/evb_rk3036.c create mode 100644 configs/evb-rk3036_defconfig create mode 100644 include/configs/evb_rk3036.h
arch/arm/dts/Makefile +2 -1
@@ -21,7 +21,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5422-odroidxu3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-firefly.dtb \ - rk3288-jerry.dtb + rk3288-jerry.dtb \ + rk3036-sdk.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \
arch/arm/dts/rk3036-sdk.dts new file +46 -0
46 lines not on this page · raw message
board/evb_rk3036/evb_rk3036/Kconfig new file +15 -0
@@ -0,0 +1,15 @@ +if TARGET_EVB_RK3036 + +config SYS_BOARD + default "evb_rk3036" + +config SYS_VENDOR + default "evb_rk3036" + +config SYS_CONFIG_NAME + default "evb_rk3036" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif
board/evb_rk3036/evb_rk3036/MAINTAINERS new file +0 -0
board/evb_rk3036/evb_rk3036/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb_rk3036.o
board/evb_rk3036/evb_rk3036/evb_rk3036.c new file +49 -0
49 lines not on this page · raw message
configs/evb-rk3036_defconfig new file +26 -0
@@ -0,0 +1,26 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ROCKCHIP_RK3036=y +CONFIG_TARGET_EVB_RK3036=y +CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CLK=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_RESET=y +CONFIG_LED=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_ROCKCHIP_DWMMC=y +CONFIG_ROCKCHIP_3036_PINCTRL=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_RAM=y +CONFIG_DM_MMC=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y
include/configs/evb_rk3036.h new file +12 -0
@@ -0,0 +1,12 @@ +/* +* (C) Copyright 2015 Rockchip Electronics Co., Ltd +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/rk3036_common.h> + +#endif
Signature · 1 line
1.9.1
PATCH v6 21/23 rockchip: Add max spl size & spl header configs
In reply to Lin HuangFrom: Jeffy Chen <[email protected]>
Our chips may have different max spl size and spl header, so we need to add configs for that.
---
Changes in v1: None
Changes in v2: None
Changes in v3: None
Changes in v4: None
Changes in v5:
- Adviced by Simon:
- move CONFIG_ROCKCHIP_MAX_INIT_SIZE and CONFIG_ROCKCHIP_CHIP_TAG
- to arch/arm/mach-rokchip/Kconfig
Changes in v6:
- Adviced by Simon:
- Kconfig more descriptive with more detail
arch/arm/mach-rockchip/Kconfig | 15 +++++++++++++++ arch/arm/mach-rockchip/rk3036/Kconfig | 6 ++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 6 ++++++ include/configs/rk3288_common.h | 2 ++ tools/Makefile | 6 ++++++ tools/rkcommon.c | 2 +- tools/rkcommon.h | 1 - tools/rkimage.c | 2 +- tools/rksd.c | 4 ++-- tools/rkspi.c | 4 ++-- 10 files changed, 41 insertions(+), 7 deletions(-)
arch/arm/mach-rockchip/Kconfig +15 -0
@@ -17,6 +17,21 @@ config ROCKCHIP_RK3036 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. +config ROCKCHIP_SPL_HDR + string "Header of rockchip's spl loader" + help + Rockchip's bootrom requires the spl loader to start with a 4-bytes + header. The content of this header depends on the chip type. + +config ROCKCHIP_MAX_SPL_SIZE + hex "Max size of rockchip's spl loader" + help + Different chip may have different sram size. And if we want to jump + back to the bootrom after spl, we may need to reserve some sram space + for the bootrom. + The max spl loader size should be sram size minus reserved + size(if needed) + config SYS_MALLOC_F default y
arch/arm/mach-rockchip/rk3036/Kconfig +6 -0
@@ -9,6 +9,12 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x400 +config ROCKCHIP_SPL_HDR + default "RK30" + +config ROCKCHIP_MAX_SPL_SIZE + default 0x1000 + config ROCKCHIP_COMMON bool "Support rk common fuction"
arch/arm/mach-rockchip/rk3288/Kconfig +6 -0
@@ -16,6 +16,12 @@ config TARGET_CHROMEBOOK_JERRY WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery functions. +config ROCKCHIP_SPL_HDR + default "RK32" + +config ROCKCHIP_MAX_SPL_SIZE + default 0x8000 + config SYS_SOC default "rockchip"
include/configs/rk3288_common.h +2 -0
@@ -44,6 +44,8 @@#define CONFIG_SPL_STACK 0xff718000#define CONFIG_SPL_TEXT_BASE 0xff704004 + +#define CONFIG_ROCKCHIP_MAX_SPL_SIZE (32 << 10)#define CONFIG_ROCKCHIP_COMMON #define CONFIG_SPL_ROCKCHIP_COMMON
tools/Makefile +6 -0
@@ -108,6 +108,12 @@ fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o # TODO([email protected]): Is this correct on Mac OS? +ifneq ($(CONFIG_ARCH_ROCKCHIP),) +HOST_EXTRACFLAGS += \ + -DCONFIG_ROCKCHIP_MAX_SPL_SIZE=$(CONFIG_ROCKCHIP_MAX_SPL_SIZE) \ + -DCONFIG_ROCKCHIP_SPL_HDR="\"$(CONFIG_ROCKCHIP_SPL_HDR)\"" +endif + ifneq ($(CONFIG_MX23)$(CONFIG_MX28),) # Add CONFIG_MXS into host CFLAGS, so we can check whether or not register # the mxsimage support within tools/mxsimage.c .
tools/rkcommon.c +1 -1
@@ -50,7 +50,7 @@ int rkcommon_set_header(void *buf, uint file_size) {struct header0_info *hdr; -if (file_size >RK_MAX_CODE1_SIZE ) +if (file_size >CONFIG_ROCKCHIP_MAX_SPL_SIZE )return -ENOSPC ;memset (buf,'\0' ,RK_CODE1_OFFSET *RK_BLK_SIZE );
tools/rkcommon.h +0 -1
@@ -11,7 +11,6 @@enum {RK_BLK_SIZE =512 ,RK_CODE1_OFFSET =4 , -RK_MAX_CODE1_SIZE =32 <<10 , };/**
tools/rkimage.c +1 -1
@@ -30,7 +30,7 @@ static void rkimage_print_header(const void *buf)static void rkimage_set_header (void *buf,struct stat *sbuf,int ifd,struct image_tool_params *params) { -memcpy (buf,"RK32" ,4 ); +memcpy (buf,CONFIG_ROCKCHIP_SPL_HDR ,4 ); }static int rkimage_extract_subimage (void *buf,struct image_tool_params *params)
tools/rksd.c +2 -2
@@ -50,7 +50,7 @@ static void rksd_set_header(void *buf, struct stat *sbuf, int ifd, size); } -memcpy (buf +RKSD_SPL_HDR_START ,"RK32" ,4 ); +memcpy (buf +RKSD_SPL_HDR_START ,CONFIG_ROCKCHIP_SPL_HDR ,4 ); }static int rksd_extract_subimage (void *buf,struct image_tool_params *params)
@@ -72,7 +72,7 @@ static int rksd_vrec_header(struct image_tool_params *params, {int pad_size; - pad_size =RKSD_SPL_HDR_START +RK_MAX_CODE1_SIZE ; + pad_size =RKSD_SPL_HDR_START +CONFIG_ROCKCHIP_MAX_SPL_SIZE ;debug ("pad_size %x\n" , pad_size);return pad_size - params->file_size;
tools/rkspi.c +2 -2
@@ -53,7 +53,7 @@ static void rkspi_set_header(void *buf, struct stat *sbuf, int ifd, size); } -memcpy (buf +RKSPI_SPL_HDR_START ,"RK32" ,4 ); +memcpy (buf +RKSPI_SPL_HDR_START ,CONFIG_ROCKCHIP_SPL_HDR ,4 );/* * Spread the image out so we only use the first 2KB of each 4KB
@@ -89,7 +89,7 @@ static int rkspi_vrec_header(struct image_tool_params *params, {int pad_size; - pad_size = (RK_MAX_CODE1_SIZE +0x7ff ) /0x800 *0x800 ; + pad_size = (CONFIG_ROCKCHIP_MAX_SPL_SIZE +0x7ff ) /0x800 *0x800 ; params->orig_file_size = pad_size;/* We will double the image size due to the SPI format */
Signature · 1 line
1.9.1
PATCH v6 22/23 rockchip: Add support for rk's second level loader
In reply to Lin HuangFrom: Jeffy Chen <[email protected]>
The Rockchip boot ROM could load & run an initial spl loader, and continue to load a second level boot-loader(which stored right after the initial loader) when it returns. Modify idblock generation code to support it.
---
Changes in v1: None
Changes in v2: None
Changes in v3: None
Changes in v4: None
Changes in v5: None
tools/rkcommon.c | 24 ++++++++++-------------- tools/rkcommon.h | 3 ++- tools/rksd.c | 2 +- tools/rkspi.c | 2 +- 4 files changed, 14 insertions(+), 17 deletions(-)
tools/rkcommon.c +10 -14
@@ -25,7 +25,7 @@ enum {* * @signature: Signature (must be RKSD_SIGNATURE) * @disable_rc4: 0 to use rc4 for boot image, 1 to use plain binary -* @code1_offset: Offset in blocks of the SPL code from this header +* @init_offset: Offset in blocks of the SPL code from this header * block. E.g. 4 means 2KB after the start of this header. * Other fields are not used by U-Boot */
@@ -33,11 +33,10 @@ struct header0_info {uint32_t signature;uint8_t reserved[4 ];uint32_t disable_rc4; -uint16_t code1_offset; -uint16_t code2_offset; -uint8_t reserved1[490 ]; -uint16_t usflashdatasize; -uint16_t ucflashbootsize; +uint16_t init_offset; +uint8_t reserved1[492 ]; +uint16_t init_size; +uint16_t init_boot_size;uint8_t reserved2[2 ]; };
@@ -53,18 +52,15 @@ int rkcommon_set_header(void *buf, uint file_size)if (file_size >CONFIG_ROCKCHIP_MAX_SPL_SIZE )return -ENOSPC ; -memset (buf,'\0' ,RK_CODE1_OFFSET *RK_BLK_SIZE ); +memset (buf,'\0' ,RK_INIT_OFFSET *RK_BLK_SIZE ); hdr = (struct header0_info *)buf; hdr->signature =RK_SIGNATURE ; hdr->disable_rc4 =1 ; - hdr->code1_offset =RK_CODE1_OFFSET ; - hdr->code2_offset =8 ; + hdr->init_offset =RK_INIT_OFFSET ; - hdr->usflashdatasize = (file_size +RK_BLK_SIZE -1 ) /RK_BLK_SIZE ; - hdr->usflashdatasize = (hdr->usflashdatasize +3 ) & ~3 ; - hdr->ucflashbootsize = hdr->usflashdatasize; - -debug ("size=%x, %x\n" , params->file_size, hdr->usflashdatasize); + hdr->init_size = (file_size +RK_BLK_SIZE -1 ) /RK_BLK_SIZE ; + hdr->init_size = (hdr->init_size +3 ) & ~3 ; + hdr->init_boot_size = hdr->init_size +RK_MAX_BOOT_SIZE /RK_BLK_SIZE ;rc4_encode (buf,RK_BLK_SIZE , rc4_key);
tools/rkcommon.h +2 -1
@@ -10,7 +10,8 @@enum {RK_BLK_SIZE =512 , -RK_CODE1_OFFSET =4 , +RK_INIT_OFFSET =4 , +RK_MAX_BOOT_SIZE =512 <<10 , };/**
tools/rksd.c +1 -1
@@ -14,7 +14,7 @@#include "rkcommon.h" enum { -RKSD_SPL_HDR_START =RK_CODE1_OFFSET *RK_BLK_SIZE , +RKSD_SPL_HDR_START =RK_INIT_OFFSET *RK_BLK_SIZE ,RKSD_SPL_START =RKSD_SPL_HDR_START +4 ,RKSD_HEADER_LEN =RKSD_SPL_START , };
tools/rkspi.c +1 -1
@@ -14,7 +14,7 @@#include "rkcommon.h" enum { -RKSPI_SPL_HDR_START =RK_CODE1_OFFSET *RK_BLK_SIZE , +RKSPI_SPL_HDR_START =RK_INIT_OFFSET *RK_BLK_SIZE ,RKSPI_SPL_START =RKSPI_SPL_HDR_START +4 ,RKSPI_HEADER_LEN =RKSPI_SPL_START ,RKSPI_SECT_LEN =RK_BLK_SIZE *4 ,
Signature · 1 line
1.9.1
PATCH v6 22/23 rockchip: Add support for rk's second level loader
Quoted 16 lines · Lin Huang
From: Jeffy Chen <[email protected]>
The Rockchip boot ROM could load & run an initial spl loader, and continue to load a second level boot-loader(which stored right after the initial loader) when it returns. Modify idblock generation code to support it.
Signed-off-by Jeffy Chen <[email protected]>Acked-by Simon Glass <[email protected]>---
Changes in v1: None
Changes in v2: None
Changes in v3: None
Changes in v4: None
Changes in v5: None
Quoted 5 lines
tools/rkcommon.c | 24 ++++++++++-------------- tools/rkcommon.h | 3 ++- tools/rksd.c | 2 +- tools/rkspi.c | 2 +- 4 files changed, 14 insertions(+), 17 deletions(-)
Applied to u-boot-rockchip, thanks!
PATCH v6 23/23 rockchip: doc: show packet rk3036 uboot image
In reply to Lin Huangshow how to packet rk3036 uboot image and boot from SD
---
Changes in v1: None
Changes in v2: None
Changes in v3: None
Changes in v4:
- fix some spell error
Changes in v5:
- Adviced by Simon:
- add evb rk3036 board to supported boards
Changes in v6:
- fix some nits
doc/README.rockchip | 11 +++++++++++ 1 file changed, 11 insertions(+)
doc/README.rockchip +11 -0
@@ -42,6 +42,10 @@ At present three RK3288 boards are supported: - Radxa Rock 2 - also uses firefly-rk3288 configuration - Haier Chromebook - use chromebook_jerry configuration +one RK3036 board is support: + + - EVB RK3036 - use evb-rk3036_defconfig configuration + For example: CROSS_COMPILE=arm-linux-gnueabi- make O=firefly firefly-rk3288_defconfig all
@@ -118,6 +122,13 @@ something like: Err: serial at ff690000 => +For evb_rk3036 board: + ./evb-rk3036/tools/mkimage -T rksd -d evb-rk3036/spl/u-boot-spl.bin out && \ + cat evb-rk3036/u-boot-dtb.bin >> out && \ + sudo dd if=out of=/dev/sdc seek=64 + +Note: rk3036 SDMMC and debug uart use the same iomux, so if you boot from SD, the + debug uart must be disabled Booting from SPI ================
Signature · 1 line
1.9.1
PATCH v6 23/23 rockchip: doc: show packet rk3036 uboot image
Quoted 16 lines · Lin Huang
show how to packet rk3036 uboot image and boot from SD
Signed-off-by Lin Huang <[email protected]>Acked-by Simon Glass <[email protected]>---
Changes in v1: None
Changes in v2: None
Changes in v3: None
Changes in v4:
- fix some spell error
Changes in v5:
- Adviced by Simon:
- add evb rk3036 board to supported boards
Changes in v6:
- fix some nits
Quoted 2 lines
doc/README.rockchip | 11 +++++++++++ 1 file changed, 11 insertions(+)
Applied to u-boot-rockchip, thanks!
v6 cover Bring up rk3036 uboot
In reply to Lin HuangHi Lin,
Quoted 117 lines · Lin Huang
This series patch bring up rk3036 uboot, since rk3036 only 4K size SRAM for SPL, so in SPL stage only support timer, uart, sdram driver, and back to bootrom when finish ddr initial, and boot up second stage from bootrom.You can boot to command line(mmc info etc) for now use this patchset.
Jeffy Chen (2):
rockchip: Add max spl size & spl header configs
rockchip: Add support for rk's second level loaderLin Huang (21):
rockchip: add timer driver
rockchip: moveSYS_MALLOC_F_LENto rk3288 ownKconfig
rockchip: renameboard-spl.ctork3288-board-spl.c
rockchip: add config decide whether to buildcommon.c
dm: core: Add SPLKconfigfor REGMAP and SYSCON
rockchip: serial driver support rk3036
rockchip: Bring in RK3036 device tree file includes and bindings
rockchip: rk3036: Add clock driver
rockchip: rk3036: Add header files for GRF
rockchip: rk3036: Add Soc reset driver
rockchip: rk3036: Add a simple syscon driver
rockchip: rk3036: Add pinctrl driver
mmc:dw_mmc: move data transfer as a separate function
mmc:dw_mmc: support fifo mode in dwc mmc driver
rockchip: mmc: use non-removable property to disginguish emmc and
sdcard register
rockchip: mmc: get the fifo mode and fifo depth property from dts
rockchip: add early uart driver
rockchip: add rk3036 sdram driver
rockchip: rk3036: Add core Soc start-up code
rockchip: Add basic support for evb-rk3036 board
rockchip: doc: show packet rk3036 uboot imagearch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3036-sdk.dts | 46 ++ arch/arm/dts/rk3036.dtsi | 428 ++++++++++++ arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 168 +++++ arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 ++++++++++++++ arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 ++++++++++ arch/arm/include/asm/arch-rockchip/timer.h | 22 + arch/arm/include/asm/arch-rockchip/uart.h | 44 ++ arch/arm/mach-rockchip/Kconfig | 28 +- arch/arm/mach-rockchip/Makefile | 10 +- arch/arm/mach-rockchip/board-spl.c | 294 --------- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 55 ++ arch/arm/mach-rockchip/rk3036/Kconfig | 23 + arch/arm/mach-rockchip/rk3036/Makefile | 13 + arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++ arch/arm/mach-rockchip/rk3036/save_boot_param.S | 32 + arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 764 ++++++++++++++++++++++ arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 + arch/arm/mach-rockchip/rk3288-board-spl.c | 277 ++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 9 + arch/arm/mach-rockchip/rk_early_print.c | 63 ++ arch/arm/mach-rockchip/rk_timer.c | 48 ++ board/evb_rk3036/evb_rk3036/Kconfig | 15 + board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 + board/evb_rk3036/evb_rk3036/evb_rk3036.c | 49 ++ configs/chromebook_jerry_defconfig | 2 + configs/evb-rk3036_defconfig | 26 + configs/firefly-rk3288_defconfig | 2 + configs/sandbox_defconfig | 2 + doc/README.rockchip | 11 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 414 ++++++++++++ drivers/core/Kconfig | 19 + drivers/core/Makefile | 4 +- drivers/mmc/dw_mmc.c | 140 ++-- drivers/mmc/rockchip_dw_mmc.c | 27 +- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++ drivers/serial/serial_rockchip.c | 1 + include/configs/evb_rk3036.h | 12 + include/configs/rk3036_common.h | 103 +++ include/configs/rk3288_common.h | 8 +- include/dt-bindings/clock/rk3036-cru.h | 186 ++++++ include/dwmmc.h | 5 + tools/Makefile | 6 + tools/rkcommon.c | 26 +- tools/rkcommon.h | 4 +- tools/rkimage.c | 2 +- tools/rksd.c | 6 +- tools/rkspi.c | 6 +- 53 files changed, 4222 insertions(+), 376 deletions(-) create mode 100644 arch/arm/dts/rk3036-sdk.dts create mode 100644 arch/arm/dts/rk3036.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/timer.h create mode 100644 arch/arm/include/asm/arch-rockchip/uart.h delete mode 100644 arch/arm/mach-rockchip/board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3036-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3036/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3036/Makefile create mode 100644 arch/arm/mach-rockchip/rk3036/reset_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3036/save_boot_param.S create mode 100644 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3036/syscon_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3288-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk_early_print.c create mode 100644 arch/arm/mach-rockchip/rk_timer.c create mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644 board/evb_rk3036/evb_rk3036/evb_rk3036.c create mode 100644 configs/evb-rk3036_defconfig create mode 100644 drivers/clk/clk_rk3036.c create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c create mode 100644 include/configs/evb_rk3036.h create mode 100644 include/configs/rk3036_common.h create mode 100644 include/dt-bindings/clock/rk3036-cru.h
Quoted 3 lines
--
1.9.1
Everything looks good except patch 15 which I think needs a few tweaks. Can you please take a look? Either you could send a new version of just that patch, or I can fix it up when applying it.
It would be good to get this applied this week if possible.
Regards,
Simon
v6 cover Bring up rk3036 uboot
Hi Simon,
Quoted 120 lines · Simon Glass
Hi Lin,
Quoted 117 lines · Lin Huang
This series patch bring up rk3036 uboot, since rk3036 only 4K size SRAM for SPL, so in SPL stage only support timer, uart, sdram driver, and back to bootrom when finish ddr initial, and boot up second stage from bootrom.You can boot to command line(mmc info etc) for now use this patchset.
Jeffy Chen (2):
rockchip: Add max spl size & spl header configs
rockchip: Add support for rk's second level loaderLin Huang (21):
rockchip: add timer driver
rockchip: moveSYS_MALLOC_F_LENto rk3288 ownKconfig
rockchip: renameboard-spl.ctork3288-board-spl.c
rockchip: add config decide whether to buildcommon.c
dm: core: Add SPLKconfigfor REGMAP and SYSCON
rockchip: serial driver support rk3036
rockchip: Bring in RK3036 device tree file includes and bindings
rockchip: rk3036: Add clock driver
rockchip: rk3036: Add header files for GRF
rockchip: rk3036: Add Soc reset driver
rockchip: rk3036: Add a simple syscon driver
rockchip: rk3036: Add pinctrl driver
mmc:dw_mmc: move data transfer as a separate function
mmc:dw_mmc: support fifo mode in dwc mmc driver
rockchip: mmc: use non-removable property to disginguish emmc and
sdcard register
rockchip: mmc: get the fifo mode and fifo depth property from dts
rockchip: add early uart driver
rockchip: add rk3036 sdram driver
rockchip: rk3036: Add core Soc start-up code
rockchip: Add basic support for evb-rk3036 board
rockchip: doc: show packet rk3036 uboot imagearch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3036-sdk.dts | 46 ++ arch/arm/dts/rk3036.dtsi | 428 ++++++++++++ arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 168 +++++ arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 ++++++++++++++ arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 ++++++++++ arch/arm/include/asm/arch-rockchip/timer.h | 22 + arch/arm/include/asm/arch-rockchip/uart.h | 44 ++ arch/arm/mach-rockchip/Kconfig | 28 +- arch/arm/mach-rockchip/Makefile | 10 +- arch/arm/mach-rockchip/board-spl.c | 294 --------- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 55 ++ arch/arm/mach-rockchip/rk3036/Kconfig | 23 + arch/arm/mach-rockchip/rk3036/Makefile | 13 + arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++ arch/arm/mach-rockchip/rk3036/save_boot_param.S | 32 + arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 764 ++++++++++++++++++++++ arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 + arch/arm/mach-rockchip/rk3288-board-spl.c | 277 ++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 9 + arch/arm/mach-rockchip/rk_early_print.c | 63 ++ arch/arm/mach-rockchip/rk_timer.c | 48 ++ board/evb_rk3036/evb_rk3036/Kconfig | 15 + board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 + board/evb_rk3036/evb_rk3036/evb_rk3036.c | 49 ++ configs/chromebook_jerry_defconfig | 2 + configs/evb-rk3036_defconfig | 26 + configs/firefly-rk3288_defconfig | 2 + configs/sandbox_defconfig | 2 + doc/README.rockchip | 11 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 414 ++++++++++++ drivers/core/Kconfig | 19 + drivers/core/Makefile | 4 +- drivers/mmc/dw_mmc.c | 140 ++-- drivers/mmc/rockchip_dw_mmc.c | 27 +- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++ drivers/serial/serial_rockchip.c | 1 + include/configs/evb_rk3036.h | 12 + include/configs/rk3036_common.h | 103 +++ include/configs/rk3288_common.h | 8 +- include/dt-bindings/clock/rk3036-cru.h | 186 ++++++ include/dwmmc.h | 5 + tools/Makefile | 6 + tools/rkcommon.c | 26 +- tools/rkcommon.h | 4 +- tools/rkimage.c | 2 +- tools/rksd.c | 6 +- tools/rkspi.c | 6 +- 53 files changed, 4222 insertions(+), 376 deletions(-)create mode 100644
arch/arm/dts/rk3036-sdk.dts
create mode 100644arch/arm/dts/rk3036.dtsi
create mode 100644arch/arm/include/asm/arch-rockchip/cru_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/grf_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/sdram_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/timer.hcreate mode 100644arch/arm/include/asm/arch-rockchip/uart.hdelete mode 100644arch/arm/mach-rockchip/board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk3036-board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk3036/Kconfigcreate mode 100644arch/arm/mach-rockchip/rk3036/Makefilecreate mode 100644arch/arm/mach-rockchip/rk3036/reset_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3036/save_boot_param.Screate mode 100644arch/arm/mach-rockchip/rk3036/sdram_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3036/syscon_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3288-board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk_early_print.ccreate mode 100644arch/arm/mach-rockchip/rk_timer.ccreate mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644board/evb_rk3036/evb_rk3036/evb_rk3036.ccreate mode 100644 configs/evb-rk3036_defconfig
create mode 100644drivers/clk/clk_rk3036.c
create mode 100644drivers/pinctrl/rockchip/pinctrl_rk3036.ccreate mode 100644include/configs/evb_rk3036.h
create mode 100644include/configs/rk3036_common.h
create mode 100644include/dt-bindings/clock/rk3036-cru.h
Quoted 8 lines
Quoted 3 lines
--
1.9.1Everything looks good except patch 15 which I think needs a few tweaks. Can you please take a look? Either you could send a new version of just that patch, or I can fix it up when applying it.
It would be good to get this applied this week if possible.
I will update patch 15 and upload new version today, thank you.
Quoted 6 lines
Regards,
Simon
Signature · 1 line
Lin Huang
v6 cover Bring up rk3036 uboot
Hi Lin,
Quoted 131 lines · hl
Hi Simon,
Quoted 125 lines · Simon Glass
Hi Lin,
Quoted 121 lines · Lin Huang
This series patch bring up rk3036 uboot, since rk3036 only 4K size SRAM for SPL, so in SPL stage only support timer, uart, sdram driver, and back to bootrom when finish ddr initial, and boot up second stage from bootrom.You can boot to command line(mmc info etc) for now use this patchset.
Jeffy Chen (2):
rockchip: Add max spl size & spl header configs
rockchip: Add support for rk's second level loaderLin Huang (21):
rockchip: add timer driver
rockchip: moveSYS_MALLOC_F_LENto rk3288 ownKconfig
rockchip: renameboard-spl.ctork3288-board-spl.c
rockchip: add config decide whether to buildcommon.c
dm: core: Add SPLKconfigfor REGMAP and SYSCON
rockchip: serial driver support rk3036
rockchip: Bring in RK3036 device tree file includes and bindings
rockchip: rk3036: Add clock driver
rockchip: rk3036: Add header files for GRF
rockchip: rk3036: Add Soc reset driver
rockchip: rk3036: Add a simple syscon driver
rockchip: rk3036: Add pinctrl driver
mmc:dw_mmc: move data transfer as a separate function
mmc:dw_mmc: support fifo mode in dwc mmc driver
rockchip: mmc: use non-removable property to disginguish emmc and
sdcard register
rockchip: mmc: get the fifo mode and fifo depth property from dts
rockchip: add early uart driver
rockchip: add rk3036 sdram driver
rockchip: rk3036: Add core Soc start-up code
rockchip: Add basic support for evb-rk3036 board
rockchip: doc: show packet rk3036 uboot imagearch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3036-sdk.dts | 46 ++ arch/arm/dts/rk3036.dtsi | 428 ++++++++++++ arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 168 +++++ arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 ++++++++++++++ arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 ++++++++++ arch/arm/include/asm/arch-rockchip/timer.h | 22 + arch/arm/include/asm/arch-rockchip/uart.h | 44 ++ arch/arm/mach-rockchip/Kconfig | 28 +- arch/arm/mach-rockchip/Makefile | 10 +- arch/arm/mach-rockchip/board-spl.c | 294 --------- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 55 ++ arch/arm/mach-rockchip/rk3036/Kconfig | 23 + arch/arm/mach-rockchip/rk3036/Makefile | 13 + arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++ arch/arm/mach-rockchip/rk3036/save_boot_param.S | 32 + arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 764 ++++++++++++++++++++++ arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 + arch/arm/mach-rockchip/rk3288-board-spl.c | 277 ++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 9 + arch/arm/mach-rockchip/rk_early_print.c | 63 ++ arch/arm/mach-rockchip/rk_timer.c | 48 ++ board/evb_rk3036/evb_rk3036/Kconfig | 15 + board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 + board/evb_rk3036/evb_rk3036/evb_rk3036.c | 49 ++ configs/chromebook_jerry_defconfig | 2 + configs/evb-rk3036_defconfig | 26 + configs/firefly-rk3288_defconfig | 2 + configs/sandbox_defconfig | 2 + doc/README.rockchip | 11 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 414 ++++++++++++ drivers/core/Kconfig | 19 + drivers/core/Makefile | 4 +- drivers/mmc/dw_mmc.c | 140 ++-- drivers/mmc/rockchip_dw_mmc.c | 27 +- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++ drivers/serial/serial_rockchip.c | 1 + include/configs/evb_rk3036.h | 12 + include/configs/rk3036_common.h | 103 +++ include/configs/rk3288_common.h | 8 +- include/dt-bindings/clock/rk3036-cru.h | 186 ++++++ include/dwmmc.h | 5 + tools/Makefile | 6 + tools/rkcommon.c | 26 +- tools/rkcommon.h | 4 +- tools/rkimage.c | 2 +- tools/rksd.c | 6 +- tools/rkspi.c | 6 +- 53 files changed, 4222 insertions(+), 376 deletions(-)create mode 100644
arch/arm/dts/rk3036-sdk.dts
create mode 100644arch/arm/dts/rk3036.dtsi
create mode 100644arch/arm/include/asm/arch-rockchip/cru_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/grf_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/sdram_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/timer.hcreate mode 100644arch/arm/include/asm/arch-rockchip/uart.hdelete mode 100644arch/arm/mach-rockchip/board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk3036-board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk3036/Kconfigcreate mode 100644arch/arm/mach-rockchip/rk3036/Makefilecreate mode 100644arch/arm/mach-rockchip/rk3036/reset_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3036/save_boot_param.Screate mode 100644arch/arm/mach-rockchip/rk3036/sdram_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3036/syscon_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3288-board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk_early_print.ccreate mode 100644arch/arm/mach-rockchip/rk_timer.ccreate mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644board/evb_rk3036/evb_rk3036/evb_rk3036.ccreate mode 100644 configs/evb-rk3036_defconfig
create mode 100644drivers/clk/clk_rk3036.c
create mode 100644drivers/pinctrl/rockchip/pinctrl_rk3036.ccreate mode 100644include/configs/evb_rk3036.h
create mode 100644include/configs/rk3036_common.h
create mode 100644include/dt-bindings/clock/rk3036-cru.h--
1.9.1
Quoted 7 lines
Quoted 5 lines
Everything looks good except patch 15 which I think needs a few tweaks. Can you please take a look? Either you could send a new version of just that patch, or I can fix it up when applying it.
It would be good to get this applied this week if possible.
I will update patch 15 and upload new version today, thank you.
A few more problems....I've had to update two of the patches. I'll resend them to the list and have pushed everything to u-boot-rockchip/testing. Please take a look and let me know if there are any problems. Otherwise I'll push to master tomorrow or Friday.
Regards,
Simon
v6 cover Bring up rk3036 uboot
Hi Simon,
Quoted 136 lines · Simon Glass
Hi Lin,
Quoted 132 lines · hl
Hi Simon,
Quoted 127 lines · Simon Glass
Hi Lin,
Quoted 117 lines · Lin Huang
This series patch bring up rk3036 uboot, since rk3036 only 4K size SRAM for SPL, so in SPL stage only support timer, uart, sdram driver, and back to bootrom when finish ddr initial, and boot up second stage from bootrom.You can boot to command line(mmc info etc) for now use this patchset.
Jeffy Chen (2):
rockchip: Add max spl size & spl header configs
rockchip: Add support for rk's second level loaderLin Huang (21):
rockchip: add timer driver
rockchip: moveSYS_MALLOC_F_LENto rk3288 ownKconfig
rockchip: renameboard-spl.ctork3288-board-spl.c
rockchip: add config decide whether to buildcommon.c
dm: core: Add SPLKconfigfor REGMAP and SYSCON
rockchip: serial driver support rk3036
rockchip: Bring in RK3036 device tree file includes and bindings
rockchip: rk3036: Add clock driver
rockchip: rk3036: Add header files for GRF
rockchip: rk3036: Add Soc reset driver
rockchip: rk3036: Add a simple syscon driver
rockchip: rk3036: Add pinctrl driver
mmc:dw_mmc: move data transfer as a separate function
mmc:dw_mmc: support fifo mode in dwc mmc driver
rockchip: mmc: use non-removable property to disginguish emmc and
sdcard register
rockchip: mmc: get the fifo mode and fifo depth property from dts
rockchip: add early uart driver
rockchip: add rk3036 sdram driver
rockchip: rk3036: Add core Soc start-up code
rockchip: Add basic support for evb-rk3036 board
rockchip: doc: show packet rk3036 uboot imagearch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3036-sdk.dts | 46 ++ arch/arm/dts/rk3036.dtsi | 428 ++++++++++++ arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 168 +++++ arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 ++++++++++++++ arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 ++++++++++ arch/arm/include/asm/arch-rockchip/timer.h | 22 + arch/arm/include/asm/arch-rockchip/uart.h | 44 ++ arch/arm/mach-rockchip/Kconfig | 28 +- arch/arm/mach-rockchip/Makefile | 10 +- arch/arm/mach-rockchip/board-spl.c | 294 --------- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 55 ++ arch/arm/mach-rockchip/rk3036/Kconfig | 23 + arch/arm/mach-rockchip/rk3036/Makefile | 13 + arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++ arch/arm/mach-rockchip/rk3036/save_boot_param.S | 32 + arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 764 ++++++++++++++++++++++ arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 + arch/arm/mach-rockchip/rk3288-board-spl.c | 277 ++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 9 + arch/arm/mach-rockchip/rk_early_print.c | 63 ++ arch/arm/mach-rockchip/rk_timer.c | 48 ++ board/evb_rk3036/evb_rk3036/Kconfig | 15 + board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 + board/evb_rk3036/evb_rk3036/evb_rk3036.c | 49 ++ configs/chromebook_jerry_defconfig | 2 + configs/evb-rk3036_defconfig | 26 + configs/firefly-rk3288_defconfig | 2 + configs/sandbox_defconfig | 2 + doc/README.rockchip | 11 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 414 ++++++++++++ drivers/core/Kconfig | 19 + drivers/core/Makefile | 4 +- drivers/mmc/dw_mmc.c | 140 ++-- drivers/mmc/rockchip_dw_mmc.c | 27 +- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++ drivers/serial/serial_rockchip.c | 1 + include/configs/evb_rk3036.h | 12 + include/configs/rk3036_common.h | 103 +++ include/configs/rk3288_common.h | 8 +- include/dt-bindings/clock/rk3036-cru.h | 186 ++++++ include/dwmmc.h | 5 + tools/Makefile | 6 + tools/rkcommon.c | 26 +- tools/rkcommon.h | 4 +- tools/rkimage.c | 2 +- tools/rksd.c | 6 +- tools/rkspi.c | 6 +- 53 files changed, 4222 insertions(+), 376 deletions(-)create mode 100644
arch/arm/dts/rk3036-sdk.dts
create mode 100644arch/arm/dts/rk3036.dtsi
create mode 100644arch/arm/include/asm/arch-rockchip/cru_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/grf_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/sdram_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/timer.hcreate mode 100644arch/arm/include/asm/arch-rockchip/uart.hdelete mode 100644arch/arm/mach-rockchip/board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk3036-board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk3036/Kconfigcreate mode 100644arch/arm/mach-rockchip/rk3036/Makefilecreate mode 100644arch/arm/mach-rockchip/rk3036/reset_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3036/save_boot_param.Screate mode 100644arch/arm/mach-rockchip/rk3036/sdram_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3036/syscon_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3288-board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk_early_print.ccreate mode 100644arch/arm/mach-rockchip/rk_timer.ccreate mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644board/evb_rk3036/evb_rk3036/evb_rk3036.ccreate mode 100644 configs/evb-rk3036_defconfig
create mode 100644drivers/clk/clk_rk3036.c
create mode 100644drivers/pinctrl/rockchip/pinctrl_rk3036.ccreate mode 100644include/configs/evb_rk3036.h
create mode 100644include/configs/rk3036_common.h
create mode 100644include/dt-bindings/clock/rk3036-cru.hQuoted 3 lines
--
1.9.1Everything looks good except patch 15 which I think needs a few tweaks. Can you please take a look? Either you could send a new version of just that patch, or I can fix it up when applying it.
Quoted 6 lines
Quoted 2 lines
Quoted 1 line
It would be good to get this applied this week if possible.
I will update patch 15 and upload new version today, thank you.
A few more problems....I've had to update two of the patches. I'll resend them to the list and have pushed everything to u-boot-rockchip/testing. Please take a look and let me know if there are any problems. Otherwise I'll push to master tomorrow or Friday.
Thank you for your updating, i have download the latest code and test, it can work, there is not problem. Thanks again.
Quoted 6 lines
Regards,
Simon
Signature · 1 line
Lin Huang
v6 cover Bring up rk3036 uboot
+Tom
Hi Lin,
Quoted 151 lines · hl
Hi Simon,
Quoted 146 lines · Simon Glass
Hi Lin,
Quoted 140 lines · hl
Hi Simon,
Quoted 124 lines · Simon Glass
Hi Lin,
Quoted 120 lines · Lin Huang
This series patch bring up rk3036 uboot, since rk3036 only 4K size SRAM for SPL, so in SPL stage only support timer, uart, sdram driver, and back to bootrom when finish ddr initial, and boot up second stage from bootrom.You can boot to command line(mmc info etc) for now use this patchset.
Jeffy Chen (2):
rockchip: Add max spl size & spl header configs
rockchip: Add support for rk's second level loaderLin Huang (21):
rockchip: add timer driver
rockchip: moveSYS_MALLOC_F_LENto rk3288 ownKconfig
rockchip: renameboard-spl.ctork3288-board-spl.c
rockchip: add config decide whether to buildcommon.c
dm: core: Add SPLKconfigfor REGMAP and SYSCON
rockchip: serial driver support rk3036
rockchip: Bring in RK3036 device tree file includes and bindings
rockchip: rk3036: Add clock driver
rockchip: rk3036: Add header files for GRF
rockchip: rk3036: Add Soc reset driver
rockchip: rk3036: Add a simple syscon driver
rockchip: rk3036: Add pinctrl driver
mmc:dw_mmc: move data transfer as a separate function
mmc:dw_mmc: support fifo mode in dwc mmc driver
rockchip: mmc: use non-removable property to disginguish emmc and
sdcard register
rockchip: mmc: get the fifo mode and fifo depth property from dts
rockchip: add early uart driver
rockchip: add rk3036 sdram driver
rockchip: rk3036: Add core Soc start-up code
rockchip: Add basic support for evb-rk3036 board
rockchip: doc: show packet rk3036 uboot imagearch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3036-sdk.dts | 46 ++ arch/arm/dts/rk3036.dtsi | 428 ++++++++++++ arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 168 +++++ arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 ++++++++++++++ arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 ++++++++++ arch/arm/include/asm/arch-rockchip/timer.h | 22 + arch/arm/include/asm/arch-rockchip/uart.h | 44 ++ arch/arm/mach-rockchip/Kconfig | 28 +- arch/arm/mach-rockchip/Makefile | 10 +- arch/arm/mach-rockchip/board-spl.c | 294 --------- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 55 ++ arch/arm/mach-rockchip/rk3036/Kconfig | 23 + arch/arm/mach-rockchip/rk3036/Makefile | 13 + arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++ arch/arm/mach-rockchip/rk3036/save_boot_param.S | 32 + arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 764 ++++++++++++++++++++++ arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 + arch/arm/mach-rockchip/rk3288-board-spl.c | 277 ++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 9 + arch/arm/mach-rockchip/rk_early_print.c | 63 ++ arch/arm/mach-rockchip/rk_timer.c | 48 ++ board/evb_rk3036/evb_rk3036/Kconfig | 15 + board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 + board/evb_rk3036/evb_rk3036/evb_rk3036.c | 49 ++ configs/chromebook_jerry_defconfig | 2 + configs/evb-rk3036_defconfig | 26 + configs/firefly-rk3288_defconfig | 2 + configs/sandbox_defconfig | 2 + doc/README.rockchip | 11 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 414 ++++++++++++ drivers/core/Kconfig | 19 + drivers/core/Makefile | 4 +- drivers/mmc/dw_mmc.c | 140 ++-- drivers/mmc/rockchip_dw_mmc.c | 27 +- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++ drivers/serial/serial_rockchip.c | 1 + include/configs/evb_rk3036.h | 12 + include/configs/rk3036_common.h | 103 +++ include/configs/rk3288_common.h | 8 +- include/dt-bindings/clock/rk3036-cru.h | 186 ++++++ include/dwmmc.h | 5 + tools/Makefile | 6 + tools/rkcommon.c | 26 +- tools/rkcommon.h | 4 +- tools/rkimage.c | 2 +- tools/rksd.c | 6 +- tools/rkspi.c | 6 +- 53 files changed, 4222 insertions(+), 376 deletions(-)create mode 100644
arch/arm/dts/rk3036-sdk.dts
create mode 100644arch/arm/dts/rk3036.dtsi
create mode 100644arch/arm/include/asm/arch-rockchip/cru_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/grf_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/sdram_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/timer.hcreate mode 100644arch/arm/include/asm/arch-rockchip/uart.hdelete mode 100644arch/arm/mach-rockchip/board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk3036-board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk3036/Kconfigcreate mode 100644arch/arm/mach-rockchip/rk3036/Makefilecreate mode 100644arch/arm/mach-rockchip/rk3036/reset_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3036/save_boot_param.Screate mode 100644arch/arm/mach-rockchip/rk3036/sdram_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3036/syscon_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3288-board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk_early_print.ccreate mode 100644arch/arm/mach-rockchip/rk_timer.ccreate mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644board/evb_rk3036/evb_rk3036/evb_rk3036.ccreate mode 100644 configs/evb-rk3036_defconfig
create mode 100644drivers/clk/clk_rk3036.c
create mode 100644drivers/pinctrl/rockchip/pinctrl_rk3036.ccreate mode 100644include/configs/evb_rk3036.h
create mode 100644include/configs/rk3036_common.h
create mode 100644include/dt-bindings/clock/rk3036-cru.hQuoted 8 lines
Quoted 3 lines
--
1.9.1Everything looks good except patch 15 which I think needs a few tweaks. Can you please take a look? Either you could send a new version of just that patch, or I can fix it up when applying it.
It would be good to get this applied this week if possible.
I will update patch 15 and upload new version today, thank you.
Quoted 8 lines
Quoted 4 lines
A few more problems....I've had to update two of the patches. I'll resend them to the list and have pushed everything to u-boot-rockchip/testing. Please take a look and let me know if there are any problems. Otherwise I'll push to master tomorrow or Friday.
Thank you for your updating, i have download the latest code and test, it can work, there is not problem. Thanks again.
OK, I have pulled this in and pushed it to master.
Two problems remain though:
1. Most important - the mkimage tool is now only built for Rockchip (a change I had to make to fix a build error) and there are two versions of it. The two Kconfig options should move to become command-line options for mkimage. These are CONFIG_ROCKCHIP_MAX_SPL_SIZE and CONFIG_ROCKCHIP_SPL_HDR. Since mkimage is a tool that is released with Linux distributions it needs to support all possible uses. We only release a single version. My suggestion is to add a command line option for mkimage to specify the Rockchip chip type rk3288, rk3066, etc.) and for the code to use the correct size/hdr automatically. You can then remove these Kconfig options.
2. As mentioned in the review, the debug UART code should use the existing debug UART feature. Do you feel comfortable looking at that? If not I could try.
Also, do you have plans to upstream support for other chips?
Quoted 5 lines
--
Lin Huang
Regards,
Simon
v6 cover Bring up rk3036 uboot
Quoted 169 lines · Simon Glass
+Tom
Hi Lin,
Quoted 151 lines · hl
Hi Simon,
Quoted 146 lines · Simon Glass
Hi Lin,
Quoted 140 lines · hl
Hi Simon,
Quoted 124 lines · Simon Glass
Hi Lin,
Quoted 120 lines · Lin Huang
This series patch bring up rk3036 uboot, since rk3036 only 4K size SRAM for SPL, so in SPL stage only support timer, uart, sdram driver, and back to bootrom when finish ddr initial, and boot up second stage from bootrom.You can boot to command line(mmc info etc) for now use this patchset.
Jeffy Chen (2):
rockchip: Add max spl size & spl header configs
rockchip: Add support for rk's second level loaderLin Huang (21):
rockchip: add timer driver
rockchip: moveSYS_MALLOC_F_LENto rk3288 ownKconfig
rockchip: renameboard-spl.ctork3288-board-spl.c
rockchip: add config decide whether to buildcommon.c
dm: core: Add SPLKconfigfor REGMAP and SYSCON
rockchip: serial driver support rk3036
rockchip: Bring in RK3036 device tree file includes and bindings
rockchip: rk3036: Add clock driver
rockchip: rk3036: Add header files for GRF
rockchip: rk3036: Add Soc reset driver
rockchip: rk3036: Add a simple syscon driver
rockchip: rk3036: Add pinctrl driver
mmc:dw_mmc: move data transfer as a separate function
mmc:dw_mmc: support fifo mode in dwc mmc driver
rockchip: mmc: use non-removable property to disginguish emmc and
sdcard register
rockchip: mmc: get the fifo mode and fifo depth property from dts
rockchip: add early uart driver
rockchip: add rk3036 sdram driver
rockchip: rk3036: Add core Soc start-up code
rockchip: Add basic support for evb-rk3036 board
rockchip: doc: show packet rk3036 uboot imagearch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3036-sdk.dts | 46 ++ arch/arm/dts/rk3036.dtsi | 428 ++++++++++++ arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 168 +++++ arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 ++++++++++++++ arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 ++++++++++ arch/arm/include/asm/arch-rockchip/timer.h | 22 + arch/arm/include/asm/arch-rockchip/uart.h | 44 ++ arch/arm/mach-rockchip/Kconfig | 28 +- arch/arm/mach-rockchip/Makefile | 10 +- arch/arm/mach-rockchip/board-spl.c | 294 --------- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 55 ++ arch/arm/mach-rockchip/rk3036/Kconfig | 23 + arch/arm/mach-rockchip/rk3036/Makefile | 13 + arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++ arch/arm/mach-rockchip/rk3036/save_boot_param.S | 32 + arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 764 ++++++++++++++++++++++ arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 + arch/arm/mach-rockchip/rk3288-board-spl.c | 277 ++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 9 + arch/arm/mach-rockchip/rk_early_print.c | 63 ++ arch/arm/mach-rockchip/rk_timer.c | 48 ++ board/evb_rk3036/evb_rk3036/Kconfig | 15 + board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 + board/evb_rk3036/evb_rk3036/evb_rk3036.c | 49 ++ configs/chromebook_jerry_defconfig | 2 + configs/evb-rk3036_defconfig | 26 + configs/firefly-rk3288_defconfig | 2 + configs/sandbox_defconfig | 2 + doc/README.rockchip | 11 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 414 ++++++++++++ drivers/core/Kconfig | 19 + drivers/core/Makefile | 4 +- drivers/mmc/dw_mmc.c | 140 ++-- drivers/mmc/rockchip_dw_mmc.c | 27 +- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++ drivers/serial/serial_rockchip.c | 1 + include/configs/evb_rk3036.h | 12 + include/configs/rk3036_common.h | 103 +++ include/configs/rk3288_common.h | 8 +- include/dt-bindings/clock/rk3036-cru.h | 186 ++++++ include/dwmmc.h | 5 + tools/Makefile | 6 + tools/rkcommon.c | 26 +- tools/rkcommon.h | 4 +- tools/rkimage.c | 2 +- tools/rksd.c | 6 +- tools/rkspi.c | 6 +- 53 files changed, 4222 insertions(+), 376 deletions(-)create mode 100644
arch/arm/dts/rk3036-sdk.dts
create mode 100644arch/arm/dts/rk3036.dtsi
create mode 100644arch/arm/include/asm/arch-rockchip/cru_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/grf_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/sdram_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/timer.hcreate mode 100644arch/arm/include/asm/arch-rockchip/uart.hdelete mode 100644arch/arm/mach-rockchip/board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk3036-board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk3036/Kconfigcreate mode 100644arch/arm/mach-rockchip/rk3036/Makefilecreate mode 100644arch/arm/mach-rockchip/rk3036/reset_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3036/save_boot_param.Screate mode 100644arch/arm/mach-rockchip/rk3036/sdram_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3036/syscon_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3288-board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk_early_print.ccreate mode 100644arch/arm/mach-rockchip/rk_timer.ccreate mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644board/evb_rk3036/evb_rk3036/evb_rk3036.ccreate mode 100644 configs/evb-rk3036_defconfig
create mode 100644drivers/clk/clk_rk3036.c
create mode 100644drivers/pinctrl/rockchip/pinctrl_rk3036.ccreate mode 100644include/configs/evb_rk3036.h
create mode 100644include/configs/rk3036_common.h
create mode 100644include/dt-bindings/clock/rk3036-cru.hQuoted 8 lines
Quoted 3 lines
--
1.9.1Everything looks good except patch 15 which I think needs a few tweaks. Can you please take a look? Either you could send a new version of just that patch, or I can fix it up when applying it.
It would be good to get this applied this week if possible.
I will update patch 15 and upload new version today, thank you.
Quoted 8 lines
Quoted 4 lines
A few more problems....I've had to update two of the patches. I'll resend them to the list and have pushed everything to u-boot-rockchip/testing. Please take a look and let me know if there are any problems. Otherwise I'll push to master tomorrow or Friday.
Thank you for your updating, i have download the latest code and test, it can work, there is not problem. Thanks again.
OK, I have pulled this in and pushed it to master.
Two problems remain though:
Quoted 10 lines
1. Most important - the mkimage tool is now only built for Rockchip (a change I had to make to fix a build error) and there are two versions of it. The two
Kconfigoptions should move to become command-line options for mkimage. These areCONFIG_ROCKCHIP_MAX_SPL_SIZEandCONFIG_ROCKCHIP_SPL_HDR. Since mkimage is a tool that is released with Linux distributions it needs to support all possible uses. We only release a single version. My suggestion is to add a command line option for mkimage to specify the Rockchip chip type rk3288, rk3066, etc.) and for the code to use the correct size/hdr automatically. You can then remove theseKconfigoptions.
This is going to be bad for distros that try and track our rc candidates even. I would suggest making use of 'mkimage -n' to pass rk3288/rk3066/rkfuturethings to the rockchip file and sort out those things there.
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20151119/ca9991d7/attachment.sig>
v6 cover Bring up rk3036 uboot
Hi Tom,
Quoted 181 lines · Tom Rini
Quoted 169 lines · Simon Glass
+Tom
Hi Lin,
Quoted 151 lines · hl
Hi Simon,
Quoted 146 lines · Simon Glass
Hi Lin,
Quoted 140 lines · hl
Hi Simon,
Quoted 124 lines · Simon Glass
Hi Lin,
Quoted 120 lines · Lin Huang
This series patch bring up rk3036 uboot, since rk3036 only 4K size SRAM for SPL, so in SPL stage only support timer, uart, sdram driver, and back to bootrom when finish ddr initial, and boot up second stage from bootrom.You can boot to command line(mmc info etc) for now use this patchset.
Jeffy Chen (2):
rockchip: Add max spl size & spl header configs
rockchip: Add support for rk's second level loaderLin Huang (21):
rockchip: add timer driver
rockchip: moveSYS_MALLOC_F_LENto rk3288 ownKconfig
rockchip: renameboard-spl.ctork3288-board-spl.c
rockchip: add config decide whether to buildcommon.c
dm: core: Add SPLKconfigfor REGMAP and SYSCON
rockchip: serial driver support rk3036
rockchip: Bring in RK3036 device tree file includes and bindings
rockchip: rk3036: Add clock driver
rockchip: rk3036: Add header files for GRF
rockchip: rk3036: Add Soc reset driver
rockchip: rk3036: Add a simple syscon driver
rockchip: rk3036: Add pinctrl driver
mmc:dw_mmc: move data transfer as a separate function
mmc:dw_mmc: support fifo mode in dwc mmc driver
rockchip: mmc: use non-removable property to disginguish emmc and
sdcard register
rockchip: mmc: get the fifo mode and fifo depth property from dts
rockchip: add early uart driver
rockchip: add rk3036 sdram driver
rockchip: rk3036: Add core Soc start-up code
rockchip: Add basic support for evb-rk3036 board
rockchip: doc: show packet rk3036 uboot imagearch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3036-sdk.dts | 46 ++ arch/arm/dts/rk3036.dtsi | 428 ++++++++++++ arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 168 +++++ arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 ++++++++++++++ arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 ++++++++++ arch/arm/include/asm/arch-rockchip/timer.h | 22 + arch/arm/include/asm/arch-rockchip/uart.h | 44 ++ arch/arm/mach-rockchip/Kconfig | 28 +- arch/arm/mach-rockchip/Makefile | 10 +- arch/arm/mach-rockchip/board-spl.c | 294 --------- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 55 ++ arch/arm/mach-rockchip/rk3036/Kconfig | 23 + arch/arm/mach-rockchip/rk3036/Makefile | 13 + arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++ arch/arm/mach-rockchip/rk3036/save_boot_param.S | 32 + arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 764 ++++++++++++++++++++++ arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 + arch/arm/mach-rockchip/rk3288-board-spl.c | 277 ++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 9 + arch/arm/mach-rockchip/rk_early_print.c | 63 ++ arch/arm/mach-rockchip/rk_timer.c | 48 ++ board/evb_rk3036/evb_rk3036/Kconfig | 15 + board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 + board/evb_rk3036/evb_rk3036/evb_rk3036.c | 49 ++ configs/chromebook_jerry_defconfig | 2 + configs/evb-rk3036_defconfig | 26 + configs/firefly-rk3288_defconfig | 2 + configs/sandbox_defconfig | 2 + doc/README.rockchip | 11 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 414 ++++++++++++ drivers/core/Kconfig | 19 + drivers/core/Makefile | 4 +- drivers/mmc/dw_mmc.c | 140 ++-- drivers/mmc/rockchip_dw_mmc.c | 27 +- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++ drivers/serial/serial_rockchip.c | 1 + include/configs/evb_rk3036.h | 12 + include/configs/rk3036_common.h | 103 +++ include/configs/rk3288_common.h | 8 +- include/dt-bindings/clock/rk3036-cru.h | 186 ++++++ include/dwmmc.h | 5 + tools/Makefile | 6 + tools/rkcommon.c | 26 +- tools/rkcommon.h | 4 +- tools/rkimage.c | 2 +- tools/rksd.c | 6 +- tools/rkspi.c | 6 +- 53 files changed, 4222 insertions(+), 376 deletions(-)create mode 100644
arch/arm/dts/rk3036-sdk.dts
create mode 100644arch/arm/dts/rk3036.dtsi
create mode 100644arch/arm/include/asm/arch-rockchip/cru_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/grf_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/sdram_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/timer.hcreate mode 100644arch/arm/include/asm/arch-rockchip/uart.hdelete mode 100644arch/arm/mach-rockchip/board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk3036-board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk3036/Kconfigcreate mode 100644arch/arm/mach-rockchip/rk3036/Makefilecreate mode 100644arch/arm/mach-rockchip/rk3036/reset_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3036/save_boot_param.Screate mode 100644arch/arm/mach-rockchip/rk3036/sdram_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3036/syscon_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3288-board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk_early_print.ccreate mode 100644arch/arm/mach-rockchip/rk_timer.ccreate mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644board/evb_rk3036/evb_rk3036/evb_rk3036.ccreate mode 100644 configs/evb-rk3036_defconfig
create mode 100644drivers/clk/clk_rk3036.c
create mode 100644drivers/pinctrl/rockchip/pinctrl_rk3036.ccreate mode 100644include/configs/evb_rk3036.h
create mode 100644include/configs/rk3036_common.h
create mode 100644include/dt-bindings/clock/rk3036-cru.hQuoted 8 lines
Quoted 3 lines
--
1.9.1Everything looks good except patch 15 which I think needs a few tweaks. Can you please take a look? Either you could send a new version of just that patch, or I can fix it up when applying it.
It would be good to get this applied this week if possible.
I will update patch 15 and upload new version today, thank you.
Quoted 8 lines
Quoted 4 lines
A few more problems....I've had to update two of the patches. I'll resend them to the list and have pushed everything to u-boot-rockchip/testing. Please take a look and let me know if there are any problems. Otherwise I'll push to master tomorrow or Friday.
Thank you for your updating, i have download the latest code and test, it can work, there is not problem. Thanks again.
OK, I have pulled this in and pushed it to master.
Two problems remain though:
Quoted 10 lines
1. Most important - the mkimage tool is now only built for Rockchip (a change I had to make to fix a build error) and there are two versions of it. The two
Kconfigoptions should move to become command-line options for mkimage. These areCONFIG_ROCKCHIP_MAX_SPL_SIZEandCONFIG_ROCKCHIP_SPL_HDR. Since mkimage is a tool that is released with Linux distributions it needs to support all possible uses. We only release a single version. My suggestion is to add a command line option for mkimage to specify the Rockchip chip type rk3288, rk3066, etc.) and for the code to use the correct size/hdr automatically. You can then remove theseKconfigoptions.
Quoted 4 lines
This is going to be bad for distros that try and track our rc candidates even. I would suggest making use of 'mkimage -n' to pass rk3288/rk3066/rkfuturethings to the rockchip file and sort out those things there.
If you like I can hold off on the pull request until this is sorted out. But in that case can you please apply this one?
http://patchwork.ozlabs.org/patch/544969/
Lin, are you able to get a patch out quickly? If we can apply this next week then it will not affect RC2.
Regards,
Simon
v6 cover Bring up rk3036 uboot
Quoted 189 lines · Simon Glass
Hi Tom,
Quoted 181 lines · Tom Rini
Quoted 169 lines · Simon Glass
+Tom
Hi Lin,
Quoted 151 lines · hl
Hi Simon,
Quoted 146 lines · Simon Glass
Hi Lin,
Quoted 140 lines · hl
Hi Simon,
Quoted 124 lines · Simon Glass
Hi Lin,
Quoted 120 lines · Lin Huang
This series patch bring up rk3036 uboot, since rk3036 only 4K size SRAM for SPL, so in SPL stage only support timer, uart, sdram driver, and back to bootrom when finish ddr initial, and boot up second stage from bootrom.You can boot to command line(mmc info etc) for now use this patchset.
Jeffy Chen (2):
rockchip: Add max spl size & spl header configs
rockchip: Add support for rk's second level loaderLin Huang (21):
rockchip: add timer driver
rockchip: moveSYS_MALLOC_F_LENto rk3288 ownKconfig
rockchip: renameboard-spl.ctork3288-board-spl.c
rockchip: add config decide whether to buildcommon.c
dm: core: Add SPLKconfigfor REGMAP and SYSCON
rockchip: serial driver support rk3036
rockchip: Bring in RK3036 device tree file includes and bindings
rockchip: rk3036: Add clock driver
rockchip: rk3036: Add header files for GRF
rockchip: rk3036: Add Soc reset driver
rockchip: rk3036: Add a simple syscon driver
rockchip: rk3036: Add pinctrl driver
mmc:dw_mmc: move data transfer as a separate function
mmc:dw_mmc: support fifo mode in dwc mmc driver
rockchip: mmc: use non-removable property to disginguish emmc and
sdcard register
rockchip: mmc: get the fifo mode and fifo depth property from dts
rockchip: add early uart driver
rockchip: add rk3036 sdram driver
rockchip: rk3036: Add core Soc start-up code
rockchip: Add basic support for evb-rk3036 board
rockchip: doc: show packet rk3036 uboot imagearch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3036-sdk.dts | 46 ++ arch/arm/dts/rk3036.dtsi | 428 ++++++++++++ arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 168 +++++ arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 ++++++++++++++ arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 ++++++++++ arch/arm/include/asm/arch-rockchip/timer.h | 22 + arch/arm/include/asm/arch-rockchip/uart.h | 44 ++ arch/arm/mach-rockchip/Kconfig | 28 +- arch/arm/mach-rockchip/Makefile | 10 +- arch/arm/mach-rockchip/board-spl.c | 294 --------- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 55 ++ arch/arm/mach-rockchip/rk3036/Kconfig | 23 + arch/arm/mach-rockchip/rk3036/Makefile | 13 + arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++ arch/arm/mach-rockchip/rk3036/save_boot_param.S | 32 + arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 764 ++++++++++++++++++++++ arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 + arch/arm/mach-rockchip/rk3288-board-spl.c | 277 ++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 9 + arch/arm/mach-rockchip/rk_early_print.c | 63 ++ arch/arm/mach-rockchip/rk_timer.c | 48 ++ board/evb_rk3036/evb_rk3036/Kconfig | 15 + board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 + board/evb_rk3036/evb_rk3036/evb_rk3036.c | 49 ++ configs/chromebook_jerry_defconfig | 2 + configs/evb-rk3036_defconfig | 26 + configs/firefly-rk3288_defconfig | 2 + configs/sandbox_defconfig | 2 + doc/README.rockchip | 11 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 414 ++++++++++++ drivers/core/Kconfig | 19 + drivers/core/Makefile | 4 +- drivers/mmc/dw_mmc.c | 140 ++-- drivers/mmc/rockchip_dw_mmc.c | 27 +- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++ drivers/serial/serial_rockchip.c | 1 + include/configs/evb_rk3036.h | 12 + include/configs/rk3036_common.h | 103 +++ include/configs/rk3288_common.h | 8 +- include/dt-bindings/clock/rk3036-cru.h | 186 ++++++ include/dwmmc.h | 5 + tools/Makefile | 6 + tools/rkcommon.c | 26 +- tools/rkcommon.h | 4 +- tools/rkimage.c | 2 +- tools/rksd.c | 6 +- tools/rkspi.c | 6 +- 53 files changed, 4222 insertions(+), 376 deletions(-)create mode 100644
arch/arm/dts/rk3036-sdk.dts
create mode 100644arch/arm/dts/rk3036.dtsi
create mode 100644arch/arm/include/asm/arch-rockchip/cru_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/grf_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/sdram_rk3036.hcreate mode 100644arch/arm/include/asm/arch-rockchip/timer.hcreate mode 100644arch/arm/include/asm/arch-rockchip/uart.hdelete mode 100644arch/arm/mach-rockchip/board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk3036-board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk3036/Kconfigcreate mode 100644arch/arm/mach-rockchip/rk3036/Makefilecreate mode 100644arch/arm/mach-rockchip/rk3036/reset_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3036/save_boot_param.Screate mode 100644arch/arm/mach-rockchip/rk3036/sdram_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3036/syscon_rk3036.ccreate mode 100644arch/arm/mach-rockchip/rk3288-board-spl.ccreate mode 100644arch/arm/mach-rockchip/rk_early_print.ccreate mode 100644arch/arm/mach-rockchip/rk_timer.ccreate mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644board/evb_rk3036/evb_rk3036/evb_rk3036.ccreate mode 100644 configs/evb-rk3036_defconfig
create mode 100644drivers/clk/clk_rk3036.c
create mode 100644drivers/pinctrl/rockchip/pinctrl_rk3036.ccreate mode 100644include/configs/evb_rk3036.h
create mode 100644include/configs/rk3036_common.h
create mode 100644include/dt-bindings/clock/rk3036-cru.hQuoted 8 lines
Quoted 3 lines
--
1.9.1Everything looks good except patch 15 which I think needs a few tweaks. Can you please take a look? Either you could send a new version of just that patch, or I can fix it up when applying it.
It would be good to get this applied this week if possible.
I will update patch 15 and upload new version today, thank you.
Quoted 8 lines
Quoted 4 lines
A few more problems....I've had to update two of the patches. I'll resend them to the list and have pushed everything to u-boot-rockchip/testing. Please take a look and let me know if there are any problems. Otherwise I'll push to master tomorrow or Friday.
Thank you for your updating, i have download the latest code and test, it can work, there is not problem. Thanks again.
OK, I have pulled this in and pushed it to master.
Two problems remain though:
Quoted 10 lines
1. Most important - the mkimage tool is now only built for Rockchip (a change I had to make to fix a build error) and there are two versions of it. The two
Kconfigoptions should move to become command-line options for mkimage. These areCONFIG_ROCKCHIP_MAX_SPL_SIZEandCONFIG_ROCKCHIP_SPL_HDR. Since mkimage is a tool that is released with Linux distributions it needs to support all possible uses. We only release a single version. My suggestion is to add a command line option for mkimage to specify the Rockchip chip type rk3288, rk3066, etc.) and for the code to use the correct size/hdr automatically. You can then remove theseKconfigoptions.Quoted 4 lines
This is going to be bad for distros that try and track our rc candidates even. I would suggest making use of 'mkimage -n' to pass rk3288/rk3066/rkfuturethings to the rockchip file and sort out those things there.
Quoted 4 lines
If you like I can hold off on the pull request until this is sorted out. But in that case can you please apply this one?
Yes I want to hold off, it'd be a bad thing to introduce for a short while I think. Patch applied.
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20151119/ee8e29a0/attachment.sig>
v6 cover Bring up rk3036 uboot
In reply to Simon GlassHi Simon,
Quoted 179 lines · Simon Glass
Hi Tom,
Quoted 172 lines · Tom Rini
Quoted 161 lines · Simon Glass
+Tom
Hi Lin,
Quoted 143 lines · hl
Hi Simon,
Quoted 138 lines · Simon Glass
Hi Lin,
Quoted 134 lines · hl
Hi Simon,
Quoted 129 lines · Simon Glass
Hi Lin,
Quoted 119 lines · Lin Huang
This series patch bring up rk3036 uboot, since rk3036 only 4K size SRAM for SPL, so in SPL stage only support timer, uart, sdram driver, and back to bootrom when finish ddr initial, and boot up second stage from bootrom.You can boot to command line(mmc info etc) for now use this patchset.
Jeffy Chen (2):
rockchip: Add max spl size & spl header configs
rockchip: Add support for rk's second level loaderLin Huang (21):
rockchip: add timer driver
rockchip: moveSYS_MALLOC_F_LENto rk3288 ownKconfig
rockchip: renameboard-spl.ctork3288-board-spl.c
rockchip: add config decide whether to buildcommon.c
dm: core: Add SPLKconfigfor REGMAP and SYSCON
rockchip: serial driver support rk3036
rockchip: Bring in RK3036 device tree file includes and bindings
rockchip: rk3036: Add clock driver
rockchip: rk3036: Add header files for GRF
rockchip: rk3036: Add Soc reset driver
rockchip: rk3036: Add a simple syscon driver
rockchip: rk3036: Add pinctrl driver
mmc:dw_mmc: move data transfer as a separate function
mmc:dw_mmc: support fifo mode in dwc mmc driver
rockchip: mmc: use non-removable property to disginguish emmc and
sdcard register
rockchip: mmc: get the fifo mode and fifo depth property from dts
rockchip: add early uart driver
rockchip: add rk3036 sdram driver
rockchip: rk3036: Add core Soc start-up code
rockchip: Add basic support for evb-rk3036 board
rockchip: doc: show packet rk3036 uboot image
arch/arm/dts/Makefile| 3 +-
arch/arm/dts/rk3036-sdk.dts| 46 ++
arch/arm/dts/rk3036.dtsi| 428 ++++++++++++
arch/arm/include/asm/arch-rockchip/cru_rk3036.h| 168 +++++
arch/arm/include/asm/arch-rockchip/grf_rk3036.h| 493
++++++++++++++arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 ++++++++++ arch/arm/include/asm/arch-rockchip/timer.h | 22 + arch/arm/include/asm/arch-rockchip/uart.h | 44 ++ arch/arm/mach-rockchip/Kconfig | 28 +- arch/arm/mach-rockchip/Makefile | 10 +- arch/arm/mach-rockchip/board-spl.c | 294 --------- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 55 ++ arch/arm/mach-rockchip/rk3036/Kconfig | 23 + arch/arm/mach-rockchip/rk3036/Makefile | 13 + arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++ arch/arm/mach-rockchip/rk3036/save_boot_param.S | 32 + arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 764 ++++++++++++++++++++++ arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 + arch/arm/mach-rockchip/rk3288-board-spl.c | 277 ++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 9 + arch/arm/mach-rockchip/rk_early_print.c | 63 ++ arch/arm/mach-rockchip/rk_timer.c | 48 ++ board/evb_rk3036/evb_rk3036/Kconfig | 15 + board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 + board/evb_rk3036/evb_rk3036/evb_rk3036.c | 49 ++ configs/chromebook_jerry_defconfig | 2 + configs/evb-rk3036_defconfig | 26 + configs/firefly-rk3288_defconfig | 2 + configs/sandbox_defconfig | 2 + doc/README.rockchip | 11 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 414 ++++++++++++ drivers/core/Kconfig | 19 + drivers/core/Makefile | 4 +- drivers/mmc/dw_mmc.c | 140 ++-- drivers/mmc/rockchip_dw_mmc.c | 27 +- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++ drivers/serial/serial_rockchip.c | 1 + include/configs/evb_rk3036.h | 12 + include/configs/rk3036_common.h | 103 +++ include/configs/rk3288_common.h | 8 +- include/dt-bindings/clock/rk3036-cru.h | 186 ++++++ include/dwmmc.h | 5 + tools/Makefile | 6 + tools/rkcommon.c | 26 +- tools/rkcommon.h | 4 +- tools/rkimage.c | 2 +- tools/rksd.c | 6 +- tools/rkspi.c | 6 +- 53 files changed, 4222 insertions(+), 376 deletions(-) create mode 100644 arch/arm/dts/rk3036-sdk.dts create mode 100644 arch/arm/dts/rk3036.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/timer.h create mode 100644 arch/arm/include/asm/arch-rockchip/uart.h delete mode 100644 arch/arm/mach-rockchip/board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3036-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3036/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3036/Makefile create mode 100644 arch/arm/mach-rockchip/rk3036/reset_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3036/save_boot_param.S create mode 100644 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3036/syscon_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3288-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk_early_print.c create mode 100644 arch/arm/mach-rockchip/rk_timer.c create mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644 board/evb_rk3036/evb_rk3036/evb_rk3036.c create mode 100644 configs/evb-rk3036_defconfig create mode 100644 drivers/clk/clk_rk3036.c create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c create mode 100644 include/configs/evb_rk3036.h create mode 100644 include/configs/rk3036_common.h create mode 100644 include/dt-bindings/clock/rk3036-cru.hQuoted 3 lines
--
1.9.1Everything looks good except patch 15 which I think needs a few tweaks. Can you please take a look? Either you could send a new version of just that patch, or I can fix it up when applying it.
Quoted 9 lines
Quoted 6 lines
Quoted 2 lines
Quoted 1 line
It would be good to get this applied this week if possible.
I will update patch 15 and upload new version today, thank you.
A few more problems....I've had to update two of the patches. I'll resend them to the list and have pushed everything to u-boot-rockchip/testing. Please take a look and let me know if there are any problems. Otherwise I'll push to master tomorrow or Friday.
Thank you for your updating, i have download the latest code and test, it can work, there is not problem. Thanks again.
OK, I have pulled this in and pushed it to master.
Two problems remain though:
Quoted 10 lines
1. Most important - the mkimage tool is now only built for Rockchip (a change I had to make to fix a build error) and there are two versions of it. The two
Kconfigoptions should move to become command-line options for mkimage. These areCONFIG_ROCKCHIP_MAX_SPL_SIZEandCONFIG_ROCKCHIP_SPL_HDR. Since mkimage is a tool that is released with Linux distributions it needs to support all possible uses. We only release a single version. My suggestion is to add a command line option for mkimage to specify the Rockchip chip type rk3288, rk3066, etc.) and for the code to use the correct size/hdr automatically. You can then remove theseKconfigoptions.Quoted 4 lines
This is going to be bad for distros that try and track our rc candidates even. I would suggest making use of 'mkimage -n' to pass rk3288/rk3066/rkfuturethings to the rockchip file and sort out those things there.
Quoted 7 lines
If you like I can hold off on the pull request until this is sorted out. But in that case can you please apply this one?
http://patchwork.ozlabs.org/patch/544969/
Lin, are you able to get a patch out quickly? If we can apply this next week then it will not affect RC2.
Jeffy will upload a patch today to fix it.
Quoted 6 lines
Regards,
Simon
Signature · 1 line
Lin Huang
v6 cover Bring up rk3036 uboot
In reply to Simon GlassHi Simon,
Quoted 172 lines · Simon Glass
+Tom
Hi Lin,
Quoted 143 lines · hl
Hi Simon,
Quoted 138 lines · Simon Glass
Hi Lin,
Quoted 134 lines · hl
Hi Simon,
Quoted 129 lines · Simon Glass
Hi Lin,
Quoted 119 lines · Lin Huang
This series patch bring up rk3036 uboot, since rk3036 only 4K size SRAM for SPL, so in SPL stage only support timer, uart, sdram driver, and back to bootrom when finish ddr initial, and boot up second stage from bootrom.You can boot to command line(mmc info etc) for now use this patchset.
Jeffy Chen (2):
rockchip: Add max spl size & spl header configs
rockchip: Add support for rk's second level loaderLin Huang (21):
rockchip: add timer driver
rockchip: moveSYS_MALLOC_F_LENto rk3288 ownKconfig
rockchip: renameboard-spl.ctork3288-board-spl.c
rockchip: add config decide whether to buildcommon.c
dm: core: Add SPLKconfigfor REGMAP and SYSCON
rockchip: serial driver support rk3036
rockchip: Bring in RK3036 device tree file includes and bindings
rockchip: rk3036: Add clock driver
rockchip: rk3036: Add header files for GRF
rockchip: rk3036: Add Soc reset driver
rockchip: rk3036: Add a simple syscon driver
rockchip: rk3036: Add pinctrl driver
mmc:dw_mmc: move data transfer as a separate function
mmc:dw_mmc: support fifo mode in dwc mmc driver
rockchip: mmc: use non-removable property to disginguish emmc and
sdcard register
rockchip: mmc: get the fifo mode and fifo depth property from dts
rockchip: add early uart driver
rockchip: add rk3036 sdram driver
rockchip: rk3036: Add core Soc start-up code
rockchip: Add basic support for evb-rk3036 board
rockchip: doc: show packet rk3036 uboot image
arch/arm/dts/Makefile| 3 +-
arch/arm/dts/rk3036-sdk.dts| 46 ++
arch/arm/dts/rk3036.dtsi| 428 ++++++++++++
arch/arm/include/asm/arch-rockchip/cru_rk3036.h| 168 +++++
arch/arm/include/asm/arch-rockchip/grf_rk3036.h| 493
++++++++++++++arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 ++++++++++ arch/arm/include/asm/arch-rockchip/timer.h | 22 + arch/arm/include/asm/arch-rockchip/uart.h | 44 ++ arch/arm/mach-rockchip/Kconfig | 28 +- arch/arm/mach-rockchip/Makefile | 10 +- arch/arm/mach-rockchip/board-spl.c | 294 --------- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 55 ++ arch/arm/mach-rockchip/rk3036/Kconfig | 23 + arch/arm/mach-rockchip/rk3036/Makefile | 13 + arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++ arch/arm/mach-rockchip/rk3036/save_boot_param.S | 32 + arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 764 ++++++++++++++++++++++ arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 + arch/arm/mach-rockchip/rk3288-board-spl.c | 277 ++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 9 + arch/arm/mach-rockchip/rk_early_print.c | 63 ++ arch/arm/mach-rockchip/rk_timer.c | 48 ++ board/evb_rk3036/evb_rk3036/Kconfig | 15 + board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 + board/evb_rk3036/evb_rk3036/evb_rk3036.c | 49 ++ configs/chromebook_jerry_defconfig | 2 + configs/evb-rk3036_defconfig | 26 + configs/firefly-rk3288_defconfig | 2 + configs/sandbox_defconfig | 2 + doc/README.rockchip | 11 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 414 ++++++++++++ drivers/core/Kconfig | 19 + drivers/core/Makefile | 4 +- drivers/mmc/dw_mmc.c | 140 ++-- drivers/mmc/rockchip_dw_mmc.c | 27 +- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++ drivers/serial/serial_rockchip.c | 1 + include/configs/evb_rk3036.h | 12 + include/configs/rk3036_common.h | 103 +++ include/configs/rk3288_common.h | 8 +- include/dt-bindings/clock/rk3036-cru.h | 186 ++++++ include/dwmmc.h | 5 + tools/Makefile | 6 + tools/rkcommon.c | 26 +- tools/rkcommon.h | 4 +- tools/rkimage.c | 2 +- tools/rksd.c | 6 +- tools/rkspi.c | 6 +- 53 files changed, 4222 insertions(+), 376 deletions(-) create mode 100644 arch/arm/dts/rk3036-sdk.dts create mode 100644 arch/arm/dts/rk3036.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/timer.h create mode 100644 arch/arm/include/asm/arch-rockchip/uart.h delete mode 100644 arch/arm/mach-rockchip/board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3036-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3036/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3036/Makefile create mode 100644 arch/arm/mach-rockchip/rk3036/reset_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3036/save_boot_param.S create mode 100644 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3036/syscon_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3288-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk_early_print.c create mode 100644 arch/arm/mach-rockchip/rk_timer.c create mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644 board/evb_rk3036/evb_rk3036/evb_rk3036.c create mode 100644 configs/evb-rk3036_defconfig create mode 100644 drivers/clk/clk_rk3036.c create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c create mode 100644 include/configs/evb_rk3036.h create mode 100644 include/configs/rk3036_common.h create mode 100644 include/dt-bindings/clock/rk3036-cru.hQuoted 3 lines
--
1.9.1Everything looks good except patch 15 which I think needs a few tweaks. Can you please take a look? Either you could send a new version of just that patch, or I can fix it up when applying it.
Quoted 9 lines
Quoted 6 lines
Quoted 2 lines
Quoted 1 line
It would be good to get this applied this week if possible.
I will update patch 15 and upload new version today, thank you.
A few more problems....I've had to update two of the patches. I'll resend them to the list and have pushed everything to u-boot-rockchip/testing. Please take a look and let me know if there are any problems. Otherwise I'll push to master tomorrow or Friday.
Thank you for your updating, i have download the latest code and test, it can work, there is not problem. Thanks again.
OK, I have pulled this in and pushed it to master.
Two problems remain though:
1. Most important - the mkimage tool is now only built for Rockchip (a change I had to make to fix a build error) and there are two versions of it. The two
Kconfigoptions should move to become command-line options for mkimage. These areCONFIG_ROCKCHIP_MAX_SPL_SIZEandCONFIG_ROCKCHIP_SPL_HDR. Since mkimage is a tool that is released with Linux distributions it needs to support all possible uses. We only release a single version. My suggestion is to add a command line option for mkimage to specify the Rockchip chip type rk3288, rk3066, etc.) and for the code to use the correct size/hdr automatically. You can then remove theseKconfigoptions.
Quoted 3 lines
2. As mentioned in the review, the debug UART code should use the existing debug UART feature. Do you feel comfortable looking at that? If not I could try.
Okay, i will do that and update ASAP.
Quoted 1 line
Also, do you have plans to upstream support for other chips?
yes, me and my colleague will continue to do other chips upstream, but it maybe not urgent.
Quoted 10 lines
Quoted 5 lines
--
Lin HuangRegards,
Simon
Signature · 1 line
Lin Huang