clk: sunxi: Add support for the H3 usb phy clocks

From: Reinder de Haan <[email protected]>

Note this commit only adds support for phys 1-3, phy 0, the otg phy, is not yet (fully) supported after this commit.

Signed-off-by Reinder de Haan <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

---
 .../devicetree/bindings/phy/sun4i-usb-phy.txt      |  1 +

 drivers/phy/phy-sun4i-usb.c                        | 67 +++++++++++++++++-----
 2 files changed, 53 insertions(+), 15 deletions(-)

Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +1 -0

index 0cebf74..95736d7 100644
@@ -9,6 +9,7 @@ Required properties:
   * allwinner,sun7i-a20-usb-phy
   * allwinner,sun8i-a23-usb-phy
   * allwinner,sun8i-a33-usb-phy
+  * allwinner,sun8i-h3-usb-phy
 - reg : a list of offset + length pairs
 - reg-names :
   * "phy_ctrl"

drivers/phy/phy-sun4i-usb.c +52 -15

index b12964b..17f97ab 100644
@@ -46,6 +46,9 @@
 #define REG_PHYBIST			0x08
 #define REG_PHYTUNE			0x0c
 #define REG_PHYCTL_A33			0x10
+#define REG_PHY_UNK_H3			0x20
+
+#define REG_PMU_UNK_H3			0x10
 
 #define PHYCTL_DATA			BIT(7)
 

@@ -79,7 +82,7 @@
 #define PHY_DISCON_TH_SEL		0x2a
 #define PHY_SQUELCH_DETECT		0x3c
 
-#define MAX_PHYS			3
+#define MAX_PHYS			4
 
 /*
  * Note do not raise the debounce time, we must report Vusb high within 100ms

@@ -88,12 +91,19 @@
 #define DEBOUNCE_TIME			msecs_to_jiffies(50)
 #define POLL_TIME			msecs_to_jiffies(250)
 
+enum sun4i_usb_phy_type {
+	sun4i_a10_phy,
+	sun8i_a33_phy,
+	sun8i_h3_phy
+};
+
 struct sun4i_usb_phy_data {
+	struct device *dev;
 	void __iomem *base;
 	struct mutex mutex;
 	int num_phys;
 	u32 disc_thresh;
-	bool has_a33_phyctl;
+	enum sun4i_usb_phy_type type;
 	struct sun4i_usb_phy {
 		struct phy *phy;
 		void __iomem *pmu;

@@ -164,12 +174,18 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
 
 	mutex_lock(&phy_data->mutex);
 
-	if (phy_data->has_a33_phyctl) {
+	switch (phy_data->type) {
+	case sun4i_a10_phy:
+		phyctl = phy_data->base + REG_PHYCTL_A10;
+		break;
+	case sun8i_a33_phy:
 		phyctl = phy_data->base + REG_PHYCTL_A33;
 		/* A33 needs us to set phyctl to 0 explicitly */
 		writel(0, phyctl);
-	} else {
-		phyctl = phy_data->base + REG_PHYCTL_A10;
+		break;
+	case sun8i_h3_phy:
+		dev_err(phy_data->dev, "H3 usb_phy_write is not supported\n");
+		break;
 	}
 
 	for (i = 0; i < len; i++) {

@@ -230,6 +246,7 @@ static int sun4i_usb_phy_init(struct phy *_phy)
 	struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
 	struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
 	int ret;
+	u32 val;
 
 	ret = clk_prepare_enable(phy->clk);
 	if (ret)

@@ -241,15 +258,26 @@ static int sun4i_usb_phy_init(struct phy *_phy)
 		return ret;
 	}
 
-	/* Enable USB 45 Ohm resistor calibration */
-	if (phy->index == 0)
-		sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
+	if (data->type == sun8i_h3_phy) {
+		if (phy->index == 0) {
+			val = readl(data->base + REG_PHY_UNK_H3);
+			writel(val & ~1, data->base + REG_PHY_UNK_H3);
+		}
+
+		val = readl(phy->pmu + REG_PMU_UNK_H3);
+		writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
+	} else {
+		/* Enable USB 45 Ohm resistor calibration */
+		if (phy->index == 0)
+			sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
 
-	/* Adjust PHY's magnitude and rate */
-	sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
+		/* Adjust PHY's magnitude and rate */
+		sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
 
-	/* Disconnect threshold adjustment */
-	sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data->disc_thresh, 2);
+		/* Disconnect threshold adjustment */
+		sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
+				    data->disc_thresh, 2);
+	}
 
 	sun4i_usb_phy_passby(phy, 1);
 

@@ -522,11 +550,14 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
 	mutex_init(&data->mutex);
 	INIT_DELAYED_WORK(&data->detect, sun4i_usb_phy0_id_vbus_det_scan);
 	dev_set_drvdata(dev, data);
+	data->dev = dev;
 
 	if (of_device_is_compatible(np, "allwinner,sun5i-a13-usb-phy") ||
 	    of_device_is_compatible(np, "allwinner,sun8i-a23-usb-phy") ||
 	    of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy"))
 		data->num_phys = 2;
+	else if (of_device_is_compatible(np, "allwinner,sun8i-h3-usb-phy"))
+		data->num_phys = 4;
 	else
 		data->num_phys = 3;
 

@@ -538,13 +569,18 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
 
 	if (of_device_is_compatible(np, "allwinner,sun6i-a31-usb-phy") ||
 	    of_device_is_compatible(np, "allwinner,sun8i-a23-usb-phy") ||
-	    of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy"))
+	    of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy") ||
+	    of_device_is_compatible(np, "allwinner,sun8i-h3-usb-phy"))
 		dedicated_clocks = true;
 	else
 		dedicated_clocks = false;
 
 	if (of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy"))
-		data->has_a33_phyctl = true;
+		data->type = sun8i_a33_phy;
+	else if (of_device_is_compatible(np, "allwinner,sun8i-h3-usb-phy"))
+		data->type = sun8i_h3_phy;
+	else
+		data->type = sun4i_a10_phy;
 
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl");
 	data->base = devm_ioremap_resource(dev, res);

@@ -620,7 +656,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
 			return PTR_ERR(phy->reset);
 		}
 
-		if (i) { /* No pmu for usbc0 */
+		if (data->type == sun8i_h3_phy || i != 0) {
 			snprintf(name, sizeof(name), "pmu%d", i);
 			res = platform_get_resource_byname(pdev,
 							IORESOURCE_MEM, name);

@@ -696,6 +732,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
 	{ .compatible = "allwinner,sun7i-a20-usb-phy" },
 	{ .compatible = "allwinner,sun8i-a23-usb-phy" },
 	{ .compatible = "allwinner,sun8i-a33-usb-phy" },
+	{ .compatible = "allwinner,sun8i-h3-usb-phy" },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);

Signature · 6 lines

2.5.0

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From: Reinder de Haan <[email protected]>

Note this commit only adds support for phys 1-3, phy 0, the otg phy, is
not yet (fully) supported after this commit.

Signed-off-by Reinder de Haan <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

---
?.../devicetree/bindings/phy/sun4i-usb-phy.txt??????|??1 + ?drivers/phy/phy-sun4i-usb.c????????????????????????| 67
+++++++++++++++++-----
?2 files changed, 53 insertions(+), 15 deletions(-)

Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +0 -0

index 0cebf74..95736d7 100644
@@ -9,6 +9,7 @@ Required properties:

???* allwinner,sun7i-a20-usb-phy
???* allwinner,sun8i-a23-usb-phy
???* allwinner,sun8i-a33-usb-phy
+??* allwinner,sun8i-h3-usb-phy
?- reg : a list of offset + length pairs
?- reg-names :
???* "phy_ctrl"

drivers/phy/phy-sun4i- renamed from drivers/phy/phy-sun4i-usb.c +0 -0

usb.c
index b12964b..17f97ab 100644

drivers/phy/phy-sun4i-usb.c +0 -0

@@ -46,6 +46,9 @@

?#define REG_PHYBIST 0x08
?#define REG_PHYTUNE 0x0c
?#define REG_PHYCTL_A33 0x10

drivers/phy/phy-sun4i-usb.c +3 -0

+#define REG_PHY_UNK_H3			0x20
+
+#define REG_PMU_UNK_H3			0x10

?
?#define PHYCTL_DATA BIT(7)
?

drivers/phy/phy-sun4i-usb.c +0 -0

@@ -79,7 +82,7 @@

?#define PHY_DISCON_TH_SEL 0x2a
?#define PHY_SQUELCH_DETECT 0x3c
?

drivers/phy/phy-sun4i-usb.c +1 -1

-#define MAX_PHYS			3
+#define MAX_PHYS			4

?
?/*
? * Note do not raise the debounce time, we must report Vusb high within 100ms

drivers/phy/phy-sun4i-usb.c +0 -0

@@ -88,12 +91,19 @@
 ?#define DEBOUNCE_TIME			msecs_to_jiffies(50)
 ?#define POLL_TIME			msecs_to_jiffies(250)

?

drivers/phy/phy-sun4i-usb.c +6 -0

+enum sun4i_usb_phy_type {
+	sun4i_a10_phy,
+	sun8i_a33_phy,
+	sun8i_h3_phy
+};
+

?struct sun4i_usb_phy_data {

drivers/phy/phy-sun4i-usb.c +1 -0

+	struct device *dev;

? void __iomem *base;
? struct mutex mutex;
? int num_phys;
? u32 disc_thresh;

drivers/phy/phy-sun4i-usb.c +1 -1

-	bool has_a33_phyctl;
+	enum sun4i_usb_phy_type type;

? struct sun4i_usb_phy {
? struct phy *phy;
? void __iomem *pmu;

drivers/phy/phy-sun4i-usb.c +0 -0

@@ -164,12 +174,18 @@ static void sun4i_usb_phy_write(struct
 sun4i_usb_phy *phy, u32 addr, u32 data,

?
? mutex_lock(&phy_data->mutex);
?

drivers/phy/phy-sun4i-usb.c +5 -1

-	if (phy_data->has_a33_phyctl) {
+	switch (phy_data->type) {
+	case sun4i_a10_phy:
+		phyctl = phy_data->base + REG_PHYCTL_A10;
+		break;
+	case sun8i_a33_phy:

? phyctl = phy_data->base + REG_PHYCTL_A33;
? /* A33 needs us to set phyctl to 0 explicitly */
? writel(0, phyctl);

drivers/phy/phy-sun4i-usb.c +3 -2

-	} else {
-		phyctl = phy_data->base + REG_PHYCTL_A10;
+		break;
+	case sun8i_h3_phy:
+		dev_err(phy_data->dev, "H3 usb_phy_write is not

supported\n");

drivers/phy/phy-sun4i-usb.c +1 -0

+		break;

? }
?
? for (i = 0; i < len; i++) {

drivers/phy/phy-sun4i-usb.c +0 -0

@@ -230,6 +246,7 @@ static int sun4i_usb_phy_init(struct phy *_phy)
 ?	struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);

? struct sun4i_usb_phy_data *data =
to_sun4i_usb_phy_data(phy);
? int ret;

drivers/phy/phy-sun4i-usb.c +1 -0

+	u32 val;

?
? ret = clk_prepare_enable(phy->clk);
? if (ret)

drivers/phy/phy-sun4i-usb.c +0 -0

@@ -241,15 +258,26 @@ static int sun4i_usb_phy_init(struct phy *_phy)
 ?		return ret;
 ?	}

?

drivers/phy/phy-sun4i-usb.c +4 -3

-	/* Enable USB 45 Ohm resistor calibration */
-	if (phy->index == 0)
-		sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
+	if (data->type == sun8i_h3_phy) {
+		if (phy->index == 0) {
+			val = readl(data->base + REG_PHY_UNK_H3);
+			writel(val & ~1, data->base +

REG_PHY_UNK_H3);

drivers/phy/phy-sun4i-usb.c +8 -0

+		}
+
+		val = readl(phy->pmu + REG_PMU_UNK_H3);
+		writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
+	} else {
+		/* Enable USB 45 Ohm resistor calibration */
+		if (phy->index == 0)
+			sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,

0x01, 1);
?

drivers/phy/phy-sun4i-usb.c +2 -2

-	/* Adjust PHY's magnitude and rate */
-	sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
+		/* Adjust PHY's magnitude and rate */
+		sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,

0x14, 5);
?

drivers/phy/phy-sun4i-usb.c +0 -2

-	/* Disconnect threshold adjustment */
-	sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data-

Quoted 1 line

disc_thresh, 2);

drivers/phy/phy-sun4i-usb.c +4 -0

+		/* Disconnect threshold adjustment */
+		sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
+				????data->disc_thresh, 2);
+	}

?
? sun4i_usb_phy_passby(phy, 1);
?

drivers/phy/phy-sun4i-usb.c +1 -0

@@ -522,11 +550,14 @@ static int sun4i_usb_phy_probe(struct
 platform_device *pdev)
 ?	mutex_init(&data->mutex);
 ?	INIT_DELAYED_WORK(&data->detect,
 sun4i_usb_phy0_id_vbus_det_scan);
 ?	dev_set_drvdata(dev, data);
+	data->dev = dev;

?
? if (of_device_is_compatible(np, "allwinner,sun5i-a13-usb-
phy") ||
? ????of_device_is_compatible(np, "allwinner,sun8i-a23-usb-
phy") ||
? ????of_device_is_compatible(np, "allwinner,sun8i-a33-usb-
phy"))
? data->num_phys = 2;

drivers/phy/phy-sun4i-usb.c +1 -0

+	else if (of_device_is_compatible(np, "allwinner,sun8i-h3-

usb-phy"))

drivers/phy/phy-sun4i-usb.c +1 -0

+		data->num_phys = 4;

? else
? data->num_phys = 3;
?

drivers/phy/phy-sun4i-usb.c +0 -0

@@ -538,13 +569,18 @@ static int sun4i_usb_phy_probe(struct
 platform_device *pdev)

?
? if (of_device_is_compatible(np, "allwinner,sun6i-a31-usb-
phy") ||
? ????of_device_is_compatible(np, "allwinner,sun8i-a23-usb-
phy") ||

drivers/phy/phy-sun4i-usb.c +0 -1

-	????of_device_is_compatible(np, "allwinner,sun8i-a33-usb-

phy"))

drivers/phy/phy-sun4i-usb.c +1 -0

+	????of_device_is_compatible(np, "allwinner,sun8i-a33-usb-

phy") ||

drivers/phy/phy-sun4i-usb.c +1 -0

+	????of_device_is_compatible(np, "allwinner,sun8i-h3-usb-

phy"))
? dedicated_clocks = true;
? else
? dedicated_clocks = false;
?
? if (of_device_is_compatible(np, "allwinner,sun8i-a33-usb-
phy"))

drivers/phy/phy-sun4i-usb.c +2 -1

-		data->has_a33_phyctl = true;
+		data->type = sun8i_a33_phy;
+	else if (of_device_is_compatible(np, "allwinner,sun8i-h3-

usb-phy"))

drivers/phy/phy-sun4i-usb.c +3 -0

+		data->type = sun8i_h3_phy;
+	else
+		data->type = sun4i_a10_phy;

?
? res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"phy_ctrl");
? data->base = devm_ioremap_resource(dev, res);

drivers/phy/phy-sun4i-usb.c +0 -0

@@ -620,7 +656,7 @@ static int sun4i_usb_phy_probe(struct
 platform_device *pdev)
 ?			return PTR_ERR(phy->reset);
 ?		}

?

drivers/phy/phy-sun4i-usb.c +1 -1

-		if (i) { /* No pmu for usbc0 */
+		if (data->type == sun8i_h3_phy || i != 0) {

? snprintf(name, sizeof(name), "pmu%d", i);
? res = platform_get_resource_byname(pdev,
? IORESOURCE_M
EM, name);

drivers/phy/phy-sun4i-usb.c +1 -0

@@ -696,6 +732,7 @@ static const struct of_device_id
 sun4i_usb_phy_of_match[] = {
 ?	{ .compatible = "allwinner,sun7i-a20-usb-phy" },
 ?	{ .compatible = "allwinner,sun8i-a23-usb-phy" },
 ?	{ .compatible = "allwinner,sun8i-a33-usb-phy" },
+	{ .compatible = "allwinner,sun8i-h3-usb-phy" },
 ?	{ },
 ?};

?MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);

Signature · 1 line

2.5.0

Quoted 5 lines · Hans de Goede

From: Reinder de Haan <[email protected]>

Note this commit only adds support for phys 1-3, phy 0, the otg phy, is
not yet (fully) supported after this commit.

This patch seems to be causing following compile warning:

In file included from include/linux/io.h:25:0,

                  from drivers/phy/phy-sun4i-usb.c:28:

drivers/phy/phy-sun4i-usb.c: In function 'sun4i_usb_phy_write': ./arch/arm/include/asm/io.h:94:2: warning: 'phyctl' may be used uninitialized in this function [-Wmaybe-uni nitialized]
asm volatile("strb %1, %0"
^
drivers/phy/phy-sun4i-usb.c:172:8: note: 'phyctl' was declared here
void *phyctl;

Quoted 214 lines

Signed-off-by Reinder de Haan <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

---
  .../devicetree/bindings/phy/sun4i-usb-phy.txt      |  1 +
  drivers/phy/phy-sun4i-usb.c                        | 67
+++++++++++++++++-----
  2 files changed, 53 insertions(+), 15 deletions(-)

Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +1 -0

index 0cebf74..95736d7 100644
@@ -9,6 +9,7 @@ Required properties:
    * allwinner,sun7i-a20-usb-phy
    * allwinner,sun8i-a23-usb-phy
    * allwinner,sun8i-a33-usb-phy
+  * allwinner,sun8i-h3-usb-phy
  - reg : a list of offset + length pairs
  - reg-names :
    * "phy_ctrl"

drivers/phy/phy-sun4i- renamed from drivers/phy/phy-sun4i-usb.c +0 -0

usb.c
index b12964b..17f97ab 100644

drivers/phy/phy-sun4i-usb.c +4 -1

@@ -46,6 +46,9 @@
  #define REG_PHYBIST			0x08
  #define REG_PHYTUNE			0x0c
  #define REG_PHYCTL_A33			0x10
+#define REG_PHY_UNK_H3			0x20
+
+#define REG_PMU_UNK_H3			0x10
 
  #define PHYCTL_DATA			BIT(7)
 

@@ -79,7 +82,7 @@
  #define PHY_DISCON_TH_SEL		0x2a
  #define PHY_SQUELCH_DETECT		0x3c
 
-#define MAX_PHYS			3
+#define MAX_PHYS			4
 
  /*
   * Note do not raise the debounce time, we must report Vusb high

within 100ms

drivers/phy/phy-sun4i-usb.c +17 -4

@@ -88,12 +91,19 @@
  #define DEBOUNCE_TIME			msecs_to_jiffies(50)
  #define POLL_TIME			msecs_to_jiffies(250)
 
+enum sun4i_usb_phy_type {
+	sun4i_a10_phy,
+	sun8i_a33_phy,
+	sun8i_h3_phy
+};
+
  struct sun4i_usb_phy_data {
+	struct device *dev;
  	void __iomem *base;
  	struct mutex mutex;
  	int num_phys;
  	u32 disc_thresh;
-	bool has_a33_phyctl;
+	enum sun4i_usb_phy_type type;
  	struct sun4i_usb_phy {
  		struct phy *phy;
  		void __iomem *pmu;

@@ -164,12 +174,18 @@ static void sun4i_usb_phy_write(struct
 sun4i_usb_phy *phy, u32 addr, u32 data,
 
  	mutex_lock(&phy_data->mutex);
 
-	if (phy_data->has_a33_phyctl) {
+	switch (phy_data->type) {
+	case sun4i_a10_phy:
+		phyctl = phy_data->base + REG_PHYCTL_A10;
+		break;
+	case sun8i_a33_phy:
  		phyctl = phy_data->base + REG_PHYCTL_A33;
  		/* A33 needs us to set phyctl to 0 explicitly */
  		writel(0, phyctl);
-	} else {
-		phyctl = phy_data->base + REG_PHYCTL_A10;
+		break;
+	case sun8i_h3_phy:
+		dev_err(phy_data->dev, "H3 usb_phy_write is not
 supported\n");
+		break;
  	}

  	for (i = 0; i < len; i++) {

drivers/phy/phy-sun4i-usb.c +1 -0

@@ -230,6 +246,7 @@ static int sun4i_usb_phy_init(struct phy *_phy)
  	struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
  	struct sun4i_usb_phy_data *data =
 to_sun4i_usb_phy_data(phy);
  	int ret;
+	u32 val;
 
  	ret = clk_prepare_enable(phy->clk);

if (ret)

drivers/phy/phy-sun4i-usb.c +14 -7

@@ -241,15 +258,26 @@ static int sun4i_usb_phy_init(struct phy *_phy)
  		return ret;
  	}
 
-	/* Enable USB 45 Ohm resistor calibration */
-	if (phy->index == 0)
-		sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
+	if (data->type == sun8i_h3_phy) {
+		if (phy->index == 0) {
+			val = readl(data->base + REG_PHY_UNK_H3);
+			writel(val & ~1, data->base +
 REG_PHY_UNK_H3);
+		}
+
+		val = readl(phy->pmu + REG_PMU_UNK_H3);
+		writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
+	} else {
+		/* Enable USB 45 Ohm resistor calibration */
+		if (phy->index == 0)
+			sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
 0x01, 1);
 
-	/* Adjust PHY's magnitude and rate */
-	sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
+		/* Adjust PHY's magnitude and rate */
+		sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,
 0x14, 5);
 
-	/* Disconnect threshold adjustment */
-	sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data-

Quoted 1 line

disc_thresh, 2);

drivers/phy/phy-sun4i-usb.c +5 -0

+		/* Disconnect threshold adjustment */
+		sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
+				    data->disc_thresh, 2);
+	}
 
  	sun4i_usb_phy_passby(phy, 1);

@@ -522,11 +550,14 @@ static int sun4i_usb_phy_probe(struct
 platform_device *pdev)
  	mutex_init(&data->mutex);
  	INIT_DELAYED_WORK(&data->detect,
 sun4i_usb_phy0_id_vbus_det_scan);
  	dev_set_drvdata(dev, data);
+	data->dev = dev;
 
  	if (of_device_is_compatible(np, "allwinner,sun5i-a13-usb-

phy") ||
of_device_is_compatible(np, "allwinner,sun8i-a23-usb-
phy") ||
of_device_is_compatible(np, "allwinner,sun8i-a33-usb-
phy"))
data->num_phys = 2;

drivers/phy/phy-sun4i-usb.c +1 -0

+	else if (of_device_is_compatible(np, "allwinner,sun8i-h3-

usb-phy"))

drivers/phy/phy-sun4i-usb.c +1 -0

+		data->num_phys = 4;
  	else
  		data->num_phys = 3;

@@ -538,13 +569,18 @@ static int sun4i_usb_phy_probe(struct
 platform_device *pdev)
 
  	if (of_device_is_compatible(np, "allwinner,sun6i-a31-usb-

phy") ||
of_device_is_compatible(np, "allwinner,sun8i-a23-usb-
phy") ||

drivers/phy/phy-sun4i-usb.c +0 -1

-	    of_device_is_compatible(np, "allwinner,sun8i-a33-usb-

phy"))

drivers/phy/phy-sun4i-usb.c +1 -0

+	    of_device_is_compatible(np, "allwinner,sun8i-a33-usb-

phy") ||

drivers/phy/phy-sun4i-usb.c +1 -0

+	    of_device_is_compatible(np, "allwinner,sun8i-h3-usb-

phy"))
dedicated_clocks = true;
else
dedicated_clocks = false;

if (of_device_is_compatible(np, "allwinner,sun8i-a33-usb-
phy"))

drivers/phy/phy-sun4i-usb.c +2 -1

-		data->has_a33_phyctl = true;
+		data->type = sun8i_a33_phy;
+	else if (of_device_is_compatible(np, "allwinner,sun8i-h3-

usb-phy"))

drivers/phy/phy-sun4i-usb.c +3 -0

+		data->type = sun8i_h3_phy;
+	else
+		data->type = sun4i_a10_phy;
 
  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

"phy_ctrl");
data->base = devm_ioremap_resource(dev, res);

drivers/phy/phy-sun4i-usb.c +1 -1

@@ -620,7 +656,7 @@ static int sun4i_usb_phy_probe(struct
 platform_device *pdev)
  			return PTR_ERR(phy->reset);
  		}
 
-		if (i) { /* No pmu for usbc0 */
+		if (data->type == sun8i_h3_phy || i != 0) {
  			snprintf(name, sizeof(name), "pmu%d", i);
  			res = platform_get_resource_byname(pdev,

IORESOURCE_M
EM, name);

drivers/phy/phy-sun4i-usb.c +1 -0

@@ -696,6 +732,7 @@ static const struct of_device_id
 sun4i_usb_phy_of_match[] = {
  	{ .compatible = "allwinner,sun7i-a20-usb-phy" },
  	{ .compatible = "allwinner,sun8i-a23-usb-phy" },
  	{ .compatible = "allwinner,sun8i-a33-usb-phy" },
+	{ .compatible = "allwinner,sun8i-h3-usb-phy" },
  	{ },
  };

MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
--
2.5.0

From: Reinder de Haan <[email protected]>

Add a node describing the usb-clks found on the H3.

Signed-off-by Reinder de Haan <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

---
 arch/arm/boot/dts/sun8i-h3.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm/boot/dts/sun8i-h3.dtsi +12 -1

index c18b5f7..22ff593 100644
@@ -266,6 +266,18 @@
                                             "mmc2_sample";
                };
 
+               usb_clk: clk at 01c200cc {
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       compatible = "allwinner,sun8i-h3-usb-clk";
+                       reg = <0x01c200cc 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "usb_phy0", "usb_phy1",
+                                            "usb_phy2", "usb_phy3",
+                                            "usb_ohci0", "usb_ohci1",
+                                            "usb_ohci2", "usb_ohci3";
+               };
+
                mbus_clk: clk at 01c2015c {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun8i-a23-mbus-clk";
--

2.5.0

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From: Reinder de Haan <[email protected]>

Enable the 3 pairs of USB host controllers used on the Orange Pi Plus.

Signed-off-by Reinder de Haan <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

---
 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +12 -0

index e67df59..e05a409 100644
@@ -60,6 +60,18 @@
        };
 };
 
+&ehci1 {
+       status = "okay";
+};
+
+&ehci2 {
+       status = "okay";
+};
+
+&ehci3 {
+       status = "okay";
+};
+
 &mmc0 {
        pinctrl-names = "default";
        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;

arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +1 -1

+};
--

2.5.0

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Hi,

Quoted 37 lines · Hans de Goede

From: Reinder de Haan <[email protected]>

Enable the 3 pairs of USB host controllers used on the Orange Pi Plus.

Signed-off-by Reinder de Haan <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

---
  arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 28 ++++++++++++++++++++++++++++
  1 file changed, 28 insertions(+)

arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +12 -0

index e67df59..e05a409 100644
@@ -60,6 +60,18 @@
         };
  };
 
+&ehci1 {
+       status = "okay";
+};
+
+&ehci2 {
+       status = "okay";
+};
+
+&ehci3 {
+       status = "okay";
+};
+
  &mmc0 {
         pinctrl-names = "default";
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;

@@ -70,8 +82,24 @@
         status = "okay";
  };
 

arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts line 87

Quoted 3 lines

arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +3 -0

+&ohci1 {
+       status = "okay";
+};

This controller is connected to a FE1.1s USB 2.0 hub, giving us the four usable external USB ports. We shouldn't need to enable OHCI.

arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts line 91

Quoted 4 lines

arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +4 -0

+
+&ohci2 {
+       status = "okay";
+};

According to the schematics, this port is never used. Please remove.

arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts line 95

Quoted 4 lines

arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +3 -0

+&ohci3 {
+       status = "okay";
+};

This is connected to the GL830 USB-SATA bridge. Again, OHCI isn't needed.

arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts line 104

Quoted 9 lines

arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +4 -0

+
  &uart0 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart0_pins_a>;
         status = "okay";
  };
+
+&usbphy {
+       status = "okay";

And what about power supplies / regulators?

Enable the 2 USB host controllers used on the Orange Pi Plus and add the necessary regulators.

Signed-off-by Reinder de Haan <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

Signed-off-by Jens Kuske <[email protected]>

---

Hi Hans,

with these regulators USB works on the Orange Pi Plus too. I don't know if adding the regulators in the dts is okay, since most regulators are defined in the sunxi-common-regulators.dtsi, but we use different pins.

Jens

  arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 44 ++++++++++++++++++++++++++++
  1 file changed, 44 insertions(+)

arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +44 -0

index e67df59..1cb6c66 100644
@@ -58,6 +58,35 @@
  	chosen {
  		stdout-path = "serial0:115200n8";
  	};
+
+	reg_usb3_vbus: usb3-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb3_vbus_pin_a>;
+		regulator-name = "usb3-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		enable-active-high;
+		gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&ehci3 {
+	status = "okay";
+};
+
+&pio {
+	usb3_vbus_pin_a: usb3_vbus_pin at 0 {
+		allwinner,pins = "PG11";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
  };
 
  &mmc0 {

@@ -70,8 +99,23 @@
  	status = "okay";
  };
 
+&reg_usb1_vbus {
+	gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
  &uart0 {
  	pinctrl-names = "default";
  	pinctrl-0 = <&uart0_pins_a>;
  	status = "okay";
  };
+
+&usb1_vbus_pin_a {
+	allwinner,pins = "PG13";
+};
+
+&usbphy {
+	usb1_vbus-supply = <&reg_usb1_vbus>;
+	usb3_vbus-supply = <&reg_usb3_vbus>;
+	status = "okay";
+};

Hi,

Quoted 6 lines · Jens Kuske

Enable the 2 USB host controllers used on the Orange Pi Plus and add the necessary regulators.

Signed-off-by Reinder de Haan <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

Signed-off-by Jens Kuske <[email protected]>

Quoted 8 lines

---

Hi Hans,

with these regulators USB works on the Orange Pi Plus too. I don't know if adding the regulators in the dts is okay, since most regulators are defined in the sunxi-common-regulators.dtsi, but we use different pins.

Thanks, I've added this to my sunxi-wip branch for now.

Regards,

Hans

p.s.

Any progress on getting the "core" H3 kernel support upstream ?

Given Arnd's remarks about how we should not hard-code the indices in the clk driver + the very KISS nature of the change to 1 parent-clk per gate setup I still believe that that one is best.

Maxime ? Chen-Yu ? It would be really good to be able to move forward with this, how do you want to proceed ?

Enable the 2 USB host controllers used on the Orange Pi Plus and add the necessary regulators.

Signed-off-by Reinder de Haan <patch...-I1/[email protected] <javascript:>>

Signed-off-by Hans de Goede <[email protected] <javascript:>>

Signed-off-by Jens Kuske <[email protected] <javascript:>>

---

Hi Hans,

with these regulators USB works on the Orange Pi Plus too. I don't know if adding the regulators in the dts is okay, since most regulators are defined in the sunxi-common-regulators.dtsi, but we use different pins.

Jens

 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 44 
++++++++++++++++++++++++++++ 
 1 file changed, 44 insertions(+) 

arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +34 -0

index e67df59..1cb6c66 100644 
@@ -58,6 +58,35 @@ 
         chosen { 
                 stdout-path = "serial0:115200n8"; 
         }; 
+ 
+        reg_usb3_vbus: usb3-vbus { 
+                compatible = "regulator-fixed"; 
+                pinctrl-names = "default"; 
+                pinctrl-0 = <&usb3_vbus_pin_a>; 
+                regulator-name = "usb3-vbus"; 
+                regulator-min-microvolt = <5000000>; 
+                regulator-max-microvolt = <5000000>; 
+                regulator-boot-on; 
+                enable-active-high; 
+                gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; 
+        }; 
+}; 
+ 
+&ehci1 { 
+        status = "okay"; 
+}; 
+ 
+&ehci3 { 
+        status = "okay"; 
+}; 
+ 
+&pio { 
+        usb3_vbus_pin_a: usb3_vbus_pin@0 { 
+                allwinner,pins = "PG11"; 
+                allwinner,function = "gpio_out"; 
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>; 
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 
+        }; 
 }; 
 
 &mmc0 { 

@@ -70,8 +99,23 @@ 
         status = "okay"; 
 }; 
 
+&reg_usb1_vbus { 
+        gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; 
+        status = "okay"; 
+}; 
+ 
 &uart0 { 
         pinctrl-names = "default"; 
         pinctrl-0 = <&uart0_pins_a>; 
         status = "okay"; 
 }; 

Quoted 79 lines · Jens Kuske

Enable the 2 USB host controllers used on the Orange Pi Plus and add the necessary regulators.

Signed-off-by Reinder de Haan <[email protected] <javascript:>>

Signed-off-by Hans de Goede <[email protected] <javascript:>>

Signed-off-by Jens Kuske <[email protected] <javascript:>>

---

Hi Hans,

with these regulators USB works on the Orange Pi Plus too. I don't know if adding the regulators in the dts is okay, since most regulators are defined in the sunxi-common-regulators.dtsi, but we use different pins.

Jens

  arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 44
++++++++++++++++++++++++++++
  1 file changed, 44 insertions(+)

arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +34 -0

index e67df59..1cb6c66 100644
@@ -58,6 +58,35 @@
          chosen {
                  stdout-path = "serial0:115200n8";
          };
+
+        reg_usb3_vbus: usb3-vbus {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&usb3_vbus_pin_a>;
+                regulator-name = "usb3-vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+                enable-active-high;
+                gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+        };
+};
+
+&ehci1 {
+        status = "okay";
+};
+
+&ehci3 {
+        status = "okay";
+};
+
+&pio {
+        usb3_vbus_pin_a: usb3_vbus_pin at 0 {
+                allwinner,pins = "PG11";
+                allwinner,function = "gpio_out";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+        };
  };
 
  &mmc0 {

@@ -70,8 +99,23 @@
          status = "okay";
  };
 
+&reg_usb1_vbus {
+        gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+
  &uart0 {
          pinctrl-names = "default";
          pinctrl-0 = <&uart0_pins_a>;
          status = "okay";
  };

arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts line 121

Quoted 10 lines

arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +10 -0

+
+&usb1_vbus_pin_a {
+        allwinner,pins = "PG13";
+};
+
+&usbphy {
+        usb1_vbus-supply = <&reg_usb1_vbus>;
+        usb3_vbus-supply = <&reg_usb3_vbus>;
+        status = "okay";
+};

I've been trying to test these patches by using Hans' github sunxi-wip branches of the kernel and U-Boot.

U-Boot at commit 7e17fd2 "suxni: Add support for Orangepi Plus and Orangepi PC boards"
Kernel at commit cb45b8 "ARM: dts: sun8i-h3-orangepi-plus: Enable USB host controllers"

Both have been built using the default defconfig for an OrangePi Plus

U-Boot starts and successfully boots the kernel, but the kernel does not appear to boot fully and hangs at:

[    0.861175] cpu cpu0: failed to get cpu0 clock: -2
[    0.865973] cpufreq-dt: probe of cpufreq-dt failed with error -2
[    0.872017] Registering SWP/SWPB emulation handler

Full boot log: http://pastebin.com/VGkEix9p

Building the kernel (or just using a dab) with the dts from commit 0a8c01 "ARM: dts: sun8i: Add Orange Pi Plus support" results in the kernel booting fully to a login prompt. Of course without enabled/working USB.

There is a fair chance I've done something wrong that is causing this. Any advice on how to get a bootable kernel?

Hi,

Quoted 11 lines · Troy Dack

Quoted 4 lines · Jens Kuske

Enable the 2 USB host controllers used on the Orange Pi Plus and add the necessary regulators.

I've been trying to test these patches by using Hans' github sunxi-wip branches of the kernel and U-Boot.

U-Boot at commit 7e17fd2 "suxni: Add support for Orangepi Plus and

Orangepi

Quoted 2 lines

PC boards"
Kernel at commit cb45b8 "ARM: dts: sun8i-h3-orangepi-plus: Enable USB

host

Quoted 7 lines

controllers"

Both have been built using the default defconfig for an OrangePi Plus

U-Boot starts and successfully boots the kernel, but the kernel does not appear to boot fully and hangs at:

Quoted 7 lines

[    0.861175] cpu cpu0: failed to get cpu0 clock: -2 
[    0.865973] cpufreq-dt: probe of cpufreq-dt failed with error -2 
[    0.872017] Registering SWP/SWPB emulation handler 

Full boot log: http://pastebin.com/VGkEix9p

Building the kernel (or just using a dab) with the dts from commit

0a8c01

Quoted 1 line

"ARM: dts: sun8i: Add Orange Pi Plus support" results in the kernel

booting

Quoted 3 lines

fully to a login prompt. Of course without enabled/working USB.

There is a fair chance I've done something wrong that is causing this.

Any

Quoted 1 line

advice on how to get a bootable kernel?

Weird, are you sure you updated both the dtb and [u|z]image at the same time ?

I'm using this kernel config:

https://fedorapeople.org/~jwrdegoede/kernel-driver-programming/kernel-config

With that everything you need is builtin, no need to build modules.

Regards,

Hans

From: Reinder de Haan <[email protected]>

The H3 has a usb-phy clk register which is similar to that of earlier SoCs, but with support for a larger number of phys. So we can simply add a new set of clk-data and a new compatible and be done with it.

Signed-off-by Reinder de Haan <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/clk-usb.c                       | 12 ++++++++++++
 2 files changed, 13 insertions(+)

Documentation/devicetree/bindings/clock/sunxi.txt +1 -0

index d303dec..23e7bce 100644
@@ -70,6 +70,7 @@ Required properties:
        "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
        "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
        "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23
+       "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
        "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
        "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
 

drivers/clk/sunxi/clk-usb.c +12 -1

index 1a72cd6..67b8e38 100644
@@ -243,3 +243,15 @@ static void __init sun9i_a80_usb_phy_setup(struct device_node *node)
        sunxi_usb_clk_setup(node, &sun9i_a80_usb_phy_data, &a80_usb_phy_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_usb_phy, "allwinner,sun9i-a80-usb-phy-clk", sun9i_a80_usb_phy_setup);
+
+static const struct usb_clk_data sun8i_h3_usb_clk_data __initconst = {
+       .clk_mask =  BIT(19) | BIT(18) | BIT(17) | BIT(16) |
+                    BIT(11) | BIT(10) | BIT(9) | BIT(8),
+       .reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
+};
+
+static void __init sun8i_h3_usb_setup(struct device_node *node)
+{
+       sunxi_usb_clk_setup(node, &sun8i_h3_usb_clk_data, &sun4i_a10_usb_lock);
+}
+CLK_OF_DECLARE(sun8i_h3_usb, "allwinner,sun8i-h3-usb-clk", sun8i_h3_usb_setup);
--

2.5.0

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Quoted 8 lines · Hans de Goede

From: Reinder de Haan <[email protected]>

The H3 has a usb-phy clk register which is similar to that of earlier SoCs, but with support for a larger number of phys. So we can simply add a new set of clk-data and a new compatible and be done with it.

Signed-off-by Reinder de Haan <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

Acked-by Chen-Yu Tsai <[email protected]>

From: Reinder de Haan <[email protected]>

The H3 has a usb-phy clk register which is similar to that of earlier SoCs, but with support for a larger number of phys. So we can simply add a new set of clk-data and a new compatible and be done with it.

Signed-off-by Reinder de Haan <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/clk-usb.c                       | 12 ++++++++++++
 2 files changed, 13 insertions(+)

Documentation/devicetree/bindings/clock/sunxi.txt +1 -0

index d303dec..23e7bce 100644
@@ -70,6 +70,7 @@ Required properties:
 	"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
 	"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
 	"allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23
+	"allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
 	"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
 	"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
 

drivers/clk/sunxi/clk-usb.c +12 -0

index 1a72cd6..67b8e38 100644
@@ -243,3 +243,15 @@ static void __init sun9i_a80_usb_phy_setup(struct device_node *node)
 	sunxi_usb_clk_setup(node, &sun9i_a80_usb_phy_data, &a80_usb_phy_lock);
 }
 CLK_OF_DECLARE(sun9i_a80_usb_phy, "allwinner,sun9i-a80-usb-phy-clk", sun9i_a80_usb_phy_setup);
+
+static const struct usb_clk_data sun8i_h3_usb_clk_data __initconst = {
+	.clk_mask =  BIT(19) | BIT(18) | BIT(17) | BIT(16) |
+		     BIT(11) | BIT(10) | BIT(9) | BIT(8),
+	.reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
+};
+
+static void __init sun8i_h3_usb_setup(struct device_node *node)
+{
+	sunxi_usb_clk_setup(node, &sun8i_h3_usb_clk_data, &sun4i_a10_usb_lock);
+}
+CLK_OF_DECLARE(sun8i_h3_usb, "allwinner,sun8i-h3-usb-clk", sun8i_h3_usb_setup);

Signature · 6 lines

2.5.0

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