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arm64: update linker script to increased L1_CACHE_BYTES value

PATCH New Ard Biesheuvel 3 participants 4 messages Dec 1, 2015 arm64

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Ard Biesheuvel

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#0 lore raw

PATCH 1/1 arm64: update linker script to increased L1_CACHE_BYTES value

Bring the linker script in line with the recent increase of L1_CACHE_BYTES to 128. Replace the hardcoded value of 64 with the symbolic constant.

Signed-off-by Ard Biesheuvel <[email protected]>
---
 arch/arm64/kernel/vmlinux.lds.S | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
arch/arm64/kernel/vmlinux.lds.S +2 -1
index 1ee2c3937d4e..3388970fbc0f 100644
@@ -5,6 +5,7 @@
  */
 
 #include <asm-generic/vmlinux.lds.h>
+#include <asm/cache.h>
 #include <asm/kernel-pgtable.h>
 #include <asm/thread_info.h>
 #include <asm/memory.h>

@@ -140,7 +141,7 @@ SECTIONS
 		ARM_EXIT_KEEP(EXIT_DATA)
 	}
 
-	PERCPU_SECTION(64)
+	PERCPU_SECTION(L1_CACHE_BYTES)
 
 	. = ALIGN(PAGE_SIZE);
 	__init_end = .;
Signature · 1 line
1.9.1
reviewer
#1 lore raw

PATCH 1/1 arm64: update linker script to increased L1_CACHE_BYTES value

Quoted 5 lines · Ard Biesheuvel

Bring the linker script in line with the recent increase of L1_CACHE_BYTES to 128. Replace the hardcoded value of 64 with the symbolic constant.

Signed-off-by Ard Biesheuvel <[email protected]>

I think we need to same substitution for RW_DATA_SECTION too, for CACHELINE_ALIGNED_DATA(cacheline) and READ_MOSTLY_DATA(cacheline).

For 32-bit, Will made the same changes in f0d5375e3c7b5d7f ("ARM:
7289/1: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes").

With that:

Acked-by Mark Rutland <[email protected]>

Mark.

Quoted 28 lines
---
 arch/arm64/kernel/vmlinux.lds.S | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
arch/arm64/kernel/vmlinux.lds.S +2 -1
index 1ee2c3937d4e..3388970fbc0f 100644
@@ -5,6 +5,7 @@
  */
 
 #include <asm-generic/vmlinux.lds.h>
+#include <asm/cache.h>
 #include <asm/kernel-pgtable.h>
 #include <asm/thread_info.h>
 #include <asm/memory.h>

@@ -140,7 +141,7 @@ SECTIONS
 		ARM_EXIT_KEEP(EXIT_DATA)
 	}
 
-	PERCPU_SECTION(64)
+	PERCPU_SECTION(L1_CACHE_BYTES)
 
 	. = ALIGN(PAGE_SIZE);
 	__init_end = .;
Signature · 1 line
1.9.1
maintainer
#2 lore raw

PATCH 1/1 arm64: update linker script to increased L1_CACHE_BYTES value

Quoted 9 lines · Mark Rutland
Quoted 5 lines · Ard Biesheuvel

Bring the linker script in line with the recent increase of L1_CACHE_BYTES to 128. Replace the hardcoded value of 64 with the symbolic constant.

Signed-off-by Ard Biesheuvel <[email protected]>

I think we need to same substitution for RW_DATA_SECTION too, for CACHELINE_ALIGNED_DATA(cacheline) and READ_MOSTLY_DATA(cacheline).

In case anyone else asks, I applied this fix-up as well.

Signature · 1 line
Catalin
maintainer Applied
#3 lore raw

PATCH 1/1 arm64: update linker script to increased L1_CACHE_BYTES value

In reply to Ard Biesheuvel
Quoted 5 lines · Ard Biesheuvel

Bring the linker script in line with the recent increase of L1_CACHE_BYTES to 128. Replace the hardcoded value of 64 with the symbolic constant.

Signed-off-by Ard Biesheuvel <[email protected]>

Applied. Thanks.

Signature · 1 line
Catalin