pinctrl: meson: enable support for external GPIO interrupts

From: Carlo Caione <[email protected]>

of_irq_find_parent was made static since it had no users outside of of_irq.c. Export it again since we are going to use it again.

Signed-off-by Carlo Caione <[email protected]>

---
 drivers/of/irq.c       | 3 ++-
 include/linux/of_irq.h | 6 ++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

drivers/of/irq.c +2 -1

index 902b89b..4fa916d 100644
@@ -53,7 +53,7 @@ EXPORT_SYMBOL_GPL(irq_of_parse_and_map);
  * Returns a pointer to the interrupt parent node, or NULL if the interrupt
  * parent could not be determined.
  */
-static struct device_node *of_irq_find_parent(struct device_node *child)
+struct device_node *of_irq_find_parent(struct device_node *child)
 {
        struct device_node *p;
        const __be32 *parp;

@@ -77,6 +77,7 @@ static struct device_node *of_irq_find_parent(struct device_node *child)
 
        return p;
 }
+EXPORT_SYMBOL_GPL(of_irq_find_parent);
 
 /**
  * of_irq_parse_raw - Low level interrupt tree parsing

include/linux/of_irq.h +0 -0

index 039f2ee..6f879c6 100644

From: Carlo Caione <[email protected]>

On Meson8 and Meson8b SoCs there are 8 independent filtered GPIO interrupt modules that can be programmed to use any of the GPIOs in the chip as an interrupt source.

For each GPIO IRQ we have:

GPIOs --> [mux]--> [polarity]--> [filter]--> [edge select]--> GIC

The eight GPIO interrupts respond to mask/unmask/clear/etc.. just like any other interrupt in the chip. The difference for the GPIO interrupts is that they can be filtered and conditioned.

This patch adds support for the external GPIOs interrupts and enables them for Meson8 and Meson8b SoCs.

Signed-off-by Carlo Caione <[email protected]>

Signed-off-by Beniamino Galvani <[email protected]>

---
 drivers/pinctrl/Kconfig                    |   1 +
 drivers/pinctrl/meson/Makefile             |   2 +-
 drivers/pinctrl/meson/irqchip-gpio-meson.c | 321 +++++++++++++++++++++++++++++
 drivers/pinctrl/meson/pinctrl-meson.c      |  30 +++
 drivers/pinctrl/meson/pinctrl-meson.h      |  15 ++
 5 files changed, 368 insertions(+), 1 deletion(-)
 create mode 100644 drivers/pinctrl/meson/irqchip-gpio-meson.c

drivers/pinctrl/meson/irqchip-gpio-meson.c new file +21 -0

+static int meson_irq_domain_alloc(struct irq_domain *domain, unsigned int irq,
+				  unsigned int nr_irqs, void *arg)
+{
+	struct meson_pinctrl *pc = domain->host_data;
+	struct irq_fwspec *irq_data = arg;
+	struct irq_fwspec gic_data;
+	irq_hw_number_t hwirq;
+	int index, ret, i;
+
+	if (irq_data->param_count != 2)
+		return -EINVAL;
+
+	hwirq = irq_data->param[0];
+	dev_dbg(pc->dev, "%s irq %d, nr %d, hwirq %lu\n",
+			__func__, irq, nr_irqs, hwirq);
+
+	for (i = 0; i < nr_irqs; i++) {
+		index = meson_map_gic_irq(domain, hwirq + i);
+		if (index < 0)
+			return index;
+

drivers/pinctrl/meson/irqchip-gpio-meson.c new file +110 -0

+
+		ret = irq_domain_alloc_irqs_parent(domain, irq + i, nr_irqs,
+						   &gic_data);
+	}
+
+	return 0;
+}
+
+static void meson_irq_domain_free(struct irq_domain *domain, unsigned int irq,
+				  unsigned int nr_irqs)
+{
+	struct meson_pinctrl *pc = domain->host_data;
+	struct irq_data *irq_data;
+	int index, i;
+
+	spin_lock(&pc->lock);
+	for (i = 0; i < nr_irqs; i++) {
+		irq_data = irq_domain_get_irq_data(domain, irq + i);
+		index = meson_get_gic_irq(pc, irq_data->hwirq);
+		if (index < 0)
+			continue;
+		pc->irq_map[index] = IRQ_FREE;
+	}
+	spin_unlock(&pc->lock);
+
+	irq_domain_free_irqs_parent(domain, irq, nr_irqs);
+}
+
+static int meson_irq_domain_translate(struct irq_domain *d,
+				      struct irq_fwspec *fwspec,
+				      unsigned long *hwirq,
+				      unsigned int *type)
+{
+	if (is_of_node(fwspec->fwnode)) {
+		if (fwspec->param_count != 2)
+			return -EINVAL;
+
+		*hwirq = fwspec->param[0];
+		*type = fwspec->param[1];
+
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
+static struct irq_domain_ops meson_irq_domain_ops = {
+	.alloc		= meson_irq_domain_alloc,
+	.free		= meson_irq_domain_free,
+	.translate	= meson_irq_domain_translate,
+};
+
+int meson_gpio_irq_init(struct meson_pinctrl *pc)
+{
+	struct device_node *node = pc->dev->of_node;
+	struct device_node *parent_node;
+	struct irq_domain *parent_domain;
+	const __be32 *irqs;
+	int i, size;
+
+	parent_node = of_irq_find_parent(node);
+	if (!parent_node) {
+		dev_err(pc->dev, "can't find parent interrupt controller\n");
+		return -EINVAL;
+	}
+
+	parent_domain = irq_find_host(parent_node);
+	if (!parent_domain) {
+		dev_err(pc->dev, "can't find parent IRQ domain\n");
+		return -EINVAL;
+	}
+
+	pc->reg_irq = meson_map_resource(pc, node, "irq");
+	if (!pc->reg_irq) {
+		dev_err(pc->dev, "can't find irq registers\n");
+		return -EINVAL;
+	}
+
+	irqs = of_get_property(node, "amlogic,irqs-gpio", &size);
+	if (!irqs) {
+		dev_err(pc->dev, "no parent interrupts specified\n");
+		return -EINVAL;
+	}
+	pc->num_gic_irqs = size / sizeof(__be32);
+
+	pc->irq_map = devm_kmalloc(pc->dev, sizeof(int) * pc->num_gic_irqs,
+				   GFP_KERNEL);
+	if (!pc->irq_map)
+		return -ENOMEM;
+
+	pc->gic_irqs = devm_kzalloc(pc->dev, sizeof(int) * pc->num_gic_irqs,
+				    GFP_KERNEL);
+	if (!pc->gic_irqs)
+		return -ENOMEM;
+
+	for (i = 0; i < pc->num_gic_irqs; i++) {
+		pc->irq_map[i] = IRQ_FREE;
+		of_property_read_u32_index(node, "amlogic,irqs-gpio", i,
+					   &pc->gic_irqs[i]);
+	}
+
+	pc->irq_domain = irq_domain_add_hierarchy(parent_domain, 0,
+						  pc->data->last_pin,
+						  node, &meson_irq_domain_ops,
+						  pc);
+	if (!pc->irq_domain)
+		return -EINVAL;
+
+	return 0;
+}

drivers/pinctrl/meson/pinctrl-meson.c +8 -0

index 0c5655b..894b9ad 100644
@@ -540,6 +540,30 @@ static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
 	return !!(val & BIT(bit));
 }
 
+static int meson_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+	struct meson_domain *domain = to_meson_domain(chip);
+	struct meson_pinctrl *pc = domain->pinctrl;
+	struct meson_bank *bank;
+	struct irq_fwspec irq_data;
+	unsigned int hwirq, irq;
+

Quoted 25 lines · Carlo Caione

From: Carlo Caione <[email protected]>

drivers/pinctrl/meson/irqchip-gpio-meson.c new file +23 -0

+static int meson_irq_domain_alloc(struct irq_domain *domain, unsigned int irq,
+                               unsigned int nr_irqs, void *arg)
+{
+     struct meson_pinctrl *pc = domain->host_data;
+     struct irq_fwspec *irq_data = arg;
+     struct irq_fwspec gic_data;
+     irq_hw_number_t hwirq;
+     int index, ret, i;
+
+     if (irq_data->param_count != 2)
+             return -EINVAL;
+
+     hwirq = irq_data->param[0];
+     dev_dbg(pc->dev, "%s irq %d, nr %d, hwirq %lu\n",
+                     __func__, irq, nr_irqs, hwirq);
+
+     for (i = 0; i < nr_irqs; i++) {
+             index = meson_map_gic_irq(domain, hwirq + i);
+             if (index < 0)
+                     return index;
+
+             irq_domain_set_hwirq_and_chip(domain, irq + i,
+                                           hwirq + i,

drivers/pinctrl/meson/irqchip-gpio-meson.c line 211

Quoted 8 lines

drivers/pinctrl/meson/irqchip-gpio-meson.c new file +8 -0

+                                           &meson_irq_chip,
+                                           pc);
+
+             gic_data.param_count = 3;
+             gic_data.fwnode = domain->parent->fwnode;
+             gic_data.param[0] = 0; /* SPI */
+             gic_data.param[1] = pc->gic_irqs[index];
+             gic_data.param[1] = IRQ_TYPE_EDGE_RISING;

That feels quite wrong. Hardcoding the trigger like this and hoping for a set_type to set it right at a later time is just asking for trouble. Why can't you use the trigger type that has been provided by the interrupt descriptor?

Quoted 13 lines

drivers/pinctrl/meson/pinctrl-meson.c +13 -0

+static int meson_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+     struct meson_domain *domain = to_meson_domain(chip);
+     struct meson_pinctrl *pc = domain->pinctrl;
+     struct meson_bank *bank;
+     struct irq_fwspec irq_data;
+     unsigned int hwirq, irq;
+
+     hwirq = domain->data->pin_base + offset;
+
+     if (meson_get_bank(domain, hwirq, &bank))
+             return -ENXIO;
+

drivers/pinctrl/meson/pinctrl-meson.c static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) · line 560

Quoted 5 lines

drivers/pinctrl/meson/pinctrl-meson.c +5 -0

+     irq_data.param_count = 2;
+     irq_data.param[0] = hwirq;
+
+     /* dummy. It will be changed later in meson_irq_set_type */
+     irq_data.param[1] = IRQ_TYPE_EDGE_RISING;

Blah. Worse than I though... How do you end-up here? Why can't you obtain the corresponding of_phandle_args instead of making things up?

This looks mad. Do you really need this?

Quoted 26 lines · Marc Zyngier

Quoted 25 lines · Carlo Caione

From: Carlo Caione <[email protected]>

drivers/pinctrl/meson/irqchip-gpio-meson.c new file +23 -0

+static int meson_irq_domain_alloc(struct irq_domain *domain, unsigned int irq,
+                               unsigned int nr_irqs, void *arg)
+{
+     struct meson_pinctrl *pc = domain->host_data;
+     struct irq_fwspec *irq_data = arg;
+     struct irq_fwspec gic_data;
+     irq_hw_number_t hwirq;
+     int index, ret, i;
+
+     if (irq_data->param_count != 2)
+             return -EINVAL;
+
+     hwirq = irq_data->param[0];
+     dev_dbg(pc->dev, "%s irq %d, nr %d, hwirq %lu\n",
+                     __func__, irq, nr_irqs, hwirq);
+
+     for (i = 0; i < nr_irqs; i++) {
+             index = meson_map_gic_irq(domain, hwirq + i);
+             if (index < 0)
+                     return index;
+
+             irq_domain_set_hwirq_and_chip(domain, irq + i,
+                                           hwirq + i,

Quoted 8 lines

drivers/pinctrl/meson/irqchip-gpio-meson.c line 211

Quoted 8 lines

drivers/pinctrl/meson/irqchip-gpio-meson.c new file +8 -0

+                                           &meson_irq_chip,
+                                           pc);
+
+             gic_data.param_count = 3;
+             gic_data.fwnode = domain->parent->fwnode;
+             gic_data.param[0] = 0; /* SPI */
+             gic_data.param[1] = pc->gic_irqs[index];
+             gic_data.param[1] = IRQ_TYPE_EDGE_RISING;

Oh, this should be gic_data.param[2]. Just noticed.

Quoted 4 lines

That feels quite wrong. Hardcoding the trigger like this and hoping for a set_type to set it right at a later time is just asking for trouble. Why can't you use the trigger type that has been provided by the interrupt descriptor?

In v2 I had the set of fwspec to track number and trigger type of the IRQ, so it was straightforward. With this patch I have moved away from that solution (as you suggested) and I'm using the 'amlogic,irqs-gpio' parameter to track down the IRQ numbers (but not the trigger type). It's the same solution we have in drivers/irqchip/irq-crossbar.c where the trigger type is hardcoded in allocate_gic_irq().
If I need to save both the IRQ and the trigger type at this point I wonder if it's better to go back to the set of fwspec or convert the fwspec to of_phandle_args and save that.

Quoted 13 lines

Quoted 13 lines

drivers/pinctrl/meson/pinctrl-meson.c +13 -0

+static int meson_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+     struct meson_domain *domain = to_meson_domain(chip);
+     struct meson_pinctrl *pc = domain->pinctrl;
+     struct meson_bank *bank;
+     struct irq_fwspec irq_data;
+     unsigned int hwirq, irq;
+
+     hwirq = domain->data->pin_base + offset;
+
+     if (meson_get_bank(domain, hwirq, &bank))
+             return -ENXIO;
+

Quoted 8 lines

drivers/pinctrl/meson/pinctrl-meson.c static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) · line 560

Quoted 5 lines

drivers/pinctrl/meson/pinctrl-meson.c +5 -0

+     irq_data.param_count = 2;
+     irq_data.param[0] = hwirq;
+
+     /* dummy. It will be changed later in meson_irq_set_type */
+     irq_data.param[1] = IRQ_TYPE_EDGE_RISING;

Blah. Worse than I though... How do you end-up here? Why can't you obtain the corresponding of_phandle_args instead of making things up?

because I do not have a of_phandle. This is basically the .to_irq hook of the gpio_chip. This code is being called programmatically from the gpiolib. No DTS/OF involved here.

Quoted 1 line

This looks mad. Do you really need this?

Well, I'm open to any suggestion on how improve this mess.

Quoted 3 lines · Carlo Caione

Quoted 2 lines · Marc Zyngier

Quoted 1 line · Carlo Caione

From: Carlo Caione <[email protected]>

Quoted 9 lines

In v2 I had the set of fwspec to track number and trigger type of the IRQ, so it was straightforward. With this patch I have moved away from that solution (as you suggested) and I'm using the 'amlogic,irqs-gpio' parameter to track down the IRQ numbers (but not the trigger type). It's the same solution we have in drivers/irqchip/irq-crossbar.c where the trigger type is hardcoded in allocate_gic_irq().
If I need to save both the IRQ and the trigger type at this point I wonder if it's better to go back to the set of fwspec or convert the fwspec to of_phandle_args and save that.

No. This should come from the interrupt specifier you are getting from the device. You should never make up that information.

Your amlogic,irqs-gpio property gives you a list of downstream interrupts. The device connected to your pinctrl HW provides you with the upstream interrupt number (which you will map to one of your downstream IRQ) and crucially the trigger type. Please look at how the TI cross bar works (again).

Quoted 22 lines

Quoted 13 lines

Quoted 13 lines

drivers/pinctrl/meson/pinctrl-meson.c +13 -0

+static int meson_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+     struct meson_domain *domain = to_meson_domain(chip);
+     struct meson_pinctrl *pc = domain->pinctrl;
+     struct meson_bank *bank;
+     struct irq_fwspec irq_data;
+     unsigned int hwirq, irq;
+
+     hwirq = domain->data->pin_base + offset;
+
+     if (meson_get_bank(domain, hwirq, &bank))
+             return -ENXIO;
+

Quoted 8 lines

drivers/pinctrl/meson/pinctrl-meson.c static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) · line 560

Quoted 5 lines

drivers/pinctrl/meson/pinctrl-meson.c +5 -0

+     irq_data.param_count = 2;
+     irq_data.param[0] = hwirq;
+
+     /* dummy. It will be changed later in meson_irq_set_type */
+     irq_data.param[1] = IRQ_TYPE_EDGE_RISING;

Blah. Worse than I though... How do you end-up here? Why can't you obtain the corresponding of_phandle_args instead of making things up?

Quoted 7 lines

because I do not have a of_phandle. This is basically the .to_irq hook of the gpio_chip. This code is being called programmatically from the gpiolib. No DTS/OF involved here.

Quoted 1 line

This looks mad. Do you really need this?

Well, I'm open to any suggestion on how improve this mess.

The question to answer is: in what circumstances do you have to convert a GPIO into an IRQ at runtime? The only case should be "when you discover a device having an interrupt pointing to your pinctrl". And in this case, you have all the information to reconfigure the HW and assign the interrupt.

I really don't get why you want or need to involve gpiolib in this.

Quoted 4 lines · Marc Zyngier

Quoted 3 lines · Carlo Caione

Quoted 2 lines · Marc Zyngier

Quoted 1 line · Carlo Caione

From: Carlo Caione <[email protected]>

[...]

Quoted 10 lines

Quoted 9 lines

In v2 I had the set of fwspec to track number and trigger type of the IRQ, so it was straightforward. With this patch I have moved away from that solution (as you suggested) and I'm using the 'amlogic,irqs-gpio' parameter to track down the IRQ numbers (but not the trigger type). It's the same solution we have in drivers/irqchip/irq-crossbar.c where the trigger type is hardcoded in allocate_gic_irq().
If I need to save both the IRQ and the trigger type at this point I wonder if it's better to go back to the set of fwspec or convert the fwspec to of_phandle_args and save that.

Quoted 8 lines

No. This should come from the interrupt specifier you are getting from the device. You should never make up that information.

Your amlogic,irqs-gpio property gives you a list of downstream interrupts. The device connected to your pinctrl HW provides you with the upstream interrupt number (which you will map to one of your downstream IRQ) and crucially the trigger type. Please look at how the TI cross bar works (again).

Ok, this definitely makes sense and I'm going to fix it in the next revision, thanks for the explanation. Still I fail to see how the TI cross bar driver is actually doing what you are suggesting here. If I'm correctly reading the code here
http://lxr.free-electrons.com/source/drivers/irqchip/irq-crossbar.c#L101
the driver is hardcoding the trigger type for the downstream IRQ to be passed to the GIC code. But probably I'm missing something obvious.

Quoted 30 lines

Quoted 22 lines

Quoted 13 lines

Quoted 13 lines

drivers/pinctrl/meson/pinctrl-meson.c +13 -0

+static int meson_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+     struct meson_domain *domain = to_meson_domain(chip);
+     struct meson_pinctrl *pc = domain->pinctrl;
+     struct meson_bank *bank;
+     struct irq_fwspec irq_data;
+     unsigned int hwirq, irq;
+
+     hwirq = domain->data->pin_base + offset;
+
+     if (meson_get_bank(domain, hwirq, &bank))
+             return -ENXIO;
+

Quoted 8 lines

drivers/pinctrl/meson/pinctrl-meson.c static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) · line 560

Quoted 5 lines

drivers/pinctrl/meson/pinctrl-meson.c +5 -0

+     irq_data.param_count = 2;
+     irq_data.param[0] = hwirq;
+
+     /* dummy. It will be changed later in meson_irq_set_type */
+     irq_data.param[1] = IRQ_TYPE_EDGE_RISING;

Blah. Worse than I though... How do you end-up here? Why can't you obtain the corresponding of_phandle_args instead of making things up?

Quoted 7 lines

because I do not have a of_phandle. This is basically the .to_irq hook of the gpio_chip. This code is being called programmatically from the gpiolib. No DTS/OF involved here.

Quoted 1 line

This looks mad. Do you really need this?

Well, I'm open to any suggestion on how improve this mess.

Quoted 7 lines

The question to answer is: in what circumstances do you have to convert a GPIO into an IRQ at runtime? The only case should be "when you discover a device having an interrupt pointing to your pinctrl". And in this case, you have all the information to reconfigure the HW and assign the interrupt.

I really don't get why you want or need to involve gpiolib in this.

Again probably I'm missing something (and Linus probably could help here) but the only place I see the .to_irq hook (that is meson_gpio_to_irq() in the driver code) being called is from gpiod_to_irq() function in the gpiolib code.

One practical case in which that code path is involved is when (for example) I have something like 'cd-gpios = <&gpio GPIOX 0>;' for the card detection IRQ in the MMC node and in this case I fail to see an easy way to get the trigger type without touching the MMC / gpiolib code (any idea?).
This function is not called at all when in the DTS I explicitly have the interrupt specifier defined using the 'interrupts = <...>' property and in that case I have all the information I need to map the downstream IRQ.

From: Carlo Caione <[email protected]>

Extend the pinctrl binding documentation with the support for external GPIO interrupts.

Signed-off-by Carlo Caione <[email protected]>

Signed-off-by Beniamino Galvani <[email protected]>

---
 Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt | 11 +++++++++++
 1 file changed, 11 insertions(+)

Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +6 -0

index 3f6a524..de669ce 100644
@@ -3,6 +3,12 @@
 Required properties for the root node:
  - compatible: "amlogic,meson8-pinctrl" or "amlogic,meson8b-pinctrl"
  - reg: address and size of registers controlling irq functionality
+ - reg-names: should be "irq"
+ - interrupt-controller: marks the device node as an interrupt controller
+ - #interrupt-cells: should be 2. The first cell is the GPIO number. The
+		     second cell is used to specify trigger type.
+ - amlogic,irqs-gpio: specifies the GPIO IRQ numbers on the GIC (GPIO_IRQ#)
+ - interrupt-parent: specifies the parent interrupt controller.
 
 === GPIO sub-nodes ===
 

Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +2 -0

+		interrupt-controller;
+		#interrupt-cells = <2>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;

Signature · 1 line

2.5.0

Quoted 30 lines · Carlo Caione

From: Carlo Caione <[email protected]>

Extend the pinctrl binding documentation with the support for external GPIO interrupts.

Signed-off-by Carlo Caione <[email protected]>

Signed-off-by Beniamino Galvani <[email protected]>

---
 Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt | 11 +++++++++++
 1 file changed, 11 insertions(+)

Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +6 -0

index 3f6a524..de669ce 100644
@@ -3,6 +3,12 @@
 Required properties for the root node:
  - compatible: "amlogic,meson8-pinctrl" or "amlogic,meson8b-pinctrl"
  - reg: address and size of registers controlling irq functionality
+ - reg-names: should be "irq"
+ - interrupt-controller: marks the device node as an interrupt controller
+ - #interrupt-cells: should be 2. The first cell is the GPIO number. The
+                  second cell is used to specify trigger type.
+ - amlogic,irqs-gpio: specifies the GPIO IRQ numbers on the GIC (GPIO_IRQ#)
+ - interrupt-parent: specifies the parent interrupt controller.
 
 === GPIO sub-nodes ===
 

@@ -46,7 +52,12 @@ pinctrl-bindings.txt
 

Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt pinctrl-bindings.txt · line 58

Quoted 6 lines

Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +3 -0

      pinctrl: pinctrl at c1109880 {
              compatible = "amlogic,meson8-pinctrl";
+             reg-names = "irq";
              reg = <0xc1109880 0x10>;
+             interrupt-parent = <&gic>;
+             amlogic,irqs-gpio = <64 65 66 67 68 69 70 71>;

Can't you just use "interrupts" here?

From: Carlo Caione <[email protected]>

In Meson SoCs we have 8 independent GPIO interrupts that can be programmed to use any of the GPIOs in the chip as interrupt source.

These GPIOs are managed by GIC but they can be conditioned (and enabled) by some registers external to the GIC.

GPIOs |--[mux1 or mux2]--[polarity]--[filter]--[edge_select]--> GIC

Changelog:

* V2:
- Introduced .irq_request_resources() and .irq_release_resources()
- s/virq/irq/ and s/pin/hwirq/
- Moved to the new irq_fwspec

* V3:
- EXPORT_SYMBOL_GPL for of_irq_find_parent()
- split GPIO management and irqchip side
- the GIC IRQs list is not kept as set of fwspecs. it's now a regular integer array.
- irq_of_phandle_args_to_fwspec discarded