imx: mx7dsabresd: Add QSPI support

PATCH New Peng Fan 4 participants 6 messages Nov 30, 2015 – Dec 4, 2015

Share & tools

Peng Fan

author

2015-11-30 09:45 UTC #0 lore raw

PATCH 1/1 imx: mx7dsabresd: Add QSPI support

Support qspi flashes for mx7dsabresd
1. introduce pin mux settings
2. enable qspi clock
3. introduce related macro definitions

Default QSPI is not enabled, since we need hardware rework to use QSPI, see SPF-28590, page 9:
"
QSPI signals are muxed with EPDC_D[7:0]
When using QSPI: de-populate R388-R391, R396-R399
populate R392-R395, R299, R300
"

After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi flashes can be deteced and read/erase/write. Log info:
"
=> sf probe
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB => sf read 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Read: OK
=> sf erase 0 0x4000000
SF: 67108864 bytes @ 0x0 Erased: OK
=> sf write 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Written: OK
"

Signed-off-by Peng Fan <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Fabio Estevam <[email protected]>

Cc Adrian Alonso <[email protected]>

---
 board/freescale/mx7dsabresd/mx7dsabresd.c | 30 ++++++++++++++++++++++++++++++
 include/configs/mx7dsabresd.h             | 15 +++++++++++++++
 2 files changed, 45 insertions(+)

board/freescale/mx7dsabresd/mx7dsabresd.c +30 -0

index 6c863da..f8ae973 100644
@@ -44,6 +44,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
 	PAD_CTL_DSE_3P3V_49OHM)
 
+#define QSPI_PAD_CTRL	\
+	(PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 /* I2C1 for PMIC */

@@ -455,6 +458,29 @@ int board_phy_config(struct phy_device *phydev)
 }
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+static iomux_v3_cfg_t const quadspi_pads[] = {
+	MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+};
+
+int board_qspi_init(void)
+{
+	/* Set the iomux */
+	imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+					 ARRAY_SIZE(quadspi_pads));
+
+	/* Set the clock */
+	set_clk_qspi();
+
+	return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();

@@ -481,6 +507,10 @@ int board_init(void)
 	setup_lcd();
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
 	return 0;
 }

include/configs/mx7dsabresd.h +15 -0

index cc98547..22e515c 100644
@@ -236,4 +236,19 @@
 #define CONFIG_VIDEO_BMP_LOGO
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		40000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#define FSL_QSPI_FLASH_NUM		1
+#define FSL_QSPI_FLASH_SIZE		SZ_64M
+#define QSPI0_BASE_ADDR			QSPI1_IPS_BASE_ADDR
+#define QSPI0_AMBA_BASE			QSPI0_ARB_BASE_ADDR
+#endif
+
 #endif	/* __CONFIG_H */

Signature · 1 line

2.6.2

Stefano Babic

2015-11-30 10:01 UTC #1 lore raw

PATCH 1/1 imx: mx7dsabresd: Add QSPI support

Quoted 107 lines · Peng Fan

Support qspi flashes for mx7dsabresd
1. introduce pin mux settings
2. enable qspi clock
3. introduce related macro definitions
Default QSPI is not enabled, since we need hardware rework to use QSPI, see SPF-28590, page 9:
"
QSPI signals are muxed with EPDC_D[7:0]
When using QSPI: de-populate R388-R391, R396-R399
populate R392-R395, R299, R300
"
After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi flashes can be deteced and read/erase/write. Log info:
"
=> sf probe
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB => sf read 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Read: OK
=> sf erase 0 0x4000000
SF: 67108864 bytes @ 0x0 Erased: OK
=> sf write 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Written: OK
"
Signed-off-by Peng Fan <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Adrian Alonso <[email protected]>
---
 board/freescale/mx7dsabresd/mx7dsabresd.c | 30 ++++++++++++++++++++++++++++++
 include/configs/mx7dsabresd.h             | 15 +++++++++++++++
 2 files changed, 45 insertions(+)
board/freescale/mx7dsabresd/mx7dsabresd.c +30 -0
index 6c863da..f8ae973 100644
@@ -44,6 +44,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
 	PAD_CTL_DSE_3P3V_49OHM)
 
+#define QSPI_PAD_CTRL	\
+	(PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 /* I2C1 for PMIC */
@@ -455,6 +458,29 @@ int board_phy_config(struct phy_device *phydev)
 }
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+static iomux_v3_cfg_t const quadspi_pads[] = {
+	MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+};
+
+int board_qspi_init(void)
+{
+	/* Set the iomux */
+	imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+					 ARRAY_SIZE(quadspi_pads));
+
+	/* Set the clock */
+	set_clk_qspi();
+
+	return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -481,6 +507,10 @@ int board_init(void)
 	setup_lcd();
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
 	return 0;
 }
 
include/configs/mx7dsabresd.h +6 -0
index cc98547..22e515c 100644
@@ -236,4 +236,19 @@
 #define CONFIG_VIDEO_BMP_LOGO
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_BUS		0

include/configs/mx7dsabresd.h line 254

Quoted 10 lines

include/configs/mx7dsabresd.h +9 -0

+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		40000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#define FSL_QSPI_FLASH_NUM		1
+#define FSL_QSPI_FLASH_SIZE		SZ_64M
+#define QSPI0_BASE_ADDR			QSPI1_IPS_BASE_ADDR
+#define QSPI0_AMBA_BASE			QSPI0_ARB_BASE_ADDR
+#endif
+
 #endif	/* __CONFIG_H */

Reviewed-by Stefano Babic <[email protected]>

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Jagan Teki

2015-12-03 11:51 UTC #2 lore raw

PATCH 1/1 imx: mx7dsabresd: Add QSPI support

Quoted 86 lines · Stefano Babic

Quoted 85 lines · Peng Fan
Support qspi flashes for mx7dsabresd
1. introduce pin mux settings
2. enable qspi clock
3. introduce related macro definitions
Default QSPI is not enabled, since we need hardware rework to use QSPI, see SPF-28590, page 9:
"
QSPI signals are muxed with EPDC_D[7:0]
When using QSPI: de-populate R388-R391, R396-R399
populate R392-R395, R299, R300
"
After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi flashes can be deteced and read/erase/write. Log info:
"
=> sf probe
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB => sf read 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Read: OK
=> sf erase 0 0x4000000
SF: 67108864 bytes @ 0x0 Erased: OK
=> sf write 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Written: OK
"
Signed-off-by Peng Fan <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Adrian Alonso <[email protected]>
---
 board/freescale/mx7dsabresd/mx7dsabresd.c | 30 ++++++++++++++++++++++++++++++
 include/configs/mx7dsabresd.h             | 15 +++++++++++++++
 2 files changed, 45 insertions(+)
board/freescale/mx7dsabresd/mx7dsabresd.c +26 -0
index 6c863da..f8ae973 100644
@@ -44,6 +44,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
      PAD_CTL_DSE_3P3V_49OHM)
 
+#define QSPI_PAD_CTRL        \
+     (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 /* I2C1 for PMIC */
@@ -455,6 +458,29 @@ int board_phy_config(struct phy_device *phydev)
 }
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+static iomux_v3_cfg_t const quadspi_pads[] = {
+     MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+     MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+     MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+     MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+     MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+     MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+};
+
+int board_qspi_init(void)
+{
+     /* Set the iomux */
+     imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+                                      ARRAY_SIZE(quadspi_pads));
+
+     /* Set the clock */
+     set_clk_qspi();
+
+     return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
      setup_iomux_uart();
@@ -481,6 +507,10 @@ int board_init(void)
      setup_lcd();
 #endif
 

Quoted 3 lines

board/freescale/mx7dsabresd/mx7dsabresd.c int board_init(void) · line 512
Quoted 3 lines
board/freescale/mx7dsabresd/mx7dsabresd.c +3 -0
+#ifdef CONFIG_FSL_QSPI
+     board_qspi_init();
+#endif

Can't we do this on drivers/spi/fsl_qspi.c ?

Quoted 23 lines

board/freescale/mx7dsabresd/mx7dsabresd.c +1 -0

+
      return 0;
 }

include/configs/mx7dsabresd.h +11 -0

index cc98547..22e515c 100644
@@ -236,4 +236,19 @@
 #define CONFIG_VIDEO_BMP_LOGO
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_BUS                0
+#define CONFIG_SF_DEFAULT_CS         0
+#define CONFIG_SF_DEFAULT_SPEED              40000000
+#define CONFIG_SF_DEFAULT_MODE               SPI_MODE_0
+#define FSL_QSPI_FLASH_NUM           1
+#define FSL_QSPI_FLASH_SIZE          SZ_64M

Quoted 9 lines

include/configs/mx7dsabresd.h line 254

Quoted 6 lines

include/configs/mx7dsabresd.h +4 -0

+#define QSPI0_BASE_ADDR                      QSPI1_IPS_BASE_ADDR
+#define QSPI0_AMBA_BASE                      QSPI0_ARB_BASE_ADDR
+#endif
+
 #endif       /* __CONFIG_H */

Reviewed-by Stefano Babic <[email protected]>

thanks!

Signature · 1 line

Jagan.

Peng Fan

2015-12-04 01:11 UTC #3 lore raw

PATCH 1/1 imx: mx7dsabresd: Add QSPI support

Hi Jagan,

Quoted 87 lines · Jagan Teki

Quoted 86 lines · Stefano Babic
Quoted 85 lines · Peng Fan
Support qspi flashes for mx7dsabresd
1. introduce pin mux settings
2. enable qspi clock
3. introduce related macro definitions
Default QSPI is not enabled, since we need hardware rework to use QSPI, see SPF-28590, page 9:
"
QSPI signals are muxed with EPDC_D[7:0]
When using QSPI: de-populate R388-R391, R396-R399
populate R392-R395, R299, R300
"
After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi flashes can be deteced and read/erase/write. Log info:
"
=> sf probe
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB => sf read 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Read: OK
=> sf erase 0 0x4000000
SF: 67108864 bytes @ 0x0 Erased: OK
=> sf write 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Written: OK
"
Signed-off-by Peng Fan <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Adrian Alonso <[email protected]>
---
 board/freescale/mx7dsabresd/mx7dsabresd.c | 30 ++++++++++++++++++++++++++++++
 include/configs/mx7dsabresd.h             | 15 +++++++++++++++
 2 files changed, 45 insertions(+)
board/freescale/mx7dsabresd/mx7dsabresd.c +26 -0
index 6c863da..f8ae973 100644
@@ -44,6 +44,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
      PAD_CTL_DSE_3P3V_49OHM)
 
+#define QSPI_PAD_CTRL        \
+     (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 /* I2C1 for PMIC */
@@ -455,6 +458,29 @@ int board_phy_config(struct phy_device *phydev)
 }
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+static iomux_v3_cfg_t const quadspi_pads[] = {
+     MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+     MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+     MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+     MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+     MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+     MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+};
+
+int board_qspi_init(void)
+{
+     /* Set the iomux */
+     imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+                                      ARRAY_SIZE(quadspi_pads));
+
+     /* Set the clock */
+     set_clk_qspi();
+
+     return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
      setup_iomux_uart();
@@ -481,6 +507,10 @@ int board_init(void)
      setup_lcd();
 #endif
 

Quoted 5 lines

Quoted 3 lines
board/freescale/mx7dsabresd/mx7dsabresd.c int board_init(void) · line 512
Quoted 3 lines
board/freescale/mx7dsabresd/mx7dsabresd.c +3 -0
+#ifdef CONFIG_FSL_QSPI
+     board_qspi_init();
+#endif
Can't we do this on drivers/spi/fsl_qspi.c ?

Not for now. i.MX6/7 does not support to use device tree now, we do not have pinmux and clk info in driver code. In future, when pinmux and clk can be extracted using dtb, this code can be moved to fsl_qspi.c.

Regards,
Peng.

Quoted 37 lines

Quoted 24 lines

board/freescale/mx7dsabresd/mx7dsabresd.c +1 -0

+
      return 0;
 }

include/configs/mx7dsabresd.h +11 -0

index cc98547..22e515c 100644
@@ -236,4 +236,19 @@
 #define CONFIG_VIDEO_BMP_LOGO
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_BUS                0
+#define CONFIG_SF_DEFAULT_CS         0
+#define CONFIG_SF_DEFAULT_SPEED              40000000
+#define CONFIG_SF_DEFAULT_MODE               SPI_MODE_0
+#define FSL_QSPI_FLASH_NUM           1
+#define FSL_QSPI_FLASH_SIZE          SZ_64M

Quoted 9 lines

include/configs/mx7dsabresd.h line 254

Quoted 6 lines

include/configs/mx7dsabresd.h +4 -0

+#define QSPI0_BASE_ADDR                      QSPI1_IPS_BASE_ADDR
+#define QSPI0_AMBA_BASE                      QSPI0_ARB_BASE_ADDR
+#endif
+
 #endif       /* __CONFIG_H */

Reviewed-by Stefano Babic <[email protected]>

thanks!

Signature · 1 line

Jagan.

Jagan Teki

2015-12-04 04:30 UTC #4 lore raw

PATCH 1/1 imx: mx7dsabresd: Add QSPI support

Quoted 95 lines · Peng Fan

Hi Jagan,
Quoted 87 lines · Jagan Teki
Quoted 86 lines · Stefano Babic
Quoted 85 lines · Peng Fan
Support qspi flashes for mx7dsabresd
1. introduce pin mux settings
2. enable qspi clock
3. introduce related macro definitions
Default QSPI is not enabled, since we need hardware rework to use QSPI, see SPF-28590, page 9:
"
QSPI signals are muxed with EPDC_D[7:0]
When using QSPI: de-populate R388-R391, R396-R399
populate R392-R395, R299, R300
"
After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi flashes can be deteced and read/erase/write. Log info:
"
=> sf probe
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB => sf read 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Read: OK
=> sf erase 0 0x4000000
SF: 67108864 bytes @ 0x0 Erased: OK
=> sf write 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Written: OK
"
Signed-off-by Peng Fan <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Adrian Alonso <[email protected]>
---
 board/freescale/mx7dsabresd/mx7dsabresd.c | 30 ++++++++++++++++++++++++++++++
 include/configs/mx7dsabresd.h             | 15 +++++++++++++++
 2 files changed, 45 insertions(+)
board/freescale/mx7dsabresd/mx7dsabresd.c +26 -0
index 6c863da..f8ae973 100644
@@ -44,6 +44,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
      PAD_CTL_DSE_3P3V_49OHM)
 
+#define QSPI_PAD_CTRL        \
+     (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 /* I2C1 for PMIC */
@@ -455,6 +458,29 @@ int board_phy_config(struct phy_device *phydev)
 }
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+static iomux_v3_cfg_t const quadspi_pads[] = {
+     MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+     MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+     MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+     MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+     MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+     MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+};
+
+int board_qspi_init(void)
+{
+     /* Set the iomux */
+     imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+                                      ARRAY_SIZE(quadspi_pads));
+
+     /* Set the clock */
+     set_clk_qspi();
+
+     return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
      setup_iomux_uart();
@@ -481,6 +507,10 @@ int board_init(void)
      setup_lcd();
 #endif
 
Quoted 5 lines
Quoted 3 lines
board/freescale/mx7dsabresd/mx7dsabresd.c int board_init(void) · line 512
Quoted 3 lines
board/freescale/mx7dsabresd/mx7dsabresd.c +3 -0
+#ifdef CONFIG_FSL_QSPI
+     board_qspi_init();
+#endif
Can't we do this on drivers/spi/fsl_qspi.c ?

Quoted 39 lines

Regards,
Peng.

Quoted 32 lines

Quoted 20 lines

board/freescale/mx7dsabresd/mx7dsabresd.c +1 -0

+
      return 0;
 }

include/configs/mx7dsabresd.h +6 -0

index cc98547..22e515c 100644
@@ -236,4 +236,19 @@
 #define CONFIG_VIDEO_BMP_LOGO
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_BUS                0

include/configs/mx7dsabresd.h line 254

Quoted 10 lines

include/configs/mx7dsabresd.h +9 -0

+#define CONFIG_SF_DEFAULT_CS         0
+#define CONFIG_SF_DEFAULT_SPEED              40000000
+#define CONFIG_SF_DEFAULT_MODE               SPI_MODE_0
+#define FSL_QSPI_FLASH_NUM           1
+#define FSL_QSPI_FLASH_SIZE          SZ_64M
+#define QSPI0_BASE_ADDR                      QSPI1_IPS_BASE_ADDR
+#define QSPI0_AMBA_BASE                      QSPI0_ARB_BASE_ADDR
+#endif
+
 #endif       /* __CONFIG_H */

Reviewed-by Stefano Babic <[email protected]>

Reviewed-by Jagan Teki <[email protected]>

thanks!

Signature · 1 line

Jagan.

Jagan Teki

2015-12-04 08:48 UTC #5 lore raw

PATCH 1/1 imx: mx7dsabresd: Add QSPI support

Quoted 33 lines · Jagan Teki

Quoted 32 lines · Peng Fan
Hi Jagan,
Quoted 30 lines · Jagan Teki
Quoted 29 lines · Stefano Babic
Quoted 28 lines · Peng Fan
Support qspi flashes for mx7dsabresd
1. introduce pin mux settings
2. enable qspi clock
3. introduce related macro definitions
Default QSPI is not enabled, since we need hardware rework to use QSPI, see SPF-28590, page 9:
"
QSPI signals are muxed with EPDC_D[7:0]
When using QSPI: de-populate R388-R391, R396-R399
populate R392-R395, R299, R300
"
After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi flashes can be deteced and read/erase/write. Log info:
"
=> sf probe
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB => sf read 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Read: OK
=> sf erase 0 0x4000000
SF: 67108864 bytes @ 0x0 Erased: OK
=> sf write 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Written: OK
"

Quoted 8 lines

Quoted 6 lines
Quoted 6 lines
Quoted 6 lines
Quoted 4 lines
Signed-off-by Peng Fan <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Adrian Alonso <[email protected]>
Reviewed-by Stefano Babic <[email protected]>
Reviewed-by Jagan Teki <[email protected]>

Applied to u-boot-spi/master

thanks!

Signature · 1 line

Jagan.