arm-cci500: Workaround pmu_event_set_period

This patch refactors the CCI PMU driver code a little bit to make it easier share the code for enabling/disabling the CCI PMU. This will be used by the hooks to work around the special cases where writing to a counter is not always that easy(e.g, CCI-500)

No functional changes.

Cc Punit Agrawal <[email protected]>

Cc Mark Rutland <[email protected]>

Signed-off-by Suzuki K. Poulose <[email protected]>

---
 drivers/bus/arm-cci.c |   32 ++++++++++++++++++++++----------
 1 file changed, 22 insertions(+), 10 deletions(-)

drivers/bus/arm-cci.c +22 -10

index ee47e6b..f5793b9 100644
@@ -667,6 +667,26 @@ static u32 pmu_get_max_counters(void)
 		CCI_PMCR_NCNT_MASK) >> CCI_PMCR_NCNT_SHIFT;
 }
 
+/* Should be called with cci_pmu->hw_events->pmu_lock held */
+static void __cci_pmu_enable(void)
+{
+	u32 val;
+
+	/* Enable all the PMU counters. */
+	val = readl_relaxed(cci_ctrl_base + CCI_PMCR) | CCI_PMCR_CEN;
+	writel(val, cci_ctrl_base + CCI_PMCR);
+}
+
+/* Should be called with cci_pmu->hw_events->pmu_lock held */
+static void __cci_pmu_disable(void)
+{
+	u32 val;
+
+	/* Disable all the PMU counters. */
+	val = readl_relaxed(cci_ctrl_base + CCI_PMCR) & ~CCI_PMCR_CEN;
+	writel(val, cci_ctrl_base + CCI_PMCR);
+}
+
 static int pmu_get_event_idx(struct cci_pmu_hw_events *hw, struct perf_event *event)
 {
 	struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);

@@ -880,16 +900,12 @@ static void cci_pmu_enable(struct pmu *pmu)
 	struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events;
 	int enabled = bitmap_weight(hw_events->used_mask, cci_pmu->num_cntrs);
 	unsigned long flags;
-	u32 val;
 
 	if (!enabled)
 		return;
 
 	raw_spin_lock_irqsave(&hw_events->pmu_lock, flags);
-
-	/* Enable all the PMU counters. */
-	val = readl_relaxed(cci_ctrl_base + CCI_PMCR) | CCI_PMCR_CEN;
-	writel(val, cci_ctrl_base + CCI_PMCR);
+	__cci_pmu_enable();
 	raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags);
 
 }

@@ -899,13 +915,9 @@ static void cci_pmu_disable(struct pmu *pmu)
 	struct cci_pmu *cci_pmu = to_cci_pmu(pmu);
 	struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events;
 	unsigned long flags;
-	u32 val;
 
 	raw_spin_lock_irqsave(&hw_events->pmu_lock, flags);
-
-	/* Disable all the PMU counters. */
-	val = readl_relaxed(cci_ctrl_base + CCI_PMCR) & ~CCI_PMCR_CEN;
-	writel(val, cci_ctrl_base + CCI_PMCR);
+	__cci_pmu_disable();
 	raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags);
 }
 

Signature · 1 line

1.7.9.5

Add helper routines to get the counter status and the event programmed on it.

Cc Punit Agrawal <[email protected]>

Cc Mark Rutland <[email protected]>

Signed-off-by Suzuki K. Poulose <[email protected]>

---
Changes since V2:
- Rename pmu_counter_get_ctrl => pmu_counter_is_enabled()

---
 drivers/bus/arm-cci.c |   12 ++++++++++++
 1 file changed, 12 insertions(+)

drivers/bus/arm-cci.c +12 -0

index f5793b9..48936c8 100644
@@ -652,11 +652,23 @@ static void pmu_enable_counter(struct cci_pmu *cci_pmu, int idx)
 	pmu_write_register(cci_pmu, 1, idx, CCI_PMU_CNTR_CTRL);
 }
 
+static bool __maybe_unused
+pmu_counter_is_enabled(struct cci_pmu *cci_pmu, int idx)
+{
+	return (pmu_read_register(cci_pmu, idx, CCI_PMU_CNTR_CTRL) & 0x1) != 0;
+}
+
 static void pmu_set_event(struct cci_pmu *cci_pmu, int idx, unsigned long event)
 {
 	pmu_write_register(cci_pmu, event, idx, CCI_PMU_EVT_SEL);
 }
 
+static u32 __maybe_unused
+pmu_get_event(struct cci_pmu *cci_pmu, int idx)
+{
+	return pmu_read_register(cci_pmu, idx, CCI_PMU_EVT_SEL);
+}
+
 /*
  * Returns the number of programmable counters actually implemented
  * by the cci

Signature · 1 line

1.7.9.5

Adds helper routines to disable the counter controls for all the counters on the CCI PMU and restore it back, by preserving the original state in caller provided mask.

Cc Punit Agrawal <[email protected]>

Cc Mark Rutland <[email protected]>

Signed-off-by Suzuki K. Poulose <[email protected]>

---
Changes since V2:
- Rename the functions to pmu_restore_counters, pmu_disable_counters
- Added comment describing why we use a private mask

---
 drivers/bus/arm-cci.c |   38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

drivers/bus/arm-cci.c +12 -0

index 48936c8..91a9d5d 100644
@@ -669,6 +669,44 @@ pmu_get_event(struct cci_pmu *cci_pmu, int idx)
 	return pmu_read_register(cci_pmu, idx, CCI_PMU_EVT_SEL);
 }
 
+
+/*
+ * For all counters on the CCI-PMU, disable any 'enabled' counters,
+ * saving the changed counters in the mask, so that we can restore
+ * it later using pmu_restore_counters. The mask is private to the
+ * caller. We cannot rely on the used_mask maintained by the CCI_PMU
+ * as it only tells us if the counter is assigned to perf_event or not.
+ * The state of the perf_event cannot be locked by the PMU layer, hence
+ * we check the individual counter status (which can be locked by
+ * cci_pm->hw_events->pmu_lock).
+ */
+static void __maybe_unused

drivers/bus/arm-cci.c +7 -0

+{
+	int i;
+
+	for_each_set_bit(i, mask, cci_pmu->num_cntrs)
+		pmu_enable_counter(cci_pmu, i);
+}
+
 /*
  * Returns the number of programmable counters actually implemented
  * by the cci

Signature · 1 line

1.7.9.5

drivers/bus/arm-cci.c pmu_get_event(struct cci_pmu *cci_pmu, int idx) · line 693

Quoted 11 lines · Suzuki K. Poulose

drivers/bus/arm-cci.c +11 -0

+static void __maybe_unused
+pmu_disable_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
+{
+	int i;
+
+	for (i = 0; i < cci_pmu->num_cntrs; i++) {
+		if (pmu_counter_is_enabled(cci_pmu, i)) {
+			set_bit(i, mask);
+			pmu_disable_counter(cci_pmu, i);
+		} else
+			clear_bit(i, mask);

Can we not assume a clean mask to begin with?

drivers/bus/arm-cci.c pmu_get_event(struct cci_pmu *cci_pmu, int idx) · line 702

Quoted 10 lines

drivers/bus/arm-cci.c +9 -0

+	}
+}
+
+/*
+ * Restore the status of the counters. Reversal of the pmu_disable_counters().
+ * For each counter set in the mask, enable the counter back.
+ */
+static void __maybe_unused
+pmu_restore_counters(struct cci_pmu *cci_pmu, unsigned long *mask)

This would probably be better with s/restore/enable/ for consistency with pmu_disable_counters.

Other than that this looks fine to me.

Quoted 16 lines · Mark Rutland

drivers/bus/arm-cci.c pmu_get_event(struct cci_pmu *cci_pmu, int idx) · line 693

Quoted 11 lines · Suzuki K. Poulose

drivers/bus/arm-cci.c +11 -0

+static void __maybe_unused
+pmu_disable_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
+{
+	int i;
+
+	for (i = 0; i < cci_pmu->num_cntrs; i++) {
+		if (pmu_counter_is_enabled(cci_pmu, i)) {
+			set_bit(i, mask);
+			pmu_disable_counter(cci_pmu, i);
+		} else
+			clear_bit(i, mask);

Can we not assume a clean mask to begin with?

If we force the caller to pass a clean mask, yes we could. I am fine with either approach.

Quoted 13 lines

drivers/bus/arm-cci.c pmu_get_event(struct cci_pmu *cci_pmu, int idx) · line 702

Quoted 10 lines

drivers/bus/arm-cci.c +9 -0

+	}
+}
+
+/*
+ * Restore the status of the counters. Reversal of the pmu_disable_counters().
+ * For each counter set in the mask, enable the counter back.
+ */
+static void __maybe_unused
+pmu_restore_counters(struct cci_pmu *cci_pmu, unsigned long *mask)

This would probably be better with s/restore/enable/ for consistency with pmu_disable_counters.

I had thought as well, but then chose restore as we don't enable all the counters. Given that we pass a mask argument, it is fine to change it to enable and will do that in the next one.

The CCI PMU driver sets the event counter to the half of the maximum value(2^31) it can count before we start the counters via pmu_event_set_period(). This is done to give us the best chance to handle the overflow interrupt, taking care of extreme interrupt latencies.

However, CCI-500 comes with advanced power saving schemes, which disables the clock to the event counters unless the counters are enabled to count (PMCR.CEN). This prevents the driver from writing the period to the counters before starting them. Also, there is no way we can reset the individual event counter to 0 (PMCR.RST resets all the counters, losing their current readings). However the value of the counter is preserved and could be read back, when the counters are not enabled.

So we cannot reliably use the counters and compute the number of events generated during the sampling period since we don't have the value of the counter at start.

This patch works around this issue by changing writes to the counter with the following steps.

1) Disable all the counters (remembering any counters which were enabled)
2) Save the current event and program the target counter to count an invalid event, which by spec is guaranteed to not-generate any events.
3) Enable the target counter.
4) Enable the CCI PMU
5) Write to the target counter.
6) Disable the CCI PMU and the target counter
7) Restore the event back on the target counter.
8) Restore the status of the all the counters

Cc Punit Agrawal <[email protected]>

Cc Mark Rutland <[email protected]>

Signed-off-by Suzuki K. Poulose <[email protected]>

---
 drivers/bus/arm-cci.c |   47 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

drivers/bus/arm-cci.c +46 -0

index 88b612f..6020a02 100644
@@ -835,6 +835,52 @@ static void __pmu_write_counter(struct cci_pmu *cci_pmu, u32 value, int idx)
 	pmu_write_register(cci_pmu, value, idx, CCI_PMU_CNTR);
 }
 
+#ifdef CONFIG_ARM_CCI500_PMU
+
+/*
+ * CCI-500 has advanced power saving policies, which could gate the
+ * clocks to the PMU counters, which makes the writes to them ineffective.
+ * The only way to write to those counters is when the global counters
+ * are enabled and the particular counter is enabled.
+ *
+ * So we do the following :
+ *
+ * 1) Disable all the PMU counters, saving their current state
+ * 2) Save the programmed event, and write an invalid event code
+ *    to the event control register for the counter, so that the
+ *    counters are not modified.
+ * 3) Enable the counter control for the counter.
+ * 4) Enable the global PMU profiling
+ * 5) Set the counter value
+ * 6) Disable the counter, global PMU.
+ * 7) Restore the event in the target counter
+ * 8) Restore the status of the rest of the counters.
+ *
+ * We choose an event code which has very little chances of getting
+ * assigned a valid code for step(2). We use the highest possible
+ * event code (0x1f) for the master interface 0.
+ */
+#define CCI500_INVALID_EVENT	((CCI500_PORT_M0 << CCI500_PMU_EVENT_SOURCE_SHIFT) | \
+				 (CCI500_PMU_EVENT_CODE_MASK << CCI500_PMU_EVENT_CODE_SHIFT))
+static void cci500_pmu_write_counter(struct cci_pmu *cci_pmu, u32 value, int idx)
+{
+	unsigned long mask[BITS_TO_LONGS(cci_pmu->num_cntrs)];
+	u32 event;
+
+	pmu_disable_counters(cci_pmu, mask);
+	event = pmu_get_event(cci_pmu, idx);
+	pmu_set_event(cci_pmu, idx, CCI500_INVALID_EVENT);
+	pmu_enable_counter(cci_pmu, idx);
+	__cci_pmu_enable();
+	__pmu_write_counter(cci_pmu, value, idx);
+	__cci_pmu_disable();
+	pmu_disable_counter(cci_pmu, idx);
+	pmu_set_event(cci_pmu, idx, event);
+	pmu_restore_counters(cci_pmu, mask);
+}
+
+#endif	/* CONFIG_ARM_CCI500_PMU */
+
 static void pmu_write_counter(struct perf_event *event, u32 value)
 {
 	struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);

Quoted 4 lines · Suzuki K. Poulose

The CCI PMU driver sets the event counter to the half of the maximum value(2^31) it can count before we start the counters via pmu_event_set_period(). This is done to give us the best chance to handle the overflow interrupt, taking care of extreme interrupt latencies.

This should work, but it seems very heavyweight given we do it for each write.

Can we not amortize this by using the {start,commit,cancel}_txn hooks?

Either we can handle 1-4 and 6-8 in those, or we can copy everything into a shadow state and apply it all in one go at commit_txn time.

Quoted 7 lines · Mark Rutland

This should work, but it seems very heavyweight given we do it for each write.

Can we not amortize this by using the {start,commit,cancel}_txn hooks?

Either we can handle 1-4 and 6-8 in those, or we can copy everything into a shadow state and apply it all in one go at commit_txn time.

I took a look at it. The only worrying part is, if pmu->add() will be called outside *_txn().

from linux/perf_event.h:

/*
* Adds/Removes a counter to/from the PMU, can be done inside a
* transaction, see the ->*_txn() methods.
*

As of now it is only called within the transactions, but the comment somehow doesn't look like enforces it.

Quoted 11 lines · Mark Rutland

Quoted 4 lines · Suzuki K. Poulose

The CCI PMU driver sets the event counter to the half of the maximum value(2^31) it can count before we start the counters via pmu_event_set_period(). This is done to give us the best chance to handle the overflow interrupt, taking care of extreme interrupt latencies.

This should work, but it seems very heavyweight given we do it for each write.

Quoted 4 lines

Can we not amortize this by using the {start,commit,cancel}_txn hooks?

Either we can handle 1-4 and 6-8 in those, or we can copy everything into a shadow state and apply it all in one go at commit_txn time.

I took a look at it. The only worrying part is, if pmu->add() will be called outside *_txn().